API driver for OV7740 CMOS image sensor.
Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
Data Structures | |
| struct | _ov_reg |
| OV7740 register struture. More... | |
Macros | |
| #define | OV7740_AEC (0x10u) |
| #define | OV7740_AHSIZE (0x18u) |
| #define | OV7740_AHSTART (0x17u) |
| #define | OV7740_AVSIZE (0x1au) |
| #define | OV7740_AVSTART (0x19u) |
| #define | OV7740_BLUE_AVG (0x05u) |
| #define | OV7740_BLUE_GAIN (0x01u) |
| #define | OV7740_BPT (0x25u) |
| #define | OV7740_CLK (0x11u) |
| (OV7740_CLK) sysclk=XVCLK1 x PLLDIV / [(CLK[5:0]+1) x2 xPreDiv] More... | |
| #define | OV7740_CLK_DIVIDER(value) ((OV7740_CLK_DIVIDER_Msk & ((value) << OV7740_CLK_DIVIDER_Pos))) |
| #define | OV7740_CLK_DIVIDER_Msk (0x3fu << OV7740_CLK_DIVIDER_Pos) |
| (OV7740_CLK) Clock divider More... | |
| #define | OV7740_CLK_DIVIDER_Pos (0) |
| #define | OV7740_CLK_PLL(value) ((OV7740_CLK_PLL_Msk & ((value) << OV7740_CLK_PLL_Pos))) |
| #define | OV7740_CLK_PLL_Msk (0x3u << OV7740_CLK_PLL_Pos) |
| (OV7740_CLK) PLL setting - Changing this value is not recommanded More... | |
| #define | OV7740_CLK_PLL_Pos (6) |
| #define | OV7740_GAIN (0x00u) |
| Register definitions. More... | |
| #define | OV7740_GREEN_AVG (0x06u) |
| #define | OV7740_GREEN_GAIN (0x03u) |
| #define | OV7740_HAEC (0x0fu) |
| #define | OV7740_MIDH (0x1cu) |
| #define | OV7740_MIDH_DEFAULT (0x7fu << 0) |
| #define | OV7740_MIDL (0x1du) |
| #define | OV7740_MIDL_DEFAULT (0xa2u << 0) |
| #define | OV7740_PIDH (0x0au) |
| #define | OV7740_PIDH_DEFAULT (0x77u << 0) |
| #define | OV7740_PIDL (0x0bu) |
| #define | OV7740_PIDL_DEFAULT (0x40u << 0) |
| #define | OV7740_PIXEL_SHIFT (0x1bu) |
| #define | OV7740_RED_AVG (0x07u) |
| #define | OV7740_RED_GAIN (0x02u) |
| #define | OV7740_REG04 (0x04u) |
| #define | OV7740_REG0C (0x0c) |
| #define | OV7740_REG0C_BYTE_SWAP_DISABLE (0x0u << 3) |
| (OV7740_REG0C) output Y9,Y8...Y3,Y2,Y1,Y0 More... | |
| #define | OV7740_REG0C_BYTE_SWAP_ENABLE (0x1u << 3) |
| (OV7740_REG0C) output Y3,Y2...Y8,Y9,Y1,Y0 More... | |
| #define | OV7740_REG0C_BYTE_SWAP_Msk (0x1u << 3) |
| (OV7740_REG0C) High 8-bit MSB and LSB swap More... | |
| #define | OV7740_REG0C_FLIP_ENABLE (0x1u << 7) |
| (OV7740_REG0C) Flip enable More... | |
| #define | OV7740_REG0C_MAX_EXPOSURE(value) ((OV7740_REG0C_MAX_EXPOSURE_Msk & ((value) << OV7740_REG0C_MAX_EXPOSURE_Pos))) |
| #define | OV7740_REG0C_MAX_EXPOSURE_Msk (0x3u << OV7740_REG0C_MAX_EXPOSURE_Pos) |
| (OV7740_REG0C) Max exposure = frame length - limit x 2 More... | |
| #define | OV7740_REG0C_MAX_EXPOSURE_Pos (1) |
| #define | OV7740_REG0C_MIRROR_ENABLE (0x1u << 6) |
| (OV7740_REG0C) Mirror enable More... | |
| #define | OV7740_REG0C_YUV_SWAP_DISABLE (0x0u << 4) |
| (OV7740_REG0C) output YUYVYUYV More... | |
| #define | OV7740_REG0C_YUV_SWAP_ENABLE (0x1u << 4) |
| (OV7740_REG0C) output UYVYUYVY More... | |
| #define | OV7740_REG0C_YUV_SWAP_Msk (0x1u << 4) |
| (OV7740_REG0C) YUV output, Y <-> UV swap More... | |
| #define | OV7740_REG0D (0x0du) |
| #define | OV7740_REG0E (0x0eu) |
| #define | OV7740_REG0E_BLC_BLUE (0x2u << OV7740_REG0E_BLC_Pos) |
| (OV7740_REG0E) Select blue line as BLC line. More... | |
| #define | OV7740_REG0E_BLC_BOTH (0x3u << OV7740_REG0E_BLC_Pos) |
| (OV7740_REG0E) Select both blue line and red line as BLC line. More... | |
| #define | OV7740_REG0E_BLC_BOTH0 (0x0u << OV7740_REG0E_BLC_Pos) |
| (OV7740_REG0E) Select both blue line and red line as BLC line. More... | |
| #define | OV7740_REG0E_BLC_LINE_ELECTRICAL (0x0u << 7) |
| (OV7740_REG0E) Electrical BLC More... | |
| #define | OV7740_REG0E_BLC_LINE_Msk (0x1u << 7) |
| (OV7740_REG0E) BLC line selection More... | |
| #define | OV7740_REG0E_BLC_LINE_OPTICAL (0x1u << 7) |
| (OV7740_REG0E) Optical BLC More... | |
| #define | OV7740_REG0E_BLC_Msk (0x3u << OV7740_REG0E_BLC_Pos) |
| (OV7740_REG0E) BLC line selection More... | |
| #define | OV7740_REG0E_BLC_Pos (5) |
| #define | OV7740_REG0E_BLC_RED (0x1u << OV7740_REG0E_BLC_Pos) |
| (OV7740_REG0E) Select red line as BLC line. More... | |
| #define | OV7740_REG0E_OUTPUT_1X (0x0u << OV7740_REG0E_OUTPUT_Pos) |
| (OV7740_REG0E) 1x More... | |
| #define | OV7740_REG0E_OUTPUT_2X (0x1u << OV7740_REG0E_OUTPUT_Pos) |
| (OV7740_REG0E) 2x More... | |
| #define | OV7740_REG0E_OUTPUT_3X (0x2u << OV7740_REG0E_OUTPUT_Pos) |
| (OV7740_REG0E) 3x More... | |
| #define | OV7740_REG0E_OUTPUT_4X (0x3u << OV7740_REG0E_OUTPUT_Pos) |
| (OV7740_REG0E) 4x More... | |
| #define | OV7740_REG0E_OUTPUT_Msk (0x3u << OV7740_REG0E_OUTPUT_Pos) |
| (OV7740_REG0E) Output driving capability More... | |
| #define | OV7740_REG0E_OUTPUT_Pos (0) |
| #define | OV7740_REG0E_SLEEP_MODE (0x1u << 3) |
| (OV7740_REG0E) Sleep mode More... | |
| #define | OV7740_REG12 (0x12u) |
| #define | OV7740_REG12_CC656_MODE (0x1u << 5) |
| #define | OV7740_REG12_RAW_RGB (0x1u << 0) |
| #define | OV7740_REG12_RESET (0x1u << 7) |
| #define | OV7740_REG12_SENSOR_RAW (0x1u << 4) |
| #define | OV7740_REG12_VSKIP (0x1u << 6) |
| #define | OV7740_REG13 (0x13u) |
| #define | OV7740_REG13_AEC_FASTER (0x1u << 7) |
| (OV7740_REG13) Faster AEC correction More... | |
| #define | OV7740_REG13_AEC_Mask (0x1u << 7) |
| (OV7740_REG13) AEC speed selection More... | |
| #define | OV7740_REG13_AEC_NORMAL (0x0u << 7) |
| (OV7740_REG13) Normal More... | |
| #define | OV7740_REG13_AGC_AUTO (0x1u << 2) |
| #define | OV7740_REG13_AGC_MANUAL (0x0u << 2) |
| #define | OV7740_REG13_AGC_Msk (0x1u << 2) |
| (OV7740_REG13) AGC auto/manual control selection More... | |
| #define | OV7740_REG13_BANDING_DISABLE (0x0u << 5) |
| #define | OV7740_REG13_BANDING_ENABLE (0x1u << 5) |
| #define | OV7740_REG13_BANDING_Mask (0x1u << 5) |
| (OV7740_REG13) Banding enable More... | |
| #define | OV7740_REG13_BANDING_OPT_ENABLE (0x1u << 4) |
| (OV7740_REG13) Minimum exposure is allowed to be less than 1/120 or 1/100 second when banding filter is enabled More... | |
| #define | OV7740_REG13_BANDING_OPT_LIMITED (0x0u << 4) |
| (OV7740_REG13) Minimum exposure is limited to 1/120 or 1/100 second when banding filter is enabled More... | |
| #define | OV7740_REG13_BANDING_OPT_Msk (0x1u << 4) |
| (OV7740_REG13) Banding option More... | |
| #define | OV7740_REG13_EXPOSURE_AUTO (0x1u << 0) |
| #define | OV7740_REG13_EXPOSURE_MANUAL (0x0u << 0) |
| #define | OV7740_REG13_EXPOSURE_Msk (0x01u << 0) |
| (OV7740_REG13) Exposure auto/manual control selection More... | |
| #define | OV7740_REG13_FRAME_DROP_DISABLE (0x0u << 6) |
| #define | OV7740_REG13_FRAME_DROP_ENABLE (0x1u << 6) |
| #define | OV7740_REG13_FRAME_DROP_Mask (0x1u << 6) |
| (OV7740_REG13) Enable frame drop function More... | |
| #define | OV7740_REG13_LAEC_DISABLE (0x0u << 3) |
| #define | OV7740_REG13_LAEC_ENABLE (0x1u << 3) |
| #define | OV7740_REG13_LAEC_Msk (0x1u << 3) |
| (OV7740_REG13) LAEC enable More... | |
| #define | OV7740_REG13_WBAL_AUTO (0x1u << 1) |
| #define | OV7740_REG13_WBAL_MANUAL (0x0u << 1) |
| #define | OV7740_REG13_WBAL_Msk (0x1u << 1) |
| (OV7740_REG13) Auto white balance control selection More... | |
| #define | OV7740_REG14 (0x14u) |
| #define | OV7740_REG15 (0x15u) |
| #define | OV7740_REG15_CEIL_0 (0x0u << 4) |
| (OV7740_REG15) Up to 0 frames More... | |
| #define | OV7740_REG15_CEIL_1 (0x1u << 4) |
| (OV7740_REG15) Up to 1 frames More... | |
| #define | OV7740_REG15_CEIL_2 (0x2u << 4) |
| (OV7740_REG15) Up to 2 frames More... | |
| #define | OV7740_REG15_CEIL_3 (0x3u << 4) |
| (OV7740_REG15) Up to 3 frames More... | |
| #define | OV7740_REG15_CEIL_7 (0x7u << 4) |
| (OV7740_REG15) Up to 7 frames More... | |
| #define | OV7740_REG15_CEIL_Mask (0x3u << 4) |
| (OV7740_REG15) Ceiling of inserting frames More... | |
| #define | OV7740_REG15_ENABLE_NIGHT (0x1u << 7) |
| (OV7740_REG15) Enable inserting frames in night mode More... | |
| #define | OV7740_REG15_GAIN(value) ((OV7740_REG15_GAIN_Msk & ((value) << OV7740_REG15_GAIN_Pos))) |
| #define | OV7740_REG15_GAIN_Msk (0x3u << OV7740_REG15_GAIN_Pos) |
| (OV7740_REG15) AGC MSBs (digital gain) (LSBs in GAIN[7:0]) More... | |
| #define | OV7740_REG15_GAIN_Pos (0) |
| #define | OV7740_REG15_NIGHT_16X_GAIN (0x3u << 2) |
| (OV7740_REG15) 16x gain More... | |
| #define | OV7740_REG15_NIGHT_2X_GAIN (0x0u << 2) |
| (OV7740_REG15) 2x gain More... | |
| #define | OV7740_REG15_NIGHT_4X_GAIN (0x1u << 2) |
| (OV7740_REG15) 4x gain More... | |
| #define | OV7740_REG15_NIGHT_8X_GAIN (0x2u << 2) |
| (OV7740_REG15) 8x gain More... | |
| #define | OV7740_REG15_NIGHT_Mask (0x3u << 2) |
| (OV7740_REG15) Night mode triggering point More... | |
| #define | OV7740_REG16 (0x16u) |
| #define | OV7740_REG1E (0x1eu) |
| #define | OV7740_REG1E (0x1eu) |
| #define | OV7740_REG1F (0x1fu) |
| #define | OV7740_REG20 (0x20u) |
| #define | OV7740_REG21 (0x21u) |
| #define | OV7740_REG27 (0x27u) |
| #define | OV7740_REG27_BLACKSUN (0x1u << 7) |
| (OV7740_REG27) Black sun cancellation enable More... | |
| #define | OV7740_REG28 (0x28u) |
| #define | OV7740_REG28_HREF_Msk (0x1u << 4) |
| (OV7740_REG28) HREF polarity More... | |
| #define | OV7740_REG28_HREF_NEGATIVE (0x1u << 4) |
| (OV7740_REG28) Output negative HREF for data valid More... | |
| #define | OV7740_REG28_HREF_OUTPUT_HREF (0x0u << 6) |
| (OV7740_REG28) HREF More... | |
| #define | OV7740_REG28_HREF_OUTPUT_HSYNC (0x1u << 6) |
| (OV7740_REG28) HSYNC More... | |
| #define | OV7740_REG28_HREF_OUTPUT_Msk (0x1u << 6) |
| (OV7740_REG28) HREF pin output swap More... | |
| #define | OV7740_REG28_HREF_POSITIVE (0x0u << 4) |
| (OV7740_REG28) Output positive HREF More... | |
| #define | OV7740_REG28_HSYNC_Msk (0x1u << 5) |
| (OV7740_REG28) HSYNC polarity More... | |
| #define | OV7740_REG28_HSYNC_NEGATIVE (0x1u << 5) |
| (OV7740_REG28) Negative More... | |
| #define | OV7740_REG28_HSYNC_POSITIVE (0x0u << 5) |
| (OV7740_REG28) Positive More... | |
| #define | OV7740_REG28_OUTPUT_REVERSE (0x1u << 7) |
| (OV7740_REG28) Output data bit reverse option More... | |
| #define | OV7740_REG28_VSYNC_Msk (0x1u << 1) |
| (OV7740_REG28) VSYNC polarity More... | |
| #define | OV7740_REG28_VSYNC_NEGATIVE (0x1u << 1) |
| (OV7740_REG28) Negative More... | |
| #define | OV7740_REG28_VSYNC_OUTPUT_Msk (0x1u << 3) |
| (OV7740_REG28) No VSYNC output option More... | |
| #define | OV7740_REG28_VSYNC_OUTPUT_NONE (0x1u << 3) |
| (OV7740_REG28) No VSYNC output when frame drop More... | |
| #define | OV7740_REG28_VSYNC_OUTPUT_STILL (0x0u << 3) |
| (OV7740_REG28) Still output VSYNC when frame drop More... | |
| #define | OV7740_REG28_VSYNC_POSITIVE (0x1u << 0) |
| (OV7740_REG28) Positive More... | |
| #define | OV7740_REG65 (0x65u) |
| #define | OV7740_REG65_BIT_SWAP_Msk (0x1u << 3) |
| (OV7740_REG65) Output data bit swap option More... | |
| #define | OV7740_REG65_BIT_SWAP_NORMAL (0x0u << 3) |
| (OV7740_REG65) Output DATA[9:0] More... | |
| #define | OV7740_REG65_BIT_SWAP_REVERSE (0x1u << 3) |
| (OV7740_REG65) Output DATA[0:9] More... | |
| #define | OV7740_VPT (0x26u) |
| #define | OV7740_WPT (0x24u) |
| #define | OV7740_YUV422CTRL (0xd9u) |
| #define | OV7740_YUV422CTRL_CNV_OPT_AVERAGE (0x0u << 0) |
| (OV7740_YUV422CTRL) Average mode More... | |
| #define | OV7740_YUV422CTRL_CNV_OPT_DROP (0x1u << 0) |
| (OV7740_YUV422CTRL) Drop mode More... | |
| #define | OV7740_YUV422CTRL_CNV_OPT_Msk (0x1u << 0) |
| (OV7740_YUV422CTRL) cnv_opt More... | |
| #define | OV7740_YUV422CTRL_V_FIRST_Msk (0x1u << 1) |
| (OV7740_YUV422CTRL) v_first More... | |
| #define | OV7740_YUV422CTRL_V_FIRST_YUYV (0x0u << 1) |
| (OV7740_YUV422CTRL) Output line will be YUYV... More... | |
| #define | OV7740_YUV422CTRL_V_FIRST_YVYU (0x1u << 1) |
| (OV7740_YUV422CTRL) Output line will be YVYU... More... | |
| #define | OV_I2C_SENSOR_ADDRESS (0x42u >> 1) /* OV7740 -> 0x42 */ |
| Slave address of OMNIVISION chip. More... | |
| #define | OV_REG_TERM (0xffu) |
| Terminating list entry for register in configuration file. More... | |
| #define | OV_VAL_TERM (0xffu) |
| Terminating list entry for value in configuration file. More... | |
Typedefs | |
| typedef enum _e_ov7740_format | e_ov7740_format |
| Enumeration of different format which could be used by the 0V7740 sensor. More... | |
| typedef struct _ov_reg | ov_reg |
| OV7740 register struture. More... | |
Enumerations | |
| enum | _e_ov7740_format { QVGA_YUV422_10FPS, QVGA_YUV422_15FPS, QVGA_YUV422_20FPS, QVGA_YUV422_30FPS, QVGA_RGB888, QQVGA_YUV422, QQVGA_RGB888, TEST_PATTERN, VGA_YUV422_20FPS } |
| Enumeration of different format which could be used by the 0V7740 sensor. More... | |
Functions | |
| uint32_t | ov_configure (Twihs *const p_twi, const e_ov7740_format format) |
| uint32_t | ov_configure_finish (Twihs *const p_twi) |
| uint32_t | ov_configure_manual (Twihs *const p_twi) |
| void | ov_dump_registers (Twihs *const p_twi, ov_reg *p_regs) |
| uint32_t | ov_init (Twihs *const p_twi) |
| void | ov_power (uint32_t on_off, Pio *const p_pio, const uint32_t ul_mask) |
| Turn OV7740 sensor on/off using power pin. More... | |
| uint32_t | ov_read_reg (Twihs *const p_twi, twihs_packet_t *p_packet) |
| void | ov_reset (Pio *const p_pio, const uint32_t ul_mask) |
| Reset OV7740 sensor using power pin. More... | |
| uint32_t | ov_restore_manual (volatile uint32_t *p_backup_addr, uint32_t ul_size) |
| Restore backup register manually. More... | |
| uint32_t | ov_store_manual (Twihs *const p_twi, volatile uint32_t *p_backup_addr, uint32_t ul_size) |
| uint32_t | ov_write_reg (Twihs *const p_twi, twihs_packet_t *const p_packet) |
| uint32_t | ov_write_regs (Twihs *const p_twi, const ov_reg *p_reg_list) |
Variables | |
| const ov_reg | OV7740_QQVGA_RGB888 [] |
| Addresses and values of the OV7740 registers for the OV7740_QVGA_RGB888 configuration: More... | |
| const ov_reg | OV7740_QQVGA_YUV422 [] |
| Addresses and values of the OV7740 registers for the OV7740_QQVGA_YUV422 configuration: More... | |
| const ov_reg | OV7740_QVGA_RGB888 [] |
| Addresses and values of the OV7740 registers for the OV7740_QVGA_RGB888 configuration: More... | |
| const ov_reg | OV7740_QVGA_YUV422_10FPS [] |
| Addresses and values of the OV7740 registers for the OV7740_QVGA_YUV422_10FPS configuration: More... | |
| const ov_reg | OV7740_QVGA_YUV422_15FPS [] |
| Addresses and values of the OV7740 registers for the OV7740_QVGA_YUV422_15FPS configuration: More... | |
| const ov_reg | OV7740_QVGA_YUV422_20FPS [] |
| Addresses and values of the OV7740 registers for the OV7740_QVGA_YUV422_20FPS configuration: More... | |
| const ov_reg | OV7740_QVGA_YUV422_30FPS [] |
| Addresses and values of the OV7740 registers for the OV7740_QVGA_YUV422_30FPS configuration: More... | |
| const ov_reg | OV7740_TEST_PATTERN [] |
| Addresses and values of the OV7740 registers for the OV7740_TEST_PATTERN configuration: More... | |
| const ov_reg | OV7740_VGA_YUV422_20FPS [] |
| Addresses and values of the OV7740 registers for the OV7740_VGA_YUV422_20FPS configuration: More... | |
| #define OV7740_AEC (0x10u) |
| #define OV7740_AHSIZE (0x18u) |
| #define OV7740_AHSTART (0x17u) |
| #define OV7740_AVSIZE (0x1au) |
| #define OV7740_AVSTART (0x19u) |
| #define OV7740_BLUE_AVG (0x05u) |
| #define OV7740_BLUE_GAIN (0x01u) |
| #define OV7740_BPT (0x25u) |
| #define OV7740_CLK (0x11u) |
(OV7740_CLK) sysclk=XVCLK1 x PLLDIV / [(CLK[5:0]+1) x2 xPreDiv]
| #define OV7740_CLK_DIVIDER | ( | value | ) | ((OV7740_CLK_DIVIDER_Msk & ((value) << OV7740_CLK_DIVIDER_Pos))) |
| #define OV7740_CLK_DIVIDER_Msk (0x3fu << OV7740_CLK_DIVIDER_Pos) |
(OV7740_CLK) Clock divider
| #define OV7740_CLK_DIVIDER_Pos (0) |
| #define OV7740_CLK_PLL | ( | value | ) | ((OV7740_CLK_PLL_Msk & ((value) << OV7740_CLK_PLL_Pos))) |
| #define OV7740_CLK_PLL_Msk (0x3u << OV7740_CLK_PLL_Pos) |
(OV7740_CLK) PLL setting - Changing this value is not recommanded
| #define OV7740_CLK_PLL_Pos (6) |
| #define OV7740_GAIN (0x00u) |
Register definitions.
(OV7740_GAIN) AGC Gain control LSBs (MSBs in REG15[1:0])
| #define OV7740_GREEN_AVG (0x06u) |
| #define OV7740_GREEN_GAIN (0x03u) |
| #define OV7740_HAEC (0x0fu) |
| #define OV7740_MIDH (0x1cu) |
Referenced by ov_manufacturer().
| #define OV7740_MIDH_DEFAULT (0x7fu << 0) |
Referenced by ov_manufacturer().
| #define OV7740_MIDL (0x1du) |
Referenced by ov_manufacturer().
| #define OV7740_MIDL_DEFAULT (0xa2u << 0) |
Referenced by ov_manufacturer().
| #define OV7740_PIDH (0x0au) |
Referenced by ov_id().
| #define OV7740_PIDH_DEFAULT (0x77u << 0) |
Referenced by ov_init().
| #define OV7740_PIDL (0x0bu) |
Referenced by ov_id().
| #define OV7740_PIDL_DEFAULT (0x40u << 0) |
| #define OV7740_PIXEL_SHIFT (0x1bu) |
| #define OV7740_RED_AVG (0x07u) |
| #define OV7740_RED_GAIN (0x02u) |
| #define OV7740_REG04 (0x04u) |
| #define OV7740_REG0C (0x0c) |
| #define OV7740_REG0C_BYTE_SWAP_DISABLE (0x0u << 3) |
(OV7740_REG0C) output Y9,Y8...Y3,Y2,Y1,Y0
| #define OV7740_REG0C_BYTE_SWAP_ENABLE (0x1u << 3) |
(OV7740_REG0C) output Y3,Y2...Y8,Y9,Y1,Y0
| #define OV7740_REG0C_BYTE_SWAP_Msk (0x1u << 3) |
(OV7740_REG0C) High 8-bit MSB and LSB swap
| #define OV7740_REG0C_FLIP_ENABLE (0x1u << 7) |
(OV7740_REG0C) Flip enable
| #define OV7740_REG0C_MAX_EXPOSURE | ( | value | ) | ((OV7740_REG0C_MAX_EXPOSURE_Msk & ((value) << OV7740_REG0C_MAX_EXPOSURE_Pos))) |
| #define OV7740_REG0C_MAX_EXPOSURE_Msk (0x3u << OV7740_REG0C_MAX_EXPOSURE_Pos) |
(OV7740_REG0C) Max exposure = frame length - limit x 2
| #define OV7740_REG0C_MAX_EXPOSURE_Pos (1) |
| #define OV7740_REG0C_MIRROR_ENABLE (0x1u << 6) |
(OV7740_REG0C) Mirror enable
| #define OV7740_REG0C_YUV_SWAP_DISABLE (0x0u << 4) |
(OV7740_REG0C) output YUYVYUYV
| #define OV7740_REG0C_YUV_SWAP_ENABLE (0x1u << 4) |
(OV7740_REG0C) output UYVYUYVY
| #define OV7740_REG0C_YUV_SWAP_Msk (0x1u << 4) |
(OV7740_REG0C) YUV output, Y <-> UV swap
| #define OV7740_REG0D (0x0du) |
| #define OV7740_REG0E (0x0eu) |
| #define OV7740_REG0E_BLC_BLUE (0x2u << OV7740_REG0E_BLC_Pos) |
(OV7740_REG0E) Select blue line as BLC line.
| #define OV7740_REG0E_BLC_BOTH (0x3u << OV7740_REG0E_BLC_Pos) |
(OV7740_REG0E) Select both blue line and red line as BLC line.
| #define OV7740_REG0E_BLC_BOTH0 (0x0u << OV7740_REG0E_BLC_Pos) |
(OV7740_REG0E) Select both blue line and red line as BLC line.
| #define OV7740_REG0E_BLC_LINE_ELECTRICAL (0x0u << 7) |
(OV7740_REG0E) Electrical BLC
| #define OV7740_REG0E_BLC_LINE_Msk (0x1u << 7) |
(OV7740_REG0E) BLC line selection
| #define OV7740_REG0E_BLC_LINE_OPTICAL (0x1u << 7) |
(OV7740_REG0E) Optical BLC
| #define OV7740_REG0E_BLC_Msk (0x3u << OV7740_REG0E_BLC_Pos) |
(OV7740_REG0E) BLC line selection
| #define OV7740_REG0E_BLC_Pos (5) |
| #define OV7740_REG0E_BLC_RED (0x1u << OV7740_REG0E_BLC_Pos) |
(OV7740_REG0E) Select red line as BLC line.
| #define OV7740_REG0E_OUTPUT_1X (0x0u << OV7740_REG0E_OUTPUT_Pos) |
(OV7740_REG0E) 1x
| #define OV7740_REG0E_OUTPUT_2X (0x1u << OV7740_REG0E_OUTPUT_Pos) |
(OV7740_REG0E) 2x
| #define OV7740_REG0E_OUTPUT_3X (0x2u << OV7740_REG0E_OUTPUT_Pos) |
(OV7740_REG0E) 3x
| #define OV7740_REG0E_OUTPUT_4X (0x3u << OV7740_REG0E_OUTPUT_Pos) |
(OV7740_REG0E) 4x
| #define OV7740_REG0E_OUTPUT_Msk (0x3u << OV7740_REG0E_OUTPUT_Pos) |
(OV7740_REG0E) Output driving capability
| #define OV7740_REG0E_OUTPUT_Pos (0) |
| #define OV7740_REG0E_SLEEP_MODE (0x1u << 3) |
(OV7740_REG0E) Sleep mode
| #define OV7740_REG12 (0x12u) |
| #define OV7740_REG12_CC656_MODE (0x1u << 5) |
| #define OV7740_REG12_RAW_RGB (0x1u << 0) |
| #define OV7740_REG12_RESET (0x1u << 7) |
| #define OV7740_REG12_SENSOR_RAW (0x1u << 4) |
| #define OV7740_REG12_VSKIP (0x1u << 6) |
| #define OV7740_REG13 (0x13u) |
| #define OV7740_REG13_AEC_FASTER (0x1u << 7) |
(OV7740_REG13) Faster AEC correction
| #define OV7740_REG13_AEC_Mask (0x1u << 7) |
(OV7740_REG13) AEC speed selection
| #define OV7740_REG13_AEC_NORMAL (0x0u << 7) |
(OV7740_REG13) Normal
| #define OV7740_REG13_AGC_AUTO (0x1u << 2) |
| #define OV7740_REG13_AGC_MANUAL (0x0u << 2) |
| #define OV7740_REG13_AGC_Msk (0x1u << 2) |
(OV7740_REG13) AGC auto/manual control selection
| #define OV7740_REG13_BANDING_DISABLE (0x0u << 5) |
| #define OV7740_REG13_BANDING_ENABLE (0x1u << 5) |
| #define OV7740_REG13_BANDING_Mask (0x1u << 5) |
(OV7740_REG13) Banding enable
| #define OV7740_REG13_BANDING_OPT_ENABLE (0x1u << 4) |
(OV7740_REG13) Minimum exposure is allowed to be less than 1/120 or 1/100 second when banding filter is enabled
| #define OV7740_REG13_BANDING_OPT_LIMITED (0x0u << 4) |
(OV7740_REG13) Minimum exposure is limited to 1/120 or 1/100 second when banding filter is enabled
| #define OV7740_REG13_BANDING_OPT_Msk (0x1u << 4) |
(OV7740_REG13) Banding option
| #define OV7740_REG13_EXPOSURE_AUTO (0x1u << 0) |
| #define OV7740_REG13_EXPOSURE_MANUAL (0x0u << 0) |
| #define OV7740_REG13_EXPOSURE_Msk (0x01u << 0) |
(OV7740_REG13) Exposure auto/manual control selection
| #define OV7740_REG13_FRAME_DROP_DISABLE (0x0u << 6) |
| #define OV7740_REG13_FRAME_DROP_ENABLE (0x1u << 6) |
| #define OV7740_REG13_FRAME_DROP_Mask (0x1u << 6) |
(OV7740_REG13) Enable frame drop function
| #define OV7740_REG13_LAEC_DISABLE (0x0u << 3) |
| #define OV7740_REG13_LAEC_ENABLE (0x1u << 3) |
| #define OV7740_REG13_LAEC_Msk (0x1u << 3) |
(OV7740_REG13) LAEC enable
| #define OV7740_REG13_WBAL_AUTO (0x1u << 1) |
| #define OV7740_REG13_WBAL_MANUAL (0x0u << 1) |
| #define OV7740_REG13_WBAL_Msk (0x1u << 1) |
(OV7740_REG13) Auto white balance control selection
| #define OV7740_REG14 (0x14u) |
| #define OV7740_REG15 (0x15u) |
| #define OV7740_REG15_CEIL_0 (0x0u << 4) |
(OV7740_REG15) Up to 0 frames
| #define OV7740_REG15_CEIL_1 (0x1u << 4) |
(OV7740_REG15) Up to 1 frames
| #define OV7740_REG15_CEIL_2 (0x2u << 4) |
(OV7740_REG15) Up to 2 frames
| #define OV7740_REG15_CEIL_3 (0x3u << 4) |
(OV7740_REG15) Up to 3 frames
| #define OV7740_REG15_CEIL_7 (0x7u << 4) |
(OV7740_REG15) Up to 7 frames
| #define OV7740_REG15_CEIL_Mask (0x3u << 4) |
(OV7740_REG15) Ceiling of inserting frames
| #define OV7740_REG15_ENABLE_NIGHT (0x1u << 7) |
(OV7740_REG15) Enable inserting frames in night mode
| #define OV7740_REG15_GAIN | ( | value | ) | ((OV7740_REG15_GAIN_Msk & ((value) << OV7740_REG15_GAIN_Pos))) |
| #define OV7740_REG15_GAIN_Msk (0x3u << OV7740_REG15_GAIN_Pos) |
(OV7740_REG15) AGC MSBs (digital gain) (LSBs in GAIN[7:0])
| #define OV7740_REG15_GAIN_Pos (0) |
| #define OV7740_REG15_NIGHT_16X_GAIN (0x3u << 2) |
(OV7740_REG15) 16x gain
| #define OV7740_REG15_NIGHT_2X_GAIN (0x0u << 2) |
(OV7740_REG15) 2x gain
| #define OV7740_REG15_NIGHT_4X_GAIN (0x1u << 2) |
(OV7740_REG15) 4x gain
| #define OV7740_REG15_NIGHT_8X_GAIN (0x2u << 2) |
(OV7740_REG15) 8x gain
| #define OV7740_REG15_NIGHT_Mask (0x3u << 2) |
(OV7740_REG15) Night mode triggering point
| #define OV7740_REG16 (0x16u) |
| #define OV7740_REG1E (0x1eu) |
| #define OV7740_REG1E (0x1eu) |
| #define OV7740_REG1F (0x1fu) |
| #define OV7740_REG20 (0x20u) |
| #define OV7740_REG21 (0x21u) |
| #define OV7740_REG27 (0x27u) |
| #define OV7740_REG27_BLACKSUN (0x1u << 7) |
(OV7740_REG27) Black sun cancellation enable
| #define OV7740_REG28 (0x28u) |
| #define OV7740_REG28_HREF_Msk (0x1u << 4) |
(OV7740_REG28) HREF polarity
| #define OV7740_REG28_HREF_NEGATIVE (0x1u << 4) |
(OV7740_REG28) Output negative HREF for data valid
| #define OV7740_REG28_HREF_OUTPUT_HREF (0x0u << 6) |
(OV7740_REG28) HREF
| #define OV7740_REG28_HREF_OUTPUT_HSYNC (0x1u << 6) |
(OV7740_REG28) HSYNC
| #define OV7740_REG28_HREF_OUTPUT_Msk (0x1u << 6) |
(OV7740_REG28) HREF pin output swap
| #define OV7740_REG28_HREF_POSITIVE (0x0u << 4) |
(OV7740_REG28) Output positive HREF
| #define OV7740_REG28_HSYNC_Msk (0x1u << 5) |
(OV7740_REG28) HSYNC polarity
| #define OV7740_REG28_HSYNC_NEGATIVE (0x1u << 5) |
(OV7740_REG28) Negative
| #define OV7740_REG28_HSYNC_POSITIVE (0x0u << 5) |
(OV7740_REG28) Positive
| #define OV7740_REG28_OUTPUT_REVERSE (0x1u << 7) |
(OV7740_REG28) Output data bit reverse option
| #define OV7740_REG28_VSYNC_Msk (0x1u << 1) |
(OV7740_REG28) VSYNC polarity
| #define OV7740_REG28_VSYNC_NEGATIVE (0x1u << 1) |
(OV7740_REG28) Negative
| #define OV7740_REG28_VSYNC_OUTPUT_Msk (0x1u << 3) |
(OV7740_REG28) No VSYNC output option
| #define OV7740_REG28_VSYNC_OUTPUT_NONE (0x1u << 3) |
(OV7740_REG28) No VSYNC output when frame drop
| #define OV7740_REG28_VSYNC_OUTPUT_STILL (0x0u << 3) |
(OV7740_REG28) Still output VSYNC when frame drop
| #define OV7740_REG28_VSYNC_POSITIVE (0x1u << 0) |
(OV7740_REG28) Positive
| #define OV7740_REG65 (0x65u) |
| #define OV7740_REG65_BIT_SWAP_Msk (0x1u << 3) |
(OV7740_REG65) Output data bit swap option
| #define OV7740_REG65_BIT_SWAP_NORMAL (0x0u << 3) |
(OV7740_REG65) Output DATA[9:0]
| #define OV7740_REG65_BIT_SWAP_REVERSE (0x1u << 3) |
(OV7740_REG65) Output DATA[0:9]
| #define OV7740_VPT (0x26u) |
| #define OV7740_WPT (0x24u) |
| #define OV7740_YUV422CTRL (0xd9u) |
Referenced by ov_dump_registers().
| #define OV7740_YUV422CTRL_CNV_OPT_AVERAGE (0x0u << 0) |
(OV7740_YUV422CTRL) Average mode
| #define OV7740_YUV422CTRL_CNV_OPT_DROP (0x1u << 0) |
(OV7740_YUV422CTRL) Drop mode
| #define OV7740_YUV422CTRL_CNV_OPT_Msk (0x1u << 0) |
(OV7740_YUV422CTRL) cnv_opt
| #define OV7740_YUV422CTRL_V_FIRST_Msk (0x1u << 1) |
(OV7740_YUV422CTRL) v_first
| #define OV7740_YUV422CTRL_V_FIRST_YUYV (0x0u << 1) |
(OV7740_YUV422CTRL) Output line will be YUYV...
| #define OV7740_YUV422CTRL_V_FIRST_YVYU (0x1u << 1) |
(OV7740_YUV422CTRL) Output line will be YVYU...
(it will affect definition of U/V in SDE. If it is set, all registers in SDE about U/V must be swapped
| #define OV_I2C_SENSOR_ADDRESS (0x42u >> 1) /* OV7740 -> 0x42 */ |
Slave address of OMNIVISION chip.
Referenced by ov_configure_finish(), ov_dump_registers(), ov_id(), ov_manufacturer(), ov_retrieve_manual(), ov_test_write(), and ov_write_regs().
| #define OV_REG_TERM (0xffu) |
Terminating list entry for register in configuration file.
Referenced by ov_write_regs().
| #define OV_VAL_TERM (0xffu) |
Terminating list entry for value in configuration file.
Referenced by ov_write_regs().
| typedef enum _e_ov7740_format e_ov7740_format |
Enumeration of different format which could be used by the 0V7740 sensor.
These enumeration allow to configure the OV7740 registers using the ov7740_table_registre.c Array.
| enum _e_ov7740_format |
Enumeration of different format which could be used by the 0V7740 sensor.
These enumeration allow to configure the OV7740 registers using the ov7740_table_registre.c Array.
| uint32_t ov_configure | ( | Twihs *const | p_twi, |
| const e_ov7740_format | format | ||
| ) |
| uint32_t ov_configure_finish | ( | Twihs *const | p_twi | ) |
| uint32_t ov_configure_manual | ( | Twihs *const | p_twi | ) |
| void ov_dump_registers | ( | Twihs *const | p_twi, |
| ov_reg * | p_regs | ||
| ) |
| uint32_t ov_init | ( | Twihs *const | p_twi | ) |
| uint32_t ov_read_reg | ( | Twihs *const | p_twi, |
| twihs_packet_t * | p_packet | ||
| ) |
| uint32_t ov_store_manual | ( | Twihs *const | p_twi, |
| volatile uint32_t * | p_backup_addr, | ||
| uint32_t | ul_size | ||
| ) |
| uint32_t ov_write_reg | ( | Twihs *const | p_twi, |
| twihs_packet_t *const | p_packet | ||
| ) |
| uint32_t ov_write_regs | ( | Twihs *const | p_twi, |
| const ov_reg * | p_reg_list | ||
| ) |
1.8.5