USB Device Driver for UDP.
Compliant with common UDD driver.
Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
#include "compiler.h"#include "preprocessor.h"#include "conf_board.h"#include "board.h"#include "ioport.h"#include "pio.h"#include "pio_handler.h"Macros | |
| #define | Is_udd_endpoint_status_enabled(status) (Tst_bits(status, UDP_CSR_EPEDS)) |
| #define | Is_udd_endpoint_status_error(status) (Tst_bits(status, UDP_CSR_ISOERROR)) |
| #define | Is_udd_endpoint_status_in(status) (Tst_bits(status, UDP_CSR_DIR)) |
| #define | Is_udd_endpoint_status_rx_all(status) ((status & (UDP_CSR_RX_DATA_BK0|UDP_CSR_RX_DATA_BK1)) == (UDP_CSR_RX_DATA_BK0|UDP_CSR_RX_DATA_BK1)) |
| #define | Is_udd_endpoint_status_rx_any_bank(status) (Tst_bits(status, UDP_CSR_RX_DATA_BK0|UDP_CSR_RX_DATA_BK0)) |
| #define | Is_udd_endpoint_status_rx_bank0(status) (Tst_bits(status, UDP_CSR_RX_DATA_BK0)) |
| #define | Is_udd_endpoint_status_rx_bank1(status) (Tst_bits(status, UDP_CSR_RX_DATA_BK1)) |
| #define | Is_udd_endpoint_status_rx_setup(status) (Tst_bits(status, UDP_CSR_RXSETUP)) |
| #define | Is_udd_endpoint_status_stall_pending(status) (Tst_bits(status, UDP_CSR_STALLSENT|UDP_CSR_FORCESTALL)) |
| #define | Is_udd_endpoint_status_stall_sent(status) (Tst_bits(status, UDP_CSR_STALLSENT)) |
| #define | Is_udd_endpoint_status_stalled(status) (Tst_bits(status, UDP_CSR_FORCESTALL)) |
| #define | Is_udd_endpoint_status_tx_complete(status) (Tst_bits(status, UDP_CSR_TXCOMP)) |
| #define | Is_udd_endpoint_status_tx_ready(status) (Tst_bits(status, UDP_CSR_TXPKTRDY)) |
| #define | udd_get_endpoint_status(ep) (UDP->UDP_CSR[ep]) |
| #define | udd_get_endpoint_status_byte_count(status) (Rd_bitfield(status, UDP_CSR_RXBYTECNT_Msk)) |
| #define | udd_get_endpoint_status_toggle(status) (Rd_bits(status, UDP_CSR_DTGLE)) |
| #define | udd_get_endpoint_status_type(status) (Rd_bits(status, UDP_CSR_EPTYPE_Msk)) |
UDP Device properties | |
These macros give IP properties (from datasheets) | |
| #define | udd_get_endpoint_max_nbr() (7) |
| Get maximal number of endpoints (3S 4S 4E, 0~7) More... | |
| #define | UDD_MAX_PEP_NB (udd_get_endpoint_max_nbr()+1) |
| #define | udd_get_endpoint_bank_max_nbr(ep) (((ep)==0||(ep)==3)?1:2) |
| Get maximal number of banks of endpoint (3S, 1~2) More... | |
| #define | udd_get_endpoint_size_max(ep) (((ep)==4||(ep)==5)?512:64) |
| Get maximal size of endpoint (3S, 512/64) More... | |
| #define | udd_is_endpoint_support_iso(ep) (((ep)==0||(ep)==3)?false:true) |
| Get isochronous support (3S, endpoints 0 and 3 not support) More... | |
| #define | Is_udd_endpoint_dma_supported(ep) (false) |
| Get DMA support of endpoints (3S, always false) More... | |
| #define | Is_udd_endpoint_high_bw_supported(ep) (false) |
| Get High Band Width support of endpoints (3S, always false) More... | |
UDP Device vbus pin management | |
UDP peripheral does not support vbus management and it's monitored by a PIO pin. This feature is optional, and it is enabled if USB_VBUS_PIN is defined in board.h and CONF_BOARD_USB_VBUS_DETECT defined in conf_board.h.
| |
| #define | UDD_VBUS_DETECT |
| #define | UDD_VBUS_IO (defined(USB_VBUS_PIN) && UDD_VBUS_DETECT) |
| #define | USB_VBUS_WKUP 0 |
| #define | udd_vbus_init(handler) |
| #define | Is_udd_vbus_high() ioport_get_pin_level(USB_VBUS_PIN) |
| #define | Is_udd_vbus_low() (!Is_udd_vbus_high()) |
| #define | udd_enable_vbus_interrupt() pio_enable_pin_interrupt(USB_VBUS_PIN) |
| #define | udd_disable_vbus_interrupt() pio_disable_pin_interrupt(USB_VBUS_PIN) |
| #define | udd_ack_vbus_interrupt(high) |
UDP peripheral enable/disable | |
| |
| #define | udd_enable_periph_ck() pmc_enable_periph_clk(ID_UDP) |
| #define | udd_disable_periph_ck() pmc_disable_periph_clk(ID_UDP) |
| #define | Is_udd_periph_ck_enabled() pmc_is_periph_clk_enabled(ID_UDP) |
UDP device attach control (by Pull-up) | |
These macros manage the UDP Device attach. | |
| #define | udd_detach_device() ( Clr_bits(UDP->UDP_TXVC, UDP_TXVC_PUON)) |
| detaches from USB bus More... | |
| #define | udd_attach_device() ( Set_bits(UDP->UDP_TXVC, UDP_TXVC_PUON)) |
| attaches to USB bus More... | |
| #define | Is_udd_detached() (!Tst_bits(UDP->UDP_TXVC, UDP_TXVC_PUON)) |
| test if the device is detached More... | |
USBB UDP transceiver management | |
These macros allows to enable/disable pad and USBB hardware | |
| #define | udd_enable_transceiver() ( Clr_bits(UDP->UDP_TXVC, UDP_TXVC_TXVDIS)) |
| #define | udd_disable_transceiver() ( Set_bits(UDP->UDP_TXVC, UDP_TXVC_TXVDIS)) |
| #define | Is_udd_transceiver_enabled() (!Tst_bits(UDP->UDP_TXVC, UDP_TXVC_TXVDIS)) |
UDP device bus events control | |
These macros manage the UDP Device bus events. | |
| #define | udd_disable_all_events() (UDP->IDR = 0xFFFF) |
| Manage misc events. More... | |
| #define | udd_disable_endpoint_events() (UDP->IDR = 0xFF) |
| #define | udd_enable_wakeups() (UDP->UDP_IER = (UDP_IER_RXRSM|UDP_IER_EXTRSM|UDP_IER_WAKEUP)) |
| #define | udd_disable_wakeups() (UDP->UDP_IDR = (UDP_IDR_RXRSM|UDP_IDR_EXTRSM|UDP_IDR_WAKEUP)) |
| #define | udd_ack_wakeups() (UDP->UDP_ICR = (UDP_ICR_RXRSM|UDP_ICR_EXTRSM|UDP_ICR_WAKEUP)) |
| #define | Is_udd_any_wakeup() (Tst_bits(UDP->UDP_ISR, (UDP_ICR_RXRSM|UDP_ICR_EXTRSM|UDP_ICR_WAKEUP))) |
| #define | Is_udd_expected_wakeup() ((UDP->UDP_ISR & (UDP_ICR_RXRSM|UDP_ICR_EXTRSM|UDP_ICR_WAKEUP)) & UDP->UDP_IMR) |
| #define | udd_enable_remote_wake_up() ( Set_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_RMWUPE)) |
| Manage remote wake-up event. More... | |
| #define | udd_disable_remote_wake_up() ( Clr_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_RMWUPE)) |
| #define | Is_udd_remote_wake_up_enabled() ( Tst_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_RMWUPE)) |
| #define | udd_initiate_remote_wake_up() |
| #define | Is_udd_pending_remote_wake_up() ( Tst_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_RSMINPR)) |
| #define | udd_enable_ext_resume_interrupt() (UDP->UDP_IER = UDP_IER_EXTRSM) |
| Manage end of resume event (ext/rx resume) The USB controller detects a valid "End of Resume" signal initiated by the host or detects a external "Resume" signal. More... | |
| #define | udd_disable_ext_resume_interrupt() (UDP->UDP_IDR = UDP_IER_EXTRSM) |
| #define | Is_udd_ext_resume_interrupt_enabled() (Tst_bits(UDP->UDP_IMR, UDP_IMR_EXTRSM)) |
| #define | udd_ack_ext_resume() (UDP->UDP_ICR = UDP_IER_EXTRSM) |
| #define | Is_udd_ext_resume() (Tst_bits(UDP->UDP_ISR, UDP_IER_EXTRSM)) |
| #define | udd_enable_resume_interrupt() (UDP->UDP_IER = UDP_IER_RXRSM) |
| #define | udd_disable_resume_interrupt() (UDP->UDP_IDR = UDP_IDR_RXRSM) |
| #define | Is_udd_resume_interrupt_enabled() (Tst_bits(UDP->UDP_IMR, UDP_IMR_RXRSM)) |
| #define | udd_ack_resume() (UDP->UDP_ICR = UDP_ICR_RXRSM) |
| #define | Is_udd_resume() (Tst_bits(UDP->UDP_ISR, UDP_ISR_RXRSM)) |
| #define | udd_enable_wake_up_interrupt() (UDP->UDP_IER = UDP_IER_WAKEUP) |
| Manage wake-up event (=usb line activity) The USB controller is reactivated by a filtered non-idle signal from the lines. More... | |
| #define | udd_disable_wake_up_interrupt() (UDP->UDP_IDR = UDP_IDR_WAKEUP) |
| #define | Is_udd_wake_up_interrupt_enabled() (Tst_bits(UDP->UDP_IMR, UDP_IMR_WAKEUP)) |
| #define | udd_ack_wake_up() (UDP->UDP_ICR = UDP_ICR_WAKEUP) |
| #define | Is_udd_wake_up() (Tst_bits(UDP->UDP_ISR, UDP_ISR_WAKEUP)) |
| #define | udd_ack_reset() (UDP->UDP_ICR = UDP_ISR_ENDBUSRES) |
| Manage reset event Set when a USB "End of Reset" has been detected. More... | |
| #define | Is_udd_reset() (Tst_bits(UDP->UDP_ISR, UDP_ISR_ENDBUSRES)) |
| #define | udd_enable_sof_interrupt() (UDP->UDP_IER = UDP_ISR_SOFINT) |
| Manage start of frame event. More... | |
| #define | udd_disable_sof_interrupt() (UDP->UDP_IDR = UDP_ISR_SOFINT) |
| #define | Is_udd_sof_interrupt_enabled() (Tst_bits(UDP->UDP_IMR, UDP_ISR_SOFINT)) |
| #define | udd_ack_sof() (UDP->UDP_ICR = UDP_ISR_SOFINT) |
| #define | Is_udd_sof() (Tst_bits(UDP->UDP_ISR, UDP_ISR_SOFINT)) |
| #define | udd_frame_number() (Rd_bitfield(UDP->UDP_FRM_NUM, UDP_FRM_NUM_FRM_NUM_Msk)) |
| #define | Is_udd_frame_number_crc_error() (Tst_bits(UDP->UDP_FRM_NUM, UDP_FRM_NUM_FRM_ERR)) |
| #define | udd_enable_suspend_interrupt() (UDP->UDP_IER = UDP_ISR_RXSUSP) |
| Manage suspend event. More... | |
| #define | udd_disable_suspend_interrupt() (UDP->UDP_IDR = UDP_ISR_RXSUSP) |
| #define | Is_udd_suspend_interrupt_enabled() (Tst_bits(UDP->UDP_IMR, UDP_ISR_RXSUSP)) |
| #define | udd_ack_suspend() (UDP->UDP_ICR = UDP_ISR_RXSUSP) |
| #define | udd_raise_suspend() (UDP->UDP_ISR = UDP_ISR_RXSUSP) |
| #define | Is_udd_suspend() (Tst_bits(UDP->UDP_ISR, UDP_ISR_RXSUSP)) |
UDP device address control | |
These macros manage the UDP Device address. | |
| #define | udd_enable_address() (Set_bits(UDP->UDP_FADDR, UDP_FADDR_FEN)) |
| enables USB device address More... | |
| #define | udd_disable_address() (Clr_bits(UDP->UDP_FADDR, UDP_FADDR_FEN)) |
| disables USB device address More... | |
| #define | Is_udd_address_enabled() (Tst_bits(UDP->UDP_FADDR, UDP_FADDR_FEN)) |
| #define | udd_configure_address(addr) (Wr_bitfield(UDP->UDP_FADDR, UDP_FADDR_FADD_Msk, addr)) |
| configures the USB device address More... | |
| #define | udd_get_configured_address() (Rd_bitfield(UDP->UDP_FADDR, UDP_FADDR_FADD_Msk)) |
| gets the currently configured USB device address More... | |
| #define | udd_enable_address_state() (Set_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_FADDEN)) |
| sets the device in address state More... | |
| #define | udd_disable_address_state() (Clr_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_FADDEN)) |
| bring back device to the default state More... | |
| #define | Is_udd_address_state_enabled() (Tst_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_FADDEN)) |
| Check if the device is in address state. More... | |
UDP device configured control | |
These macros manage the UDP Device configure state. | |
| #define | udd_enable_configured_state() (Set_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_CONFG)) |
| sets USB device in configured state More... | |
| #define | udd_disable_configured_state() (Clr_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_CONFG)) |
| #define | Is_udd_configured_state_enabled() (Tst_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_CONFG)) |
UDP Device endpoint drivers | |
These macros manage the common features of the endpoints. | |
| #define | UDP_REG_NO_EFFECT_1_ALL |
| Generic macro for CSR register access. More... | |
| #define | udp_set_csr(ep, bits) |
| #define | udp_clear_csr(ep, bits) |
| #define | udp_write_csr(ep, mask, bits) |
UDP Device endpoint configuration | |
| #define | udd_enable_endpoint(ep) udp_set_csr(ep, UDP_CSR_EPEDS) |
| enables the selected endpoint More... | |
| #define | udd_disable_endpoint(ep) udp_clear_csr(ep, UDP_CSR_EPEDS) |
| disables the selected endpoint More... | |
| #define | Is_udd_endpoint_enabled(ep) (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_EPEDS)) |
| tests if the selected endpoint is enabled More... | |
| #define | udd_reset_endpoint(ep) |
| resets the selected endpoint More... | |
| #define | Is_udd_resetting_endpoint(ep) (Tst_bits(UDP->UDP_RST_EP, UDP_RST_EP_EP0 << (ep))) |
| tests if the selected endpoint is being reset More... | |
| #define | udd_configure_endpoint_type(ep, type) udp_write_csr(ep, UDP_CSR_EPTYPE_Msk, type) |
| configures the selected endpoint type (shifted) More... | |
| #define | udd_get_endpoint_type(ep) (Rd_bits(UDP->UDP_CSR[ep], UDP_CSR_EPTYPE_Msk)) |
| gets the configured selected endpoint type (shifted) More... | |
| #define | Is_udd_endpoint_type_in(ep) (Tst_bits(UDP->UDP_CSR[ep], 0x4 << UDP_CSR_EPTYPE_Pos)) |
| #define | udd_configure_endpoint_direction(ep, dir) udp_write_csr(ep, UDP_CSR_DIR, (dir << 7) & UDP_CSR_DIR) |
| configures the selected endpoint direction (shifted) More... | |
| #define | udd_set_endpoint_direction_in(ep) udp_set_csr(ep, UDP_CSR_DIR) |
| configures the selected endpoint direction as IN (shifted) More... | |
| #define | udd_get_endpoint_direction(ep) (Rd_bits(UDP->UDP_CSR[ep], UDP_CSR_DIR)) |
| gets the configured selected endpoint direction (shifted) More... | |
| #define | Is_udd_endpoint_in(ep) (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_DIR)) |
| #define | udd_configure_endpoint(ep, type, dir) |
| configures selected endpoint in one step (type and dir are not shifted definitions) More... | |
| #define | Is_udd_endpoint_configured(ep) (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_EPEDS)) |
| tests if current endpoint is configured (=enabled) More... | |
| #define | udd_control_direction() (Rd_bits(UDP->UDP_CSR[0], UDP_CSR_DIR)) |
| returns the control direction More... | |
| #define | udd_data_toggle(ep) (Rd_bits(UDP->UDP_CSR[ep], UDP_CSR_DTGLE)) |
| returns data toggle More... | |
UDP Device control endpoint interrupts | |
These macros control the endpoints interrupts. | |
| #define | udd_enable_endpoint_interrupt(ep) (UDP->UDP_IER = UDP_IER_EP0INT << (ep)) |
| enables the selected endpoint interrupt More... | |
| #define | udd_disable_endpoint_interrupt(ep) (UDP->UDP_IDR = UDP_IDR_EP0INT << (ep)) |
| disables the selected endpoint interrupt More... | |
| #define | Is_udd_endpoint_interrupt_enabled(ep) (Tst_bits(UDP->UDP_IMR, UDP_IMR_EP0INT << (ep))) |
| tests if the selected endpoint interrupt is enabled More... | |
| #define | Is_udd_endpoint_interrupt(ep) (Tst_bits(UDP->UDP_ISR, UDP_ISR_EP0INT << (ep))) |
| tests if an interrupt is triggered by the selected endpoint More... | |
| #define | udd_get_interrupt_endpoint_number() (ctz(((UDP->UDP_ISR) & (UDP->UDP_IMR)) | (1 << UDD_MAX_PEP_NB))) |
| returns the lowest endpoint number generating an endpoint interrupt or UDD_MAX_PEP_NB if none More... | |
UDP Device control endpoint errors | |
These macros control the endpoint errors. | |
| #define | Is_udd_endpoint_stall_pending(ep) (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_FORCESTALL|UDP_CSR_STALLSENT)) |
| #define | udd_enable_stall_handshake(ep) udp_set_csr(ep, UDP_CSR_FORCESTALL) |
| enables the STALL handshake More... | |
| #define | udd_disable_stall_handshake(ep) udp_clear_csr(ep, UDP_CSR_FORCESTALL) |
| disables the STALL handshake More... | |
| #define | Is_udd_endpoint_stall_requested(ep) (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_FORCESTALL)) |
| tests if STALL handshake request is running More... | |
| #define | Is_udd_stall(ep) (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_STALLSENT)) |
| tests if STALL sent More... | |
| #define | udd_ack_stall(ep) udp_clear_csr(ep, UDP_CSR_STALLSENT) |
| acks STALL sent More... | |
| #define | Is_udd_crc_error(ep) (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_ISOERROR)) |
| tests if CRC ERROR ISO detected More... | |
| #define | udd_ack_crc_error(ep) udp_clear_csr(ep, UDP_CSR_ISOERROR) |
| acks CRC ERROR ISO detected More... | |
UDP Device control endpoint transfer | |
These macros control the endpoint transfer. | |
| #define | udd_byte_count(ep) (Rd_bitfield(UDP->UDP_CSR[ep], UDP_CSR_RXBYTECNT_Msk)) |
| returns the byte count More... | |
| #define | Is_udd_all_banks_received(ep) ((UDP->UDP_CSR[ep] & (UDP_CSR_RX_DATA_BK0|UDP_CSR_RX_DATA_BK1)) == (UDP_CSR_RX_DATA_BK0|UDP_CSR_RX_DATA_BK1)) |
| test if both banks received More... | |
| #define | Is_udd_any_bank_received(ep) (Tst_bits(UDP->UDP_CSR[ep], (UDP_CSR_RX_DATA_BK0|UDP_CSR_RX_DATA_BK1))) |
| test if Any of the Bank received More... | |
| #define | Is_udd_bank0_received(ep) (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_RX_DATA_BK0)) |
| test if Bank 0 received More... | |
| #define | udd_ack_bank0_received(ep) udp_clear_csr(ep, UDP_CSR_RX_DATA_BK0) |
| acks Bank 0 received More... | |
| #define | Is_udd_bank1_received(ep) (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_RX_DATA_BK1)) |
| test if Bank 1 received More... | |
| #define | udd_ack_bank1_received(ep) udp_clear_csr(ep, UDP_CSR_RX_DATA_BK1) |
| acks Bank 1 received More... | |
| #define | udd_nb_banks_received(ep) |
| returns the number of received banks More... | |
| #define | Is_udd_setup_received(ep) (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_RXSETUP)) |
| tests if SETUP received More... | |
| #define | udd_ack_setup_received(ep) udp_clear_csr(ep, UDP_CSR_RXSETUP) |
| acks SETUP received More... | |
| #define | Is_udd_in_pending(ep) (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_TXPKTRDY|UDP_CSR_TXCOMP)) |
| tests if IN pending (TX ready or IN sending) More... | |
| #define | Is_udd_in_sent(ep) (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_TXCOMP)) |
| tests if IN sending More... | |
| #define | udd_ack_in_sent(ep) udp_clear_csr(ep, UDP_CSR_TXCOMP) |
| acks IN sending More... | |
| #define | Is_udd_transmit_ready(ep) (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_TXPKTRDY)) |
| tests if transmit packet is ready More... | |
| #define | udd_set_transmit_ready(ep) udp_set_csr(ep, UDP_CSR_TXPKTRDY) |
| set transmit packet ready More... | |
| #define | udd_kill_data_in_fifo(ep, dual_bank) |
| cancel transmission data held in banks (if TXPKTRDY is set) More... | |
| #define | udd_endpoint_fifo_read(ep) (UDP->UDP_FDR[ep]) |
| read one byte from endpoint fifo More... | |
| #define | udd_endpoint_fifo_write(ep, byte) |
| write one byte to endpoint fifo More... | |
Functions | |
| static __always_inline void | io_pin_init (uint32_t pin, uint32_t flags, IRQn_Type port_irqn, uint8_t irq_level, void(*handler)(uint32_t, uint32_t), uint32_t wkup) |
| #define Is_udd_address_enabled | ( | ) | (Tst_bits(UDP->UDP_FADDR, UDP_FADDR_FEN)) |
| #define Is_udd_address_state_enabled | ( | ) | (Tst_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_FADDEN)) |
Check if the device is in address state.
Referenced by udd_getaddress().
| #define Is_udd_all_banks_received | ( | ep | ) | ((UDP->UDP_CSR[ep] & (UDP_CSR_RX_DATA_BK0|UDP_CSR_RX_DATA_BK1)) == (UDP_CSR_RX_DATA_BK0|UDP_CSR_RX_DATA_BK1)) |
test if both banks received
| #define Is_udd_any_bank_received | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], (UDP_CSR_RX_DATA_BK0|UDP_CSR_RX_DATA_BK1))) |
test if Any of the Bank received
| #define Is_udd_bank0_received | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_RX_DATA_BK0)) |
test if Bank 0 received
Referenced by udd_ctrl_in_sent(), and udd_ctrl_interrupt().
| #define Is_udd_bank1_received | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_RX_DATA_BK1)) |
test if Bank 1 received
| #define Is_udd_configured_state_enabled | ( | ) | (Tst_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_CONFG)) |
| #define Is_udd_crc_error | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_ISOERROR)) |
tests if CRC ERROR ISO detected
| #define Is_udd_endpoint_configured | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_EPEDS)) |
tests if current endpoint is configured (=enabled)
| #define Is_udd_endpoint_enabled | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_EPEDS)) |
tests if the selected endpoint is enabled
| #define Is_udd_endpoint_in | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_DIR)) |
| #define Is_udd_endpoint_interrupt | ( | ep | ) | (Tst_bits(UDP->UDP_ISR, UDP_ISR_EP0INT << (ep))) |
tests if an interrupt is triggered by the selected endpoint
Referenced by udd_ctrl_interrupt().
| #define Is_udd_endpoint_interrupt_enabled | ( | ep | ) | (Tst_bits(UDP->UDP_IMR, UDP_IMR_EP0INT << (ep))) |
tests if the selected endpoint interrupt is enabled
| #define Is_udd_endpoint_stall_pending | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_FORCESTALL|UDP_CSR_STALLSENT)) |
| #define Is_udd_endpoint_stall_requested | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_FORCESTALL)) |
tests if STALL handshake request is running
| #define Is_udd_endpoint_status_rx_all | ( | status | ) | ((status & (UDP_CSR_RX_DATA_BK0|UDP_CSR_RX_DATA_BK1)) == (UDP_CSR_RX_DATA_BK0|UDP_CSR_RX_DATA_BK1)) |
| #define Is_udd_endpoint_status_rx_any_bank | ( | status | ) | (Tst_bits(status, UDP_CSR_RX_DATA_BK0|UDP_CSR_RX_DATA_BK0)) |
| #define Is_udd_endpoint_status_stall_pending | ( | status | ) | (Tst_bits(status, UDP_CSR_STALLSENT|UDP_CSR_FORCESTALL)) |
| #define Is_udd_endpoint_type_in | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], 0x4 << UDP_CSR_EPTYPE_Pos)) |
| #define Is_udd_in_pending | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_TXPKTRDY|UDP_CSR_TXCOMP)) |
tests if IN pending (TX ready or IN sending)
| #define Is_udd_in_sent | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_TXCOMP)) |
tests if IN sending
Referenced by udd_ctrl_interrupt().
| #define Is_udd_resetting_endpoint | ( | ep | ) | (Tst_bits(UDP->UDP_RST_EP, UDP_RST_EP_EP0 << (ep))) |
tests if the selected endpoint is being reset
| #define Is_udd_setup_received | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_RXSETUP)) |
tests if SETUP received
Referenced by udd_ctrl_interrupt().
| #define Is_udd_stall | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_STALLSENT)) |
tests if STALL sent
Referenced by udd_ctrl_interrupt().
| #define Is_udd_transmit_ready | ( | ep | ) | (Tst_bits(UDP->UDP_CSR[ep], UDP_CSR_TXPKTRDY)) |
tests if transmit packet is ready
| #define udd_ack_bank0_received | ( | ep | ) | udp_clear_csr(ep, UDP_CSR_RX_DATA_BK0) |
acks Bank 0 received
Referenced by udd_ctrl_out_received().
| #define udd_ack_bank1_received | ( | ep | ) | udp_clear_csr(ep, UDP_CSR_RX_DATA_BK1) |
acks Bank 1 received
| #define udd_ack_crc_error | ( | ep | ) | udp_clear_csr(ep, UDP_CSR_ISOERROR) |
acks CRC ERROR ISO detected
| #define udd_ack_in_sent | ( | ep | ) | udp_clear_csr(ep, UDP_CSR_TXCOMP) |
acks IN sending
Referenced by udd_ctrl_in_sent().
| #define udd_ack_setup_received | ( | ep | ) | udp_clear_csr(ep, UDP_CSR_RXSETUP) |
acks SETUP received
Referenced by udd_ctrl_setup_received().
| #define udd_ack_stall | ( | ep | ) | udp_clear_csr(ep, UDP_CSR_STALLSENT) |
acks STALL sent
Referenced by udd_ctrl_interrupt().
| #define udd_byte_count | ( | ep | ) | (Rd_bitfield(UDP->UDP_CSR[ep], UDP_CSR_RXBYTECNT_Msk)) |
returns the byte count
Referenced by udd_ctrl_out_received(), and udd_ctrl_setup_received().
| #define udd_configure_address | ( | addr | ) | (Wr_bitfield(UDP->UDP_FADDR, UDP_FADDR_FADD_Msk, addr)) |
configures the USB device address
Referenced by udd_reset_ep_ctrl(), and udd_set_address().
| #define udd_configure_endpoint | ( | ep, | |
| type, | |||
| dir | |||
| ) |
configures selected endpoint in one step (type and dir are not shifted definitions)
Referenced by udd_reset_ep_ctrl().
| #define udd_configure_endpoint_direction | ( | ep, | |
| dir | |||
| ) | udp_write_csr(ep, UDP_CSR_DIR, (dir << 7) & UDP_CSR_DIR) |
configures the selected endpoint direction (shifted)
| #define udd_configure_endpoint_type | ( | ep, | |
| type | |||
| ) | udp_write_csr(ep, UDP_CSR_EPTYPE_Msk, type) |
configures the selected endpoint type (shifted)
| #define udd_control_direction | ( | ) | (Rd_bits(UDP->UDP_CSR[0], UDP_CSR_DIR)) |
returns the control direction
| #define udd_data_toggle | ( | ep | ) | (Rd_bits(UDP->UDP_CSR[ep], UDP_CSR_DTGLE)) |
returns data toggle
| #define udd_disable_address | ( | ) | (Clr_bits(UDP->UDP_FADDR, UDP_FADDR_FEN)) |
disables USB device address
Referenced by udd_set_address().
| #define udd_disable_address_state | ( | ) | (Clr_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_FADDEN)) |
bring back device to the default state
Referenced by ISR(), and udd_set_address().
| #define udd_disable_configured_state | ( | ) | (Clr_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_CONFG)) |
Referenced by ISR().
| #define udd_disable_endpoint | ( | ep | ) | udp_clear_csr(ep, UDP_CSR_EPEDS) |
disables the selected endpoint
| #define udd_disable_endpoint_interrupt | ( | ep | ) | (UDP->UDP_IDR = UDP_IDR_EP0INT << (ep)) |
disables the selected endpoint interrupt
| #define udd_disable_stall_handshake | ( | ep | ) | udp_clear_csr(ep, UDP_CSR_FORCESTALL) |
disables the STALL handshake
| #define udd_enable_address | ( | ) | (Set_bits(UDP->UDP_FADDR, UDP_FADDR_FEN)) |
enables USB device address
Referenced by udd_reset_ep_ctrl(), and udd_set_address().
| #define udd_enable_address_state | ( | ) | (Set_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_FADDEN)) |
sets the device in address state
Referenced by udd_set_address().
| #define udd_enable_configured_state | ( | ) | (Set_bits(UDP->UDP_GLB_STAT, UDP_GLB_STAT_CONFG)) |
sets USB device in configured state
| #define udd_enable_endpoint | ( | ep | ) | udp_set_csr(ep, UDP_CSR_EPEDS) |
enables the selected endpoint
Referenced by udd_reset_ep_ctrl().
| #define udd_enable_endpoint_interrupt | ( | ep | ) | (UDP->UDP_IER = UDP_IER_EP0INT << (ep)) |
enables the selected endpoint interrupt
Referenced by udd_reset_ep_ctrl().
| #define udd_enable_stall_handshake | ( | ep | ) | udp_set_csr(ep, UDP_CSR_FORCESTALL) |
enables the STALL handshake
Referenced by udd_ctrl_stall_data().
| #define udd_endpoint_fifo_read | ( | ep | ) | (UDP->UDP_FDR[ep]) |
read one byte from endpoint fifo
Referenced by udd_ctrl_out_received(), and udd_ctrl_setup_received().
| #define udd_endpoint_fifo_write | ( | ep, | |
| byte | |||
| ) |
write one byte to endpoint fifo
Referenced by udd_ctrl_in_sent().
| #define udd_get_configured_address | ( | ) | (Rd_bitfield(UDP->UDP_FADDR, UDP_FADDR_FADD_Msk)) |
gets the currently configured USB device address
Referenced by udd_getaddress().
| #define udd_get_endpoint_direction | ( | ep | ) | (Rd_bits(UDP->UDP_CSR[ep], UDP_CSR_DIR)) |
gets the configured selected endpoint direction (shifted)
| #define udd_get_endpoint_status | ( | ep | ) | (UDP->UDP_CSR[ep]) |
| #define udd_get_endpoint_status_byte_count | ( | status | ) | (Rd_bitfield(status, UDP_CSR_RXBYTECNT_Msk)) |
| #define udd_get_endpoint_type | ( | ep | ) | (Rd_bits(UDP->UDP_CSR[ep], UDP_CSR_EPTYPE_Msk)) |
gets the configured selected endpoint type (shifted)
| #define udd_get_interrupt_endpoint_number | ( | ) | (ctz(((UDP->UDP_ISR) & (UDP->UDP_IMR)) | (1 << UDD_MAX_PEP_NB))) |
returns the lowest endpoint number generating an endpoint interrupt or UDD_MAX_PEP_NB if none
| #define udd_kill_data_in_fifo | ( | ep, | |
| dual_bank | |||
| ) |
cancel transmission data held in banks (if TXPKTRDY is set)
| #define udd_nb_banks_received | ( | ep | ) |
returns the number of received banks
| #define udd_reset_endpoint | ( | ep | ) |
resets the selected endpoint
| #define udd_set_endpoint_direction_in | ( | ep | ) | udp_set_csr(ep, UDP_CSR_DIR) |
configures the selected endpoint direction as IN (shifted)
Referenced by udd_ctrl_setup_received().
| #define udd_set_transmit_ready | ( | ep | ) | udp_set_csr(ep, UDP_CSR_TXPKTRDY) |
set transmit packet ready
Referenced by udd_ctrl_in_sent(), and udd_ctrl_send_zlp_in().
| #define udp_clear_csr | ( | ep, | |
| bits | |||
| ) |
Clears specified bit(s) in the UDP_CSR.
| ep | Endpoint number. |
| bits | Bitmap to set to 0. |
| #define UDP_REG_NO_EFFECT_1_ALL |
Generic macro for CSR register access.
| #define udp_set_csr | ( | ep, | |
| bits | |||
| ) |
Sets specified bit(s) in the UDP_CSR.
| ep | Endpoint number. |
| bits | Bitmap to set to 1. |
| #define udp_write_csr | ( | ep, | |
| mask, | |||
| bits | |||
| ) |
Write specified bit(s) in the UDP_CSR.
| ep | Endpoint number. |
| bits | Bitmap to write. |
|
static |
1.8.5