phy_at86rf212b.h File Reference

Physical Layer Abstraction for AT86RF212B addon interface.

Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.

Data Structures
union	AT86RF212B_IFREG

Macros
#define	AACK_ACK_TIME   2
#define	AACK_DIS_ACK   4
#define	AACK_FLTR_RES_FT   5
#define	AACK_FVN_MODE   6
#define	AACK_I_AM_COORD   3
#define	AACK_PROM_MODE   1
#define	AACK_SET_PD   5
#define	AACK_UPLD_RES_FT   4
#define	AES_BLOCK_SIZE   16
#define	AES_CORE_CYCLE_TIME   24 /* us */
#define	AES_CTRL_DIR   3
#define	AES_CTRL_M_REG   0x94
#define	AES_CTRL_MODE   4
#define	AES_CTRL_REG   0x83
#define	AES_CTRL_REQUEST   7
#define	AES_KEY_REG   0x84
#define	AES_STATE_REG   0x84
#define	AES_STATUS_DONE   0
#define	AES_STATUS_ER   7
#define	AES_STATUS_REG   0x82
#define	ALT_SPECTRUM   4 /* Only in AT86RF212B */
#define	ANT_CTRL   0
#define	ANT_DIV_EN   3 /* Only in AT86RF212B */
#define	ANT_EXT_SW_EN   2
#define	ANT_SEL   7 /* Only in AT86RF212B */
#define	AVDD_OK   6
#define	AVREG_EXT   7
#define	BATMON_HR   4
#define	BATMON_OK   5
#define	BATMON_VTH   0
#define	BPSK_OQPSK   3
#define	CC_BAND   0
#define	CC_CTRL_0_REG   0x13
#define	CC_CTRL_1_REG   0x14
#define	CCA_CS_THRES   4 /* Only in AT86RF212B */
#define	CCA_DONE   7
#define	CCA_ED_THRES   0
#define	CCA_MODE   5
#define	CCA_REQUEST   7
#define	CCA_STATUS   6
#define	CHANNEL   0
#define	CLKM_CTRL   0
#define	CLKM_SHA_SEL   3
#define	CSMA_LBT_MODE   6
#define	CSMA_SEED_1   0
#define	DVDD_OK   2
#define	DVREG_EXT   3
#define	F_SHIFT_MODE   2 /* Only in AT86RF212B */
#define	FTN_START   7
#define	GC_PA   5
#define	GC_TX_OFFS   0
#define	JCM_EN   5
#define	MAX_BE   4
#define	MAX_CSMA_RETRES   1
#define	MAX_FRAME_RETRES   4
#define	MIN_BE   0
#define	OQPSK_DATA_RATE   0
#define	OQPSK_SCRAM_EN   5
#define	OQPSK_SUB1_RC_EN   4 /* Only in AT86RF212 */
#define	PA_BOOST   7
#define	PA_LT   6
#define	PAD_IO   6
#define	PAD_IO_CLKM   4
#define	PHY_MOD_BPSK20_CHAN_0   (0x00)
#define	PHY_MOD_BPSK40_CHAN_N   (0x04)
#define	PHY_RSSI_BASE_VAL_BPSK_20   (-100)
#define	PHY_RSSI_BASE_VAL_BPSK_40   (-99)
#define	PHY_RSSI_BASE_VAL_OQPSK_RC_250   (-97)
#define	PHY_RSSI_BASE_VAL_OQPSK_SIN_250   (-98)
#define	PHY_RSSI_BASE_VAL_OQPSK_SIN_RC_100   (-98)
#define	PLL_CF   0 /* Only in AT86RF212 */
#define	PLL_CF_START   7
#define	PLL_DCU_START   7
#define	PLL_LOCK_CP   7
#define	PROTOCOL_HEADER_SIZE   0
#define	PWR_BPSK_OFFSET   (0x03)
#define	RANDOM_NUMBER_UPDATE_INTERVAL   1 /* us */
#define	RF_CMD_FRAME_R   ((0 << 7) | (0 << 6) | (1 << 5))
#define	RF_CMD_FRAME_W   ((0 << 7) | (1 << 6) | (1 << 5))
#define	RF_CMD_REG_R   ((1 << 7) | (0 << 6))
#define	RF_CMD_REG_W   ((1 << 7) | (1 << 6))
#define	RF_CMD_SRAM_R   ((0 << 7) | (0 << 6) | (0 << 5))
#define	RF_CMD_SRAM_W   ((0 << 7) | (1 << 6) | (0 << 5))
#define	RF_CTRL_0_REG   0x16
#define	RF_CTRL_1_REG   0x19 /* Only in AT86RF212 */
#define	RF_MC   4 /* Only in AT86RF212 */
#define	RND_VALUE   5
#define	RSSI   0
#define	RX_CRC_VALID   7
#define	RX_OVERRIDE   4 /* Only in AT86RF212B */
#define	RX_PACKET_SIZE   (RX_BUFFER_SIZE+PROTOCOL_HEADER_SIZE+MY_ADDRESS_LENGTH+MY_ADDRESS_LENGTH+12)
#define	RX_PDT_DIS   7
#define	RX_PDT_LEVEL   0
#define	RX_SAFE_MODE   7
#define	SEC_LEVEL_CBC_MAC_128   5
#define	SEC_LEVEL_CBC_MAC_32   7
#define	SEC_LEVEL_CBC_MAC_64   6
#define	SEC_LEVEL_CCM_128   2
#define	SEC_LEVEL_CCM_32   4
#define	SEC_LEVEL_CCM_64   3
#define	SEC_LEVEL_CTR   1
#define	SLOTTED_OPERATION   0
#define	SUB_MODE   2
#define	TRAC_STATUS   5
#define	TRX_CMD   0
#define	TRX_OFF_AVDD_EN   6
#define	TRX_STATUS   0
#define	TX_PWR   0
#define	XTAL_MODE   4
#define	XTAL_TRIM   0

Functions
void	PHY_SetBand (uint8_t band)
void	PHY_SetModulation (uint8_t modulation)

#define AACK_ACK_TIME   2

#define AACK_DIS_ACK   4

#define AACK_FLTR_RES_FT   5

#define AACK_FVN_MODE   6

#define AACK_I_AM_COORD   3

#define AACK_PROM_MODE   1

#define AACK_SET_PD   5

#define AACK_UPLD_RES_FT   4

#define AES_BLOCK_SIZE   16

#define AES_CORE_CYCLE_TIME   24 /* us */

#define AES_CTRL_DIR   3

#define AES_CTRL_M_REG   0x94

#define AES_CTRL_MODE   4

#define AES_CTRL_REG   0x83

#define AES_CTRL_REQUEST   7

#define AES_KEY_REG   0x84

#define AES_STATE_REG   0x84

#define AES_STATUS_DONE   0

#define AES_STATUS_ER   7

#define AES_STATUS_REG   0x82

#define ALT_SPECTRUM   4 /* Only in AT86RF212B */

Referenced by PHY_Init().

#define ANT_CTRL   0

#define ANT_DIV_EN   3 /* Only in AT86RF212B */

#define ANT_EXT_SW_EN   2

#define ANT_SEL   7 /* Only in AT86RF212B */

#define AVDD_OK   6

#define AVREG_EXT   7

#define BATMON_HR   4

#define BATMON_OK   5

#define BATMON_VTH   0

#define BPSK_OQPSK   3

Referenced by PHY_Init(), and phyRssiBaseVal().

#define CC_BAND   0

#define CC_CTRL_0_REG   0x13

Referenced by phySetChannel().

#define CC_CTRL_1_REG   0x14

Referenced by phySetChannel().

#define CCA_CS_THRES   4 /* Only in AT86RF212B */

#define CCA_DONE   7

#define CCA_ED_THRES   0

#define CCA_MODE   5

#define CCA_REQUEST   7

#define CCA_STATUS   6

#define CHANNEL   0

#define CLKM_CTRL   0

#define CLKM_SHA_SEL   3

#define CSMA_LBT_MODE   6

#define CSMA_SEED_1   0

#define DVDD_OK   2

#define DVREG_EXT   3

#define F_SHIFT_MODE   2 /* Only in AT86RF212B */

#define FTN_START   7

#define GC_PA   5

#define GC_TX_OFFS   0

#define JCM_EN   5

#define MAX_BE   4

#define MAX_CSMA_RETRES   1

#define MAX_FRAME_RETRES   4

#define MIN_BE   0

#define OQPSK_DATA_RATE   0

#define OQPSK_SCRAM_EN   5

#define OQPSK_SUB1_RC_EN   4 /* Only in AT86RF212 */

#define PA_BOOST   7

#define PA_LT   6

#define PAD_IO   6

#define PAD_IO_CLKM   4

#define PHY_MOD_BPSK20_CHAN_0   (0x00)

Referenced by phySetChannel().

#define PHY_MOD_BPSK40_CHAN_N   (0x04)

Referenced by phySetChannel().

#define PHY_RSSI_BASE_VAL_BPSK_20   (-100)

Referenced by phyRssiBaseVal().

#define PHY_RSSI_BASE_VAL_BPSK_40   (-99)

Referenced by phyRssiBaseVal().

#define PHY_RSSI_BASE_VAL_OQPSK_RC_250   (-97)

Referenced by phyRssiBaseVal().

#define PHY_RSSI_BASE_VAL_OQPSK_SIN_250   (-98)

Referenced by phyRssiBaseVal().

#define PHY_RSSI_BASE_VAL_OQPSK_SIN_RC_100   (-98)

Referenced by phyRssiBaseVal().

#define PLL_CF   0 /* Only in AT86RF212 */

#define PLL_CF_START   7

#define PLL_DCU_START   7

#define PLL_LOCK_CP   7

#define PROTOCOL_HEADER_SIZE   0

#define PWR_BPSK_OFFSET   (0x03)

Referenced by PHY_Init().

#define RANDOM_NUMBER_UPDATE_INTERVAL   1 /* us */

Referenced by PHY_RandomReq().

#define RF_CMD_FRAME_R   ((0 << 7) | (0 << 6) | (1 << 5))

#define RF_CMD_FRAME_W   ((0 << 7) | (1 << 6) | (1 << 5))

#define RF_CMD_REG_R   ((1 << 7) | (0 << 6))

#define RF_CMD_REG_W   ((1 << 7) | (1 << 6))

#define RF_CMD_SRAM_R   ((0 << 7) | (0 << 6) | (0 << 5))

#define RF_CMD_SRAM_W   ((0 << 7) | (1 << 6) | (0 << 5))

#define RF_CTRL_0_REG   0x16

Referenced by PHY_Init().

#define RF_CTRL_1_REG   0x19 /* Only in AT86RF212 */

#define RF_MC   4 /* Only in AT86RF212 */

#define RND_VALUE   5

#define RSSI   0

#define RX_CRC_VALID   7

#define RX_OVERRIDE   4 /* Only in AT86RF212B */

#define RX_PACKET_SIZE   (RX_BUFFER_SIZE+PROTOCOL_HEADER_SIZE+MY_ADDRESS_LENGTH+MY_ADDRESS_LENGTH+12)

#define RX_PDT_DIS   7

#define RX_PDT_LEVEL   0

#define RX_SAFE_MODE   7

#define SEC_LEVEL_CBC_MAC_128   5

#define SEC_LEVEL_CBC_MAC_32   7

#define SEC_LEVEL_CBC_MAC_64   6

#define SEC_LEVEL_CCM_128   2

#define SEC_LEVEL_CCM_32   4

#define SEC_LEVEL_CCM_64   3

#define SEC_LEVEL_CTR   1

#define SLOTTED_OPERATION   0

#define SUB_MODE   2

Referenced by PHY_Init(), and phyRssiBaseVal().

#define TRAC_STATUS   5

#define TRX_CMD   0

#define TRX_OFF_AVDD_EN   6

#define TRX_STATUS   0

#define TX_PWR   0

#define XTAL_MODE   4

#define XTAL_TRIM   0

void PHY_SetBand

(

uint8_t

band

)

References phyBand, and phySetChannel().

void PHY_SetModulation

(

uint8_t

modulation

)

References phyModulation, and phySetChannel().