simulator_examples/dsp32_iir/iir_example.c File Reference

32-bit IIR filtering

Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries.

#include <avr32/io.h>
#include "compiler.h"
#include "board.h"
#include "dsp.h"
#include "dsp_debug.h"
#include "sysclk.h"

Macros
#define	DEN_PREDIV   3
#define	DEN_SIZE   5
#define	NUM_PREDIV   3
#define	NUM_SIZE   6
#define	SIZE   48

Functions
int	main (int argc, char *argv[])
	The main function. More...

Variables
A_ALIGNED dsp32_t	den [DEN_SIZE]
A_ALIGNED dsp32_t	num [NUM_SIZE]
A_ALIGNED dsp32_t	x [SIZE+NUM_SIZE-1]
	The input signal (sampling rate: 48KHz) A mix between a 4000 Hz and a 1000 Hz signal (mixed by addition) More...
A_ALIGNED dsp32_t	y [SIZE+DEN_SIZE]
	The output buffer. More...

#define DEN_PREDIV   3

Referenced by main().

#define DEN_SIZE   5

Referenced by main().

#define NUM_PREDIV   3

Referenced by main().

#define NUM_SIZE   6

Referenced by main().

#define SIZE   48

Referenced by main().

int main	(	int	argc,
		char *	argv[]
	)

The main function.

Note

the call to sysclk_init() will disable all non-vital peripheral clocks, except for the peripheral clocks explicitly enabled in conf_clock.h.

References den, DEN_PREDIV, DEN_SIZE, dsp32_debug_sprintf(), dsp32_filt_iir(), dsp_debug_initialization, FOSC0, i, num, NUM_PREDIV, NUM_SIZE, SIZE, sysclk_init(), x, and y.

A_ALIGNED dsp32_t den[DEN_SIZE]

Initial value:

= {
    DSP32_Q(-4.1534907 / (1 << DEN_PREDIV)),
    DSP32_Q(6.9612765  / (1 << DEN_PREDIV)),
    DSP32_Q(-5.877997  / (1 << DEN_PREDIV)),
    DSP32_Q(2.498365   / (1 << DEN_PREDIV)),

}

Referenced by dsp16_op_div(), dsp16_win_kaiser(), dsp32_op_div(), dsp32_win_kaiser(), dsp_debug_sprint_after_radix(), dsp_sprint_after_radix(), main(), and make_odither_array().

A_ALIGNED dsp32_t num[NUM_SIZE]

Initial value:

= {
    DSP32_Q(0.6537018  / (1 << NUM_PREDIV)),
    DSP32_Q(-3.2685088 / (1 << NUM_PREDIV)),
    DSP32_Q(6.5370176  / (1 << NUM_PREDIV)),
    DSP32_Q(-6.5370176 / (1 << NUM_PREDIV)),
    DSP32_Q(3.2685088  / (1 << NUM_PREDIV)),

}

Referenced by decompress_smooth_data(), dsp16_filt_lpfirdesign(), dsp16_op_asin(), dsp16_op_ln(), dsp16_op_ln_raw(), dsp16_op_log10(), dsp16_op_log2(), dsp16_op_pow(), dsp16_op_sqrt(), dsp16_win_kaiser(), dsp32_op_asin(), dsp32_op_ln(), dsp32_op_ln_raw(), dsp32_op_log10(), dsp32_op_log2(), dsp32_op_pow(), dsp32_op_sqrt(), dsp32_win_kaiser(), filter_get_description(), filter_set_active(), host_user_check_class(), main(), make_odither_array(), and netif_find().

A_ALIGNED dsp32_t x[SIZE+NUM_SIZE-1]

The input signal (sampling rate: 48KHz) A mix between a 4000 Hz and a 1000 Hz signal (mixed by addition)

A_ALIGNED dsp32_t y[SIZE+DEN_SIZE]

Initial value:

= {

}

The output buffer.