Clock system configuration.
Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
Macros | |
#define | CONFIG_PLL0_DIV 4 |
#define | CONFIG_PLL0_MUL 8 |
#define | CONFIG_PLL0_SOURCE PLL_SRC_RC32MHZ |
#define | CONFIG_SYSCLK_PSBCDIV CLK_PSBCDIV_1_2_gc |
#define | CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL |
#define CONFIG_PLL0_DIV 4 |
Referenced by pll_enable_config_defaults().
#define CONFIG_PLL0_MUL 8 |
Referenced by pll_enable_config_defaults().
#define CONFIG_PLL0_SOURCE PLL_SRC_RC32MHZ |
Referenced by pll_enable_config_defaults(), and sysclk_init().
#define CONFIG_SYSCLK_PSBCDIV CLK_PSBCDIV_1_2_gc |
Referenced by sysclk_get_per2_hz(), sysclk_get_per_hz(), and sysclk_init().
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL |
Referenced by sysclk_get_main_hz(), and sysclk_init().