MEMORY - EBI SDRAM Controller

EBI (External Bus Interface) SDRAM Controller allows to connect a SDRAM to the microcontroller.

Macros
#define	SDRAM   ((void *)AVR32_EBI_CS1_0_ADDRESS)
	Pointer to SDRAM. More...
#define	SDRAM_SIZE
	SDRAM size. More...

Functions
void	sdram_enter_self_refresh (void)
	Set the SDRAM in self refresh mode. The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. More...
void	sdram_exit_self_refresh (void)
	Exit from the SDRAM self refresh mode, inhibits self refresh mode. More...
void	sdramc_init (unsigned long hsb_hz)
	Initializes the AVR32 SDRAM Controller and the connected SDRAM(s). More...

#define SDRAM   ((void *)AVR32_EBI_CS1_0_ADDRESS)

Pointer to SDRAM.

Referenced by sdramc_init().

#define SDRAM_SIZE

Value:

(1 << (SDRAM_BANK_BITS + \
                               SDRAM_ROW_BITS  + \
                               SDRAM_COL_BITS  + \
                               (SDRAM_DBW >> 4)))

SDRAM size.

void sdram_enter_self_refresh

(

void

)

Set the SDRAM in self refresh mode. The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking.

Note

Once the SELF REFRESH command is registered, all the inputs to the SDRAM become "Don't Care" with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that.

An example of entering/exiting CPU sleep mode while keeping SDRAM content is : sdram_enter_self_refresh(); SLEEP(AVR32_PM_SMODE_STATIC); sdram_exit_self_refresh();

void sdram_exit_self_refresh

(

void

)

Exit from the SDRAM self refresh mode, inhibits self refresh mode.

void sdramc_init

(

unsigned long

hsb_hz

)

Initializes the AVR32 SDRAM Controller and the connected SDRAM(s).

Parameters

hsb_hz

HSB frequency in Hz (the HSB frequency is applied to the SDRAMC and to the SDRAM).

Note

HMATRIX and SDRAMC registers are always read with a dummy load operation after having been written to, in order to force write-back before executing the following accesses, which depend on the values set in these registers.

Each access to the SDRAM address space validates the mode of the SDRAMC and generates an operation corresponding to this mode.

References ATPASTE2, SDRAM, SDRAM_BANK_BITS, SDRAM_CAS, SDRAM_COL_BITS, SDRAM_DBW, SDRAM_INIT_AUTO_REFRESH_COUNT, SDRAM_ROW_BITS, SDRAM_STABLE_CLOCK_INIT_DELAY, SDRAM_TMRD, SDRAM_TR, SDRAM_TRAS, SDRAM_TRC, SDRAM_TRCD, SDRAM_TRFC, SDRAM_TRP, SDRAM_TWR, SDRAM_TXSR, sdramc_enable_muxed_pins(), sdramc_ns_delay, and sdramc_us_delay.