init.c File Reference

SAME70-XPLD board init.

Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.

#include "compiler.h"
#include "board.h"
#include "conf_board.h"
#include "ioport.h"
#include "pio.h"
#include "mpu.h"

Macros
#define	ioport_set_pin_input_mode(pin, mode, sense)
	Set input mode for one single IOPORT pin. More...
#define	ioport_set_pin_peripheral_mode(pin, mode)
	Set peripheral mode for one single IOPORT pin. More...
#define	ioport_set_port_peripheral_mode(port, masks, mode)
	Set peripheral mode for IOPORT pins. More...

Functions
static void	_setup_memory_region (void)
	Default memory map Address range Memory region Memory type Shareability Cache policy 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable - 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT 0xA0000000- 0xBFFFFFFF Device Device Shareable 0xC0000000- 0xDFFFFFFF Device Device Non Shareable 0xE0000000- 0xFFFFFFFF System - -. More...
void	board_init (void)
	This function initializes the board target resources. More...
static void	tcm_disable (void)
	TCM memory Disable. More...

#define ioport_set_pin_input_mode	(		pin,
			mode,
			sense
	)

Value:

do {\
		ioport_set_pin_dir(pin, IOPORT_DIR_INPUT);\
		ioport_set_pin_mode(pin, mode);\
		ioport_set_pin_sense_mode(pin, sense);\
    } while (0)

Set input mode for one single IOPORT pin.

It will configure port mode and disable pin mode (but enable peripheral).

Parameters

pin	IOPORT pin to configure
mode	Mode masks to configure for the specified pin (IOPORT Modes)
sense	Sense for interrupt detection (ioport_sense)

Referenced by board_init().

#define ioport_set_pin_peripheral_mode	(		pin,
			mode
	)

Value:

do {\
		ioport_set_pin_mode(pin, mode);\
		ioport_disable_pin(pin);\
    } while (0)

Set peripheral mode for one single IOPORT pin.

It will configure port mode and disable pin mode (but enable peripheral).

Parameters

pin	IOPORT pin to configure
mode	Mode masks to configure for the specified pin (IOPORT Modes)

Referenced by board_init().

#define ioport_set_port_peripheral_mode	(		port,
			masks,
			mode
	)

Value:

do {\
		ioport_set_port_mode(port, masks, mode);\
		ioport_disable_port(port, masks);\
    } while (0)

Set peripheral mode for IOPORT pins.

It will configure port mode and disable pin mode (but enable peripheral).

Parameters

port	IOPORT port to configure
masks	IOPORT pin masks to configure
mode	Mode masks to configure for the specified pin (IOPORT Modes)

static void _setup_memory_region ( void  )

static

Default memory map Address range Memory region Memory type Shareability Cache policy 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable - 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT 0xA0000000- 0xBFFFFFFF Device Device Shareable 0xC0000000- 0xDFFFFFFF Device Device Non Shareable 0xE0000000- 0xFFFFFFFF System - -.

Set up a memory region.

ITCM memory region — Normal START_Addr:- 0x00000000UL END_Addr:- 0x00400000UL

Internal flash memory region — Normal read-only (update to Strongly ordered in write accesses) START_Addr:- 0x00400000UL END_Addr:- 0x00600000UL

DTCM memory region — Normal START_Addr:- 0x20000000L END_Addr:- 0x20400000UL

SRAM Cacheable memory region — Normal START_Addr:- 0x20400000UL END_Addr:- 0x2043FFFFUL

Internal SRAM second partition memory region — Normal START_Addr:- 0x20440000UL END_Addr:- 0x2045FFFFUL

Peripheral memory region — DEVICE Shareable START_Addr:- 0x40000000UL END_Addr:- 0x5FFFFFFFUL

External EBI memory memory region — Strongly Ordered START_Addr:- 0x60000000UL END_Addr:- 0x6FFFFFFFUL

SDRAM cacheable memory region — Normal START_Addr:- 0x70000000UL END_Addr:- 0x7FFFFFFFUL

QSPI memory region — Strongly ordered START_Addr:- 0x80000000UL END_Addr:- 0x9FFFFFFFUL

USB RAM Memory region — Device START_Addr:- 0xA0100000UL END_Addr:- 0xA01FFFFFUL

References DTCM_END_ADDRESS, DTCM_START_ADDRESS, EXT_EBI_END_ADDRESS, EXT_EBI_START_ADDRESS, IFLASH_END_ADDRESS, IFLASH_START_ADDRESS, INNER_NORMAL_WB_NWA_TYPE, INNER_NORMAL_WB_RWA_TYPE, INNER_OUTER_NORMAL_NOCACHE_TYPE, ITCM_END_ADDRESS, ITCM_START_ADDRESS, MPU_AP_FULL_ACCESS, MPU_AP_PRIVILEGED_READ_WRITE, MPU_AP_READONLY, mpu_cal_mpu_region_size(), MPU_DEFAULT_DTCM_REGION, MPU_DEFAULT_IFLASH_REGION, MPU_DEFAULT_ITCM_REGION, MPU_DEFAULT_SDRAM_REGION, MPU_DEFAULT_SRAM_REGION_1, MPU_DEFAULT_SRAM_REGION_2, MPU_ENABLE, mpu_enable(), MPU_EXT_EBI_REGION, MPU_PERIPHERALS_REGION, MPU_PRIVDEFENA, MPU_QSPIMEM_REGION, MPU_REGION_ENABLE, MPU_REGION_EXECUTE_NEVER, MPU_REGION_VALID, mpu_set_region(), MPU_USBHSRAM_REGION, NON_SHAREABLE, PERIPHERALS_END_ADDRESS, PERIPHERALS_START_ADDRESS, QSPI_END_ADDRESS, QSPI_START_ADDRESS, SDRAM_END_ADDRESS, SDRAM_START_ADDRESS, SHAREABLE, SHAREABLE_DEVICE_TYPE, SRAM_FIRST_END_ADDRESS, SRAM_FIRST_START_ADDRESS, SRAM_SECOND_END_ADDRESS, SRAM_SECOND_START_ADDRESS, STRONGLY_ORDERED_SHAREABLE_TYPE, USBHSRAM_END_ADDRESS, and USBHSRAM_START_ADDRESS.

Referenced by board_init().

static void tcm_disable ( void  )

inlinestatic

TCM memory Disable.

The function enables TCM memories

Referenced by board_init().