Specified Interrupt Register (MDINTR, 21)

List Bit definitions: MII_MDINTR.

Macros
#define	MII_FDX_CHANGE   (1u << 4)
	Reserved: 7 to 5, Reserved. More...
#define	MII_FDX_MASK   (1u << 11)
	Reserved: 14 to 12, Reserved. More...
#define	MII_INTR_MASK   (1u << 8)
	Master Interrupt Mask. More...
#define	MII_INTR_PEND   (1u << 15)
	Interrupt Pending. More...
#define	MII_INTR_STATUS   (1u << 0)
	Reserved: 1, Reserved. More...
#define	MII_LINK_CHANGE   (1u << 2)
	Link Status Change Interrupt. More...
#define	MII_LINK_MASK   (1u << 9)
	Link Interrupt Mask. More...
#define	MII_SPD_CHANGE   (1u << 3)
	Speed Status Change Interrupt. More...
#define	MII_SPD_MASK   (1u << 10)
	Speed Interrupt Mask. More...

#define MII_FDX_CHANGE   (1u << 4)

Reserved: 7 to 5, Reserved.

Duplex Status Change Interrupt

#define MII_FDX_MASK   (1u << 11)

Reserved: 14 to 12, Reserved.

Full duplex Interrupt Mask

#define MII_INTR_MASK   (1u << 8)

Master Interrupt Mask.

#define MII_INTR_PEND   (1u << 15)

Interrupt Pending.

#define MII_INTR_STATUS   (1u << 0)

Reserved: 1, Reserved.

Interrupt Status

#define MII_LINK_CHANGE   (1u << 2)

Link Status Change Interrupt.

#define MII_LINK_MASK   (1u << 9)

Link Interrupt Mask.

#define MII_SPD_CHANGE   (1u << 3)

Speed Status Change Interrupt.

#define MII_SPD_MASK   (1u << 10)

Speed Interrupt Mask.