smc_et024006dhu.h File Reference

Macros
#define	_SMC_ET024005DHU_H_
#define	_SMC_ET024005DHU_H_
#define	EXT_SM_SIZE   0x200001
#define	EXT_SM_SIZE   0x200001
	SMC Peripheral Memory Size in Bytes. More...
#define	NCS_CONTROLLED_READ   false
#define	NCS_CONTROLLED_READ   false
	Whether read is controlled by NCS or by NRD. More...
#define	NCS_CONTROLLED_WRITE   false
	Whether write is controlled by NCS or by NWE. More...
#define	NCS_CONTROLLED_WRITE   false
#define	NCS_RD_HOLD   30
#define	NCS_RD_HOLD   30
#define	NCS_RD_PULSE   240
#define	NCS_RD_PULSE   240
#define	NCS_RD_SETUP   0
#define	NCS_RD_SETUP   0
#define	NCS_WR_HOLD   10
#define	NCS_WR_HOLD   10
#define	NCS_WR_PULSE   90
#define	NCS_WR_PULSE   90
#define	NCS_WR_SETUP   0
#define	NCS_WR_SETUP   0
#define	NRD_CYCLE   Max((NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD),(NRD_SETUP + NRD_PULSE + NRD_HOLD))
#define	NRD_CYCLE   Max((NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD),(NRD_SETUP + NRD_PULSE + NRD_HOLD))
#define	NRD_HOLD   30
#define	NRD_HOLD   30
#define	NRD_PULSE   210
#define	NRD_PULSE   210
#define	NRD_SETUP   30
#define	NRD_SETUP   30
#define	NWAIT_MODE   AVR32_SMC_EXNW_MODE_DISABLED
	Whether to use the NWAIT pin. More...
#define	NWAIT_MODE   AVR32_SMC_EXNW_MODE_DISABLED
#define	NWE_CYCLE   Max((NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD),(NWE_SETUP + NWE_PULSE + NWE_HOLD))
#define	NWE_CYCLE   Max((NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD),(NWE_SETUP + NWE_PULSE + NWE_HOLD))
#define	NWE_HOLD   20
#define	NWE_HOLD   20
#define	NWE_PULSE   60
#define	NWE_PULSE   60
#define	NWE_SETUP   20
#define	NWE_SETUP   20
#define	PAGE_MODE   false
#define	PAGE_MODE   false
#define	PAGE_SIZE   0
#define	PAGE_SIZE   0
#define	SMC_8_BIT_CHIPS   false
#define	SMC_8_BIT_CHIPS   false
	Whether 8-bit SM chips are connected on the SMC. More...
#define	SMC_DBW   16
	SMC Data Bus Width. More...
#define	SMC_DBW   16
#define	TDF_CYCLES   0
#define	TDF_CYCLES   0
#define	TDF_OPTIM   false
#define	TDF_OPTIM   false

#define _SMC_ET024005DHU_H_

#define _SMC_ET024005DHU_H_

#define EXT_SM_SIZE   0x200001

#define EXT_SM_SIZE   0x200001

SMC Peripheral Memory Size in Bytes.

#define NCS_CONTROLLED_READ   false

#define NCS_CONTROLLED_READ   false

Whether read is controlled by NCS or by NRD.

#define NCS_CONTROLLED_WRITE   false

Whether write is controlled by NCS or by NWE.

#define NCS_CONTROLLED_WRITE   false

#define NCS_RD_HOLD   30

#define NCS_RD_HOLD   30

#define NCS_RD_PULSE   240

#define NCS_RD_PULSE   240

#define NCS_RD_SETUP   0

#define NCS_RD_SETUP   0

#define NCS_WR_HOLD   10

#define NCS_WR_HOLD   10

#define NCS_WR_PULSE   90

#define NCS_WR_PULSE   90

#define NCS_WR_SETUP   0

#define NCS_WR_SETUP   0

#define NRD_CYCLE   Max((NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD),(NRD_SETUP + NRD_PULSE + NRD_HOLD))

#define NRD_CYCLE   Max((NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD),(NRD_SETUP + NRD_PULSE + NRD_HOLD))

#define NRD_HOLD   30

#define NRD_HOLD   30

#define NRD_PULSE   210

#define NRD_PULSE   210

#define NRD_SETUP   30

#define NRD_SETUP   30

#define NWAIT_MODE   AVR32_SMC_EXNW_MODE_DISABLED

Whether to use the NWAIT pin.

#define NWAIT_MODE   AVR32_SMC_EXNW_MODE_DISABLED

#define NWE_CYCLE   Max((NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD),(NWE_SETUP + NWE_PULSE + NWE_HOLD))

#define NWE_CYCLE   Max((NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD),(NWE_SETUP + NWE_PULSE + NWE_HOLD))

#define NWE_HOLD   20

#define NWE_HOLD   20

#define NWE_PULSE   60

#define NWE_PULSE   60

#define NWE_SETUP   20

#define NWE_SETUP   20

#define PAGE_MODE   false

#define PAGE_MODE   false

#define PAGE_SIZE   0

#define PAGE_SIZE   0

#define SMC_8_BIT_CHIPS   false

#define SMC_8_BIT_CHIPS   false

Whether 8-bit SM chips are connected on the SMC.

#define SMC_DBW   16

SMC Data Bus Width.

#define SMC_DBW   16

#define TDF_CYCLES   0

#define TDF_CYCLES   0

#define TDF_OPTIM   false

#define TDF_OPTIM   false