atmegarfa1/inc/tal_internal.h File Reference

#include "bmm.h"
#include "qmm.h"
#include "tal_slotted_csma.h"
#include "mac_build_config.h"

Macros
#define	_BV(x)   (1 << (x))
	Bit value – compute the bitmask for a bit position. More...
#define	PIN_ACK_OK_END()
#define	PIN_ACK_OK_START()
#define	PIN_ACK_WAITING_END()
#define	PIN_ACK_WAITING_START()
#define	PIN_BACKOFF_END()
#define	PIN_BACKOFF_START()
#define	PIN_BEACON_END()
#define	PIN_BEACON_LOSS_TIMER_END()
#define	PIN_BEACON_LOSS_TIMER_START()
#define	PIN_BEACON_START()
#define	PIN_CCA_END()
#define	PIN_CCA_START()
#define	PIN_CSMA_END()
#define	PIN_CSMA_START()
#define	PIN_NO_ACK_END()
#define	PIN_NO_ACK_START()
#define	PIN_TX_END()
#define	PIN_TX_START()
#define	PIN_WAITING_FOR_BEACON_END()
#define	PIN_WAITING_FOR_BEACON_START()
#define	TAL_PSDU_US_PER_OCTET(octets)   ((uint16_t)(octets) * 32)
	Conversion of number of PSDU octets to duration in microseconds. More...
#define	TRX_IRQ_AWAKE_ONLY   (TRX_IRQ_AWAKE)
#define	TRX_IRQ_CCA_ED_ONLY   (TRX_IRQ_CCA_ED_READY)
#define	TRX_IRQ_DEFAULT
#define	TRX_IRQ_NONE   (0)
Transceiver Access Macros
See Also Transceiver macros section of group_pal_gpio
#define	trx_reg_write(addr, data)   (*(volatile uint8_t *)(addr)) = (data)
	Writes data into a transceiver register. More...
#define	trx_reg_read(addr)   (*(volatile uint8_t *)(addr))
	Reads current value from a transceiver register. More...
#define	trx_frame_read(data, length)   memcpy((data), (void *)&TRXFBST, (length))
	Reads frame buffer of the transceiver. More...
#define	trx_frame_write(data, length)   memcpy((void *)&TRXFBST, (data), (length))
	Writes data into frame buffer of the transceiver. More...
#define	_trx_bit_read(addr, mask, pos)   (((*(volatile uint8_t *)(addr)) & (mask)) >> (pos))
#define	trx_bit_read(arg)   _trx_bit_read(arg)
	Subregister read. More...
#define	_trx_bit_write(addr, mask, pos, val)
#define	trx_bit_write(arg1, val)   _trx_bit_write(arg1, val)
	Subregister write. More...
Transceiver Access Macros
#define	TRX_RST_HIGH()   (TRXPR |= _BV(TRXRST))
	Set Reset Bit. More...
#define	TRX_RST_LOW()   (TRXPR &= ~_BV(TRXRST))
	Clear Reset Bit. More...
#define	TRX_SLP_TR_HIGH()   (TRXPR |= _BV(SLPTR))
	Set Sleep/TR Bit. More...
#define	TRX_SLP_TR_LOW()   (TRXPR &= ~_BV(SLPTR))
	Clear Sleep/TR Bit. More...
Transceiver IRQ Macros
#define	CLEAR_TRX_IRQ_TX_END()   (IRQ_STATUS = _BV(TX_END))
	Clears TRX TX_END interrupt. More...
#define	CLEAR_TRX_IRQ_TSTAMP()   (IRQ_STATUS = _BV(RX_START))
	Clear RX TIME STAMP interrupt. More...
#define	CLEAR_TRX_IRQ_RX_END()   (IRQ_STATUS = _BV(RX_END))
	Clear TRX RX_END interrupt. More...
#define	CLEAR_TRX_IRQ_CCA_ED()   (IRQ_STATUS = _BV(CCA_ED_DONE_EN))
	Clear TRX CCA_ED_DONE interrupt. More...
#define	CLEAR_TRX_IRQ_AMI()   (IRQ_STATUS = _BV(AMI))
	Clear AMI interrupt. More...
#define	CLEAR_TRX_IRQ_BATMON()   (BATMON = _BV(BAT_LOW))
	Clear TRX BAT LOW interrupt. More...
#define	CLEAR_TRX_IRQ_AWAKE()   (IRQ_STATUS = _BV(AWAKE))
	Clear TRX AWAKE interrupt. More...
#define	CLEAR_TRX_IRQ_PLL_LOCK()   (IRQ_STATUS = _BV(PLL_LOCK))
	Clear TRX PLL LOCK interrupt. More...
#define	CLEAR_TRX_IRQ_PLL_UNLOCK()   (IRQ_STATUS = _BV(PLL_UNLOCK))
	Clear TRX PLL UNLOCK interrupt. More...

Typedefs
typedef enum tal_state_tag	tal_state_t
	TAL states. More...
typedef enum trx_irq_reason_tag	trx_irq_reason_t
	Transceiver interrupt reasons. More...

Enumerations
enum	tal_state_tag {   TAL_IDLE = 0,   TAL_TX_AUTO = 1,   TAL_TX_DONE = 2,   TAL_SLOTTED_CSMA = 3,   TAL_IDLE = 0,   TAL_TX_AUTO = 1,   TAL_TX_DONE = 2,   TAL_SLOTTED_CSMA = 3 }
	TAL states. More...
enum	trx_irq_reason_tag {   TRX_NO_IRQ = (0x00),   TRX_IRQ_PLL_LOCK = (0x01),   TRX_IRQ_PLL_UNLOCK = (0x02),   TRX_IRQ_RX_START = (0x04),   TRX_IRQ_RX_END = (0x08),   TRX_IRQ_CCA_ED_READY = (0x10),   TRX_IRQ_AMI = (0x20),   TRX_IRQ_TX_END = (0x40),   TRX_IRQ_AWAKE = (0x80),   TRX_NO_IRQ = (0x00),   TRX_IRQ_PLL_LOCK = (0x01),   TRX_IRQ_PLL_UNLOCK = (0x02),   TRX_IRQ_RX_START = (0x04),   TRX_IRQ_RX_END = (0x08),   TRX_IRQ_CCA_ED_READY = (0x10),   TRX_IRQ_AMI = (0x20),   TRX_IRQ_TX_END = (0x40),   TRX_IRQ_AWAKE = (0x80) }
	Transceiver interrupt reasons. More...

Functions
tal_trx_status_t	set_trx_state (trx_cmd_t trx_cmd)
	Sets transceiver state. More...

Variables
uint8_t	last_frame_length
frame_info_t *	mac_frame_ptr
	Frame pointer for the frame structure provided by the MCL. More...
volatile bool	tal_awake_end_flag
csma_state_t	tal_csma_state
	CSMA state machine variable. More...
uint8_t *	tal_frame_to_tx
	Pointer to the 15.4 frame created by the TAL to be handed over to the transceiver. More...
queue_t	tal_incoming_frame_queue
	Queue that contains all frames that are uploaded from the trx, but have not be processed by the MCL yet. More...
buffer_t *	tal_rx_buffer
	Pointer to receive buffer that can be used to upload a frame from the trx. More...
bool	tal_rx_on_required
	Indicates if the transceiver needs to switch on its receiver by tal_task(), because it could not be switched on due to buffer shortage. More...
uint32_t	tal_rx_timestamp
	Timestamp The timestamping is only required for beaconing networks or if timestamping is explicitly enabled. More...
tal_state_t	tal_state
	Current state of the TAL state machine. More...
tal_trx_status_t	tal_trx_status
	Current state of the transceiver. More...

#define _BV

(

x

)

(1 << (x))

Bit value – compute the bitmask for a bit position.

#define _trx_bit_read	(		addr,
			mask,
			pos
	)		(((*(volatile uint8_t *)(addr)) & (mask)) >> (pos))

#define _trx_bit_write	(		addr,
			mask,
			pos,
			val
	)

Value:

do { \
        (*(volatile uint8_t *)(addr)) \
            = ((*(volatile uint8_t *)(addr)) & ~(mask)) | \
                (((val) << (pos)) & (mask)); \
} \
    while (0)

#define CLEAR_TRX_IRQ_AMI

(

)

(IRQ_STATUS = _BV(AMI))

Clear AMI interrupt.

#define CLEAR_TRX_IRQ_AWAKE

(

)

(IRQ_STATUS = _BV(AWAKE))

Clear TRX AWAKE interrupt.

#define CLEAR_TRX_IRQ_BATMON

(

)

(BATMON = _BV(BAT_LOW))

Clear TRX BAT LOW interrupt.

#define CLEAR_TRX_IRQ_CCA_ED

(

)

(IRQ_STATUS = _BV(CCA_ED_DONE_EN))

Clear TRX CCA_ED_DONE interrupt.

#define CLEAR_TRX_IRQ_PLL_LOCK

(

)

(IRQ_STATUS = _BV(PLL_LOCK))

Clear TRX PLL LOCK interrupt.

#define CLEAR_TRX_IRQ_PLL_UNLOCK

(

)

(IRQ_STATUS = _BV(PLL_UNLOCK))

Clear TRX PLL UNLOCK interrupt.

#define CLEAR_TRX_IRQ_RX_END

(

)

(IRQ_STATUS = _BV(RX_END))

Clear TRX RX_END interrupt.

#define CLEAR_TRX_IRQ_TSTAMP

(

)

(IRQ_STATUS = _BV(RX_START))

Clear RX TIME STAMP interrupt.

#define CLEAR_TRX_IRQ_TX_END

(

)

(IRQ_STATUS = _BV(TX_END))

Clears TRX TX_END interrupt.

#define PIN_ACK_OK_END

(

)

#define PIN_ACK_OK_START

(

)

#define PIN_ACK_WAITING_END

(

)

#define PIN_ACK_WAITING_START

(

)

#define PIN_BACKOFF_END

(

)

#define PIN_BACKOFF_START

(

)

#define PIN_BEACON_END

(

)

#define PIN_BEACON_LOSS_TIMER_END

(

)

#define PIN_BEACON_LOSS_TIMER_START

(

)

#define PIN_BEACON_START

(

)

#define PIN_CCA_END

(

)

#define PIN_CCA_START

(

)

#define PIN_CSMA_END

(

)

#define PIN_CSMA_START

(

)

#define PIN_NO_ACK_END

(

)

#define PIN_NO_ACK_START

(

)

#define PIN_TX_END

(

)

#define PIN_TX_START

(

)

#define PIN_WAITING_FOR_BEACON_END

(

)

#define PIN_WAITING_FOR_BEACON_START

(

)

#define TAL_PSDU_US_PER_OCTET

(

octets

)

((uint16_t)(octets) * 32)

Conversion of number of PSDU octets to duration in microseconds.

#define trx_bit_read

(

arg

)

_trx_bit_read(arg)

Subregister read.

Parameters

arg	Subregister

Returns

Value of the read subregister

#define trx_bit_write	(		arg1,
			val
	)		_trx_bit_write(arg1, val)

Subregister write.

Parameters

[in]	arg1	Subregister
[out]	val	Data, which is muxed into the register

#define trx_frame_read	(		data,
			length
	)		memcpy((data), (void *)&TRXFBST, (length))

Reads frame buffer of the transceiver.

This macro reads the frame buffer of the transceiver.

Parameters

[out]	data	Pointer to the location to store frame
[in]	length	Number of bytes to be read from the frame buffer.

#define trx_frame_write	(		data,
			length
	)		memcpy((void *)&TRXFBST, (data), (length))

Writes data into frame buffer of the transceiver.

This macro writes data into the frame buffer of the transceiver

Parameters

[in]	data	Pointer to data to be written into frame buffer
[in]	length	Number of bytes to be written into frame buffer

#define TRX_IRQ_AWAKE_ONLY   (TRX_IRQ_AWAKE)

#define TRX_IRQ_CCA_ED_ONLY   (TRX_IRQ_CCA_ED_READY)

#define TRX_IRQ_DEFAULT

Value:

(TRX_IRQ_RX_START | TRX_IRQ_RX_END | \
	TRX_IRQ_TX_END)

#define TRX_IRQ_NONE   (0)

#define trx_reg_read

(

addr

)

(*(volatile uint8_t *)(addr))

Reads current value from a transceiver register.

This macro reads the current value from a transceiver register.

Parameters

addr	Specifies the address of the trx register from which the data shall be read

Returns

value of the register read

#define trx_reg_write	(		addr,
			data
	)		(*(volatile uint8_t *)(addr)) = (data)

Writes data into a transceiver register.

This macro writes a value into transceiver register.

Parameters

addr	Address of the trx register
data	Data to be written to trx register

#define TRX_RST_HIGH

(

)

(TRXPR |= _BV(TRXRST))

Set Reset Bit.

#define TRX_RST_LOW

(

)

(TRXPR &= ~_BV(TRXRST))

Clear Reset Bit.

#define TRX_SLP_TR_HIGH

(

)

(TRXPR |= _BV(SLPTR))

Set Sleep/TR Bit.

#define TRX_SLP_TR_LOW

(

)

(TRXPR &= ~_BV(SLPTR))

Clear Sleep/TR Bit.

typedef enum tal_state_tag tal_state_t

TAL states.

typedef enum trx_irq_reason_tag trx_irq_reason_t

Transceiver interrupt reasons.

enum tal_state_tag

TAL states.

Enumerator
TAL_IDLE
TAL_TX_AUTO
TAL_TX_DONE
TAL_SLOTTED_CSMA
TAL_IDLE
TAL_TX_AUTO
TAL_TX_DONE
TAL_SLOTTED_CSMA

enum trx_irq_reason_tag

Transceiver interrupt reasons.

Enumerator
TRX_NO_IRQ	No interrupt is indicated by IRQ_STATUS register.
TRX_IRQ_PLL_LOCK	PLL goes to lock-state.
TRX_IRQ_PLL_UNLOCK	Signals an unlocked PLL.
TRX_IRQ_RX_START	Signals begin of a receiving frame.
TRX_IRQ_RX_END	Signals completion of a frame reception.
TRX_IRQ_CCA_ED_READY	Signals the end of a CCA or ED measurement.
TRX_IRQ_AMI	Signals an address match.
TRX_IRQ_TX_END	Signals the completion of a frame transmission.
TRX_IRQ_AWAKE	Indicates that the radio transceiver reached TRX_OFF state after P_ON, RESET, or SLEEP states.
TRX_NO_IRQ	No interrupt is indicated by IRQ_STATUS register.
TRX_IRQ_PLL_LOCK	PLL goes to lock-state.
TRX_IRQ_PLL_UNLOCK	Signals an unlocked PLL.
TRX_IRQ_RX_START	Signals begin of a receiving frame.
TRX_IRQ_RX_END	Signals completion of a frame reception.
TRX_IRQ_CCA_ED_READY	Signals the end of a CCA or ED measurement.
TRX_IRQ_AMI	Signals an address match.
TRX_IRQ_TX_END	Signals the completion of a frame transmission.
TRX_IRQ_AWAKE	Indicates that the radio transceiver reached TRX_OFF state after P_ON, RESET, or SLEEP states.

uint8_t last_frame_length

Referenced by process_incoming_frame(), send_frame(), and tal_tx_frame().

frame_info_t* mac_frame_ptr

Frame pointer for the frame structure provided by the MCL.

Referenced by calculate_transaction_duration(), handle_tx_end_irq(), tal_tx_frame(), tx_done(), and tx_done_handling().

volatile bool tal_awake_end_flag

Referenced by set_trx_state(), and trx_awake_handler_cb().

csma_state_t tal_csma_state

CSMA state machine variable.

Referenced by beacon_loss_timer_cb(), cca_timer_handler_cb(), csma_backoff_calculation(), handle_tx_end_irq(), internal_tal_reset(), process_incoming_frame(), send_frame_at_next_backoff_boundary(), slotted_csma_state_handling(), and tx_done().

uint8_t* tal_frame_to_tx

Pointer to the 15.4 frame created by the TAL to be handed over to the transceiver.

Referenced by calculate_transaction_duration(), send_frame(), tal_tx_frame(), and tx_done_handling().

queue_t tal_incoming_frame_queue

Queue that contains all frames that are uploaded from the trx, but have not be processed by the MCL yet.

Referenced by handle_received_frame_irq(), mac_ready_to_sleep(), tal_init(), tal_reset(), and tal_task().

buffer_t* tal_rx_buffer

Pointer to receive buffer that can be used to upload a frame from the trx.

Referenced by handle_received_frame_irq(), handle_tx_end_irq(), tal_init(), tal_pib_set(), and tal_rx_enable().

uint32_t tal_rx_timestamp

Timestamp The timestamping is only required for beaconing networks or if timestamping is explicitly enabled.

Referenced by handle_received_frame_irq(), and trx_irq_timestamp_handler_cb().