Microchip® Advanced Software Framework

Macros | Typedefs | Enumerations
wireless/avr2025_mac/source/tal/atmegarfa1/inc/atmega128rfa1.h File Reference
#include "tal_types.h"

Macros

#define ACK_DISABLE   (1)
 Constant ACK_DISABLE for sub-register SR_AACK_DIS_ACK in register CSMA_SEED_1. More...
 
#define ACK_ENABLE   (0)
 Constant ACK_ENABLE for sub-register SR_AACK_DIS_ACK in register CSMA_SEED_1. More...
 
#define ACK_TIME_12_SYMBOLS   (0)
 Constant ACK_TIME_12_SYMBOLS for sub-register SR_AACK_ACK_TIME in register XAH_CTRL_1. More...
 
#define ACK_TIME_2_SYMBOLS   (1)
 Constant ACK_TIME_2_SYMBOLS for sub-register SR_AACK_ACK_TIME in register XAH_CTRL_1. More...
 
#define AES_COMPLETED   (1)
 Constant AES_COMPLETED for sub-register SR_AES_DONE in register AES_STATUS. More...
 
#define AES_DIR_DECRYPT   (1)
 Constant AES_DIR_DECRYPT for sub-register SR_AES_DIR in register AES_CTRL. More...
 
#define AES_DIR_ENCRYPT   (0)
 Constant AES_DIR_ENCRYPT for sub-register SR_AES_DIR in register AES_CTRL. More...
 
#define AES_NOT_COMPLETED   (0)
 Constant AES_NOT_COMPLETED for sub-register SR_AES_DONE in register AES_STATUS. More...
 
#define AES_START   (1)
 Constant AES_START for sub-register SR_AES_REQUEST in register AES_CTRL. More...
 
#define ANT_DIV_DISABLE   (0)
 Constant ANT_DIV_DISABLE for sub-register SR_ANT_DIV_EN in register ANT_DIV. More...
 
#define ANT_DIV_ENABLE   (1)
 Constant ANT_DIV_ENABLE for sub-register SR_ANT_DIV_EN in register ANT_DIV. More...
 
#define ANT_EXT_SW_DISABLE   (0)
 Constant ANT_EXT_SW_DISABLE for sub-register SR_ANT_EXT_SW_EN in register ANT_DIV. More...
 
#define ANT_EXT_SW_ENABLE   (1)
 Constant ANT_EXT_SW_ENABLE for sub-register SR_ANT_EXT_SW_EN in register ANT_DIV. More...
 
#define ATMEGA128RFA1_PART_NUM   (0x83)
 Constant ATMEGA128RFA1_PART_NUM for sub-register SR_PART_NUM in register PART_NUM. More...
 
#define BATMON_ABOVE_THRES   (1)
 Constant BATMON_ABOVE_THRES for sub-register SR_BATMON_OK in register BATMON. More...
 
#define BATMON_BELOW_THRES   (0)
 Constant BATMON_BELOW_THRES for sub-register SR_BATMON_OK in register BATMON. More...
 
#define BATMON_HIGH_RANGE   (1)
 Constant BATMON_HIGH_RANGE for sub-register SR_BATMON_HR in register BATMON. More...
 
#define BATMON_LOW_RANGE   (0)
 Constant BATMON_LOW_RANGE for sub-register SR_BATMON_HR in register BATMON. More...
 
#define CCA_CH_BUSY   (0)
 Constant CCA_CH_BUSY for sub-register SR_CCA_STATUS in register TRX_STATUS. More...
 
#define CCA_CH_IDLE   (1)
 Constant CCA_CH_IDLE for sub-register SR_CCA_STATUS in register TRX_STATUS. More...
 
#define CCA_COMPLETED   (1)
 Constant CCA_COMPLETED for sub-register SR_CCA_DONE in register TRX_STATUS. More...
 
#define CCA_DETECTION_TIME_SYM   (8)
 CSMA timimg parameters. More...
 
#define CCA_DURATION_SYM
 
#define CCA_MODE_0   (0)
 Constant CCA_MODE_0 for sub-register SR_CCA_MODE in register PHY_CC_CCA. More...
 
#define CCA_MODE_1   (1)
 Constant CCA_MODE_1 for sub-register SR_CCA_MODE in register PHY_CC_CCA. More...
 
#define CCA_MODE_2   (2)
 Constant CCA_MODE_2 for sub-register SR_CCA_MODE in register PHY_CC_CCA. More...
 
#define CCA_MODE_3   (3)
 Constant CCA_MODE_3 for sub-register SR_CCA_MODE in register PHY_CC_CCA. More...
 
#define CCA_NOT_COMPLETED   (0)
 Constant CCA_NOT_COMPLETED for sub-register SR_CCA_DONE in register TRX_STATUS. More...
 
#define CCA_PRE_START_DURATION_US   (20)
 
#define CCA_PREPARATION_DURATION_US   (50)
 
#define CCA_PROCESS_TIME_SYM   (1)
 
#define CCA_START   (1)
 Constant CCA_START for sub-register SR_CCA_REQUEST in register PHY_CC_CCA. More...
 
#define CRC16_NOT_VALID   (0)
 Constant CRC16_NOT_VALID for sub-register SR_RX_CRC_VALID in register PHY_RSSI. More...
 
#define CRC16_VALID   (1)
 Constant CRC16_VALID for sub-register SR_RX_CRC_VALID in register PHY_RSSI. More...
 
#define FRAME_VERSION_0   (0)
 Constant FRAME_VERSION_0 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1. More...
 
#define FRAME_VERSION_01   (1)
 Constant FRAME_VERSION_01 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1. More...
 
#define FRAME_VERSION_012   (2)
 Constant FRAME_VERSION_012 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1. More...
 
#define FRAME_VERSION_IGNORED   (3)
 Constant FRAME_VERSION_IGNORED for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1. More...
 
#define I_AM_COORD_DISABLE   (0)
 Constant I_AM_COORD_DISABLE for sub-register SR_AACK_I_AM_COORD in register CSMA_SEED_1. More...
 
#define I_AM_COORD_ENABLE   (1)
 Constant I_AM_COORD_ENABLE for sub-register SR_AACK_I_AM_COORD in register CSMA_SEED_1. More...
 
#define IRQ_PROCESSING_DLY_US   (32)
 
#define P_ON_TO_CLKM_AVAILABLE_MAX_US   (1000)
 
#define P_ON_TO_CLKM_AVAILABLE_TYP_US   (380)
 
#define PA_LT_2_US   (0)
 Constant PA_LT_2_US for sub-register SR_PA_LT in register PHY_TX_PWR. More...
 
#define PA_LT_4_US   (1)
 Constant PA_LT_4_US for sub-register SR_PA_LT in register PHY_TX_PWR. More...
 
#define PA_LT_6_US   (2)
 Constant PA_LT_6_US for sub-register SR_PA_LT in register PHY_TX_PWR. More...
 
#define PA_LT_8_US   (3)
 Constant PA_LT_8_US for sub-register SR_PA_LT in register PHY_TX_PWR. More...
 
#define PD_ACK_BIT_SET_DISABLE   (0)
 Constant PD_ACK_BIT_SET_DISABLE for sub-register SR_AACK_SET_PD in register CSMA_SEED_1. More...
 
#define PD_ACK_BIT_SET_ENABLE   (1)
 Constant PD_ACK_BIT_SET_ENABLE for sub-register SR_AACK_SET_PD in register CSMA_SEED_1. More...
 
#define PRE_TX_DURATION_US   (32)
 
#define PROM_MODE_DISABLE   (0)
 Constant PROM_MODE_DISABLE for sub-register SR_AACK_PROM_MODE in register XAH_CTRL_1. More...
 
#define PROM_MODE_ENABLE   (1)
 Constant PROM_MODE_ENABLE for sub-register SR_AACK_PROM_MODE in register XAH_CTRL_1. More...
 
#define RATE_1_MBPS   (2)
 Constant RATE_1_MBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2. More...
 
#define RATE_250_KBPS   (0)
 Constant RATE_250_KBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2. More...
 
#define RATE_2_MBPS   (3)
 Constant RATE_2_MBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2. More...
 
#define RATE_500_KBPS   (1)
 Constant RATE_500_KBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2. More...
 
#define RESET_TO_TRX_OFF_MAX_US   (1000)
 
#define RESET_TO_TRX_OFF_TYP_US   (37)
 
#define REV_AB   (2)
 Constant REV_AB for sub-register SR_VERSION_NUM in register VERSION_NUM. More...
 
#define REV_C   (3)
 Constant REV_C for sub-register SR_VERSION_NUM in register VERSION_NUM. More...
 
#define REV_D   (4)
 Constant REV_D for sub-register SR_VERSION_NUM in register VERSION_NUM. More...
 
#define REV_F   (12)
 Constant REV_F for sub-register SR_VERSION_NUM in register VERSION_NUM. More...
 
#define RG_AES_CTRL   (0x13C)
 Register addresses. More...
 
#define RG_AES_KEY   (0x13F)
 Offset for register AES_KEY. More...
 
#define RG_AES_STATE   (0x13E)
 Offset for register AES_STATE. More...
 
#define RG_AES_STATUS   (0x13D)
 Offset for register AES_STATUS. More...
 
#define RG_ANT_DIV   (0x14D)
 Offset for register ANT_DIV. More...
 
#define RG_BATMON   (0x151)
 Offset for register BATMON. More...
 
#define RG_CCA_THRES   (0x149)
 Offset for register CCA_THRES. More...
 
#define RG_CSMA_BE   (0x16F)
 Offset for register CSMA_BE. More...
 
#define RG_CSMA_SEED_0   (0x16D)
 Offset for register CSMA_SEED_0. More...
 
#define RG_CSMA_SEED_1   (0x16E)
 Offset for register CSMA_SEED_1. More...
 
#define RG_FTN_CTRL   (0x158)
 Offset for register FTN_CTRL. More...
 
#define RG_IEEE_ADDR_0   (0x164)
 Offset for register IEEE_ADDR_0. More...
 
#define RG_IEEE_ADDR_1   (0x165)
 Offset for register IEEE_ADDR_1. More...
 
#define RG_IEEE_ADDR_2   (0x166)
 Offset for register IEEE_ADDR_2. More...
 
#define RG_IEEE_ADDR_3   (0x167)
 Offset for register IEEE_ADDR_3. More...
 
#define RG_IEEE_ADDR_4   (0x168)
 Offset for register IEEE_ADDR_4. More...
 
#define RG_IEEE_ADDR_5   (0x169)
 Offset for register IEEE_ADDR_5. More...
 
#define RG_IEEE_ADDR_6   (0x16A)
 Offset for register IEEE_ADDR_6. More...
 
#define RG_IEEE_ADDR_7   (0x16B)
 Offset for register IEEE_ADDR_7. More...
 
#define RG_IRQ_MASK   (0x14E)
 Offset for register IRQ_MASK. More...
 
#define RG_IRQ_STATUS   (0x14F)
 Offset for register IRQ_STATUS. More...
 
#define RG_MAN_ID_0   (0x15E)
 Offset for register MAN_ID_0. More...
 
#define RG_MAN_ID_1   (0x15F)
 Offset for register MAN_ID_1. More...
 
#define RG_PAN_ID_0   (0x162)
 Offset for register PAN_ID_0. More...
 
#define RG_PAN_ID_1   (0x163)
 Offset for register PAN_ID_1. More...
 
#define RG_PART_NUM   (0x15C)
 Offset for register PART_NUM. More...
 
#define RG_PHY_CC_CCA   (0x148)
 Offset for register PHY_CC_CCA. More...
 
#define RG_PHY_ED_LEVEL   (0x147)
 Offset for register PHY_ED_LEVEL. More...
 
#define RG_PHY_RSSI   (0x146)
 Offset for register PHY_RSSI. More...
 
#define RG_PHY_TX_PWR   (0x145)
 Offset for register PHY_TX_PWR. More...
 
#define RG_PLL_CF   (0x15A)
 Offset for register PLL_CF. More...
 
#define RG_PLL_DCU   (0x15B)
 Offset for register PLL_DCU. More...
 
#define RG_RX_CTRL   (0x14A)
 Offset for register RX_CTRL. More...
 
#define RG_RX_SYN   (0x155)
 Offset for register RX_SYN. More...
 
#define RG_SFD_VALUE   (0x14B)
 Offset for register SFD_VALUE. More...
 
#define RG_SHORT_ADDR_0   (0x160)
 Offset for register SHORT_ADDR_0. More...
 
#define RG_SHORT_ADDR_1   (0x161)
 Offset for register SHORT_ADDR_1. More...
 
#define RG_TRX_CTRL_0   (0x143)
 Offset for register TRX_CTRL_0. More...
 
#define RG_TRX_CTRL_1   (0x144)
 Offset for register TRX_CTRL_1. More...
 
#define RG_TRX_CTRL_2   (0x14C)
 Offset for register TRX_CTRL_2. More...
 
#define RG_TRX_STATE   (0x142)
 Offset for register TRX_STATE. More...
 
#define RG_TRX_STATUS   (0x141)
 Offset for register TRX_STATUS. More...
 
#define RG_TRXFBEND   (0x1FF)
 Offset for register TRXFBEND. More...
 
#define RG_TRXFBST   (0x180)
 Offset for register TRXFBST. More...
 
#define RG_TST_CTRL_DIGI   (0x176)
 Offset for register TST_CTRL_DIGI. More...
 
#define RG_TST_RX_LENGTH   (0x17B)
 Offset for register TST_RX_LENGTH. More...
 
#define RG_VERSION_NUM   (0x15D)
 Offset for register VERSION_NUM. More...
 
#define RG_VREG_CTRL   (0x150)
 Offset for register VREG_CTRL. More...
 
#define RG_XAH_CTRL_0   (0x16C)
 Offset for register XAH_CTRL_0. More...
 
#define RG_XAH_CTRL_1   (0x157)
 Offset for register XAH_CTRL_1. More...
 
#define RG_XOSC_CTRL   (0x152)
 Offset for register XOSC_CTRL. More...
 
#define RSSI_BASE_VAL_DBM   (-90)
 
#define RST_PULSE_WIDTH_US   (1)
 Typical timing values. More...
 
#define RX_DISABLE   (1)
 Constant RX_DISABLE for sub-register SR_RX_PDT_DIS in register RX_SYN. More...
 
#define RX_ENABLE   (0)
 Constant RX_ENABLE for sub-register SR_RX_PDT_DIS in register RX_SYN. More...
 
#define RX_SAFE_MODE_DISABLE   (0)
 Constant RX_SAFE_MODE_DISABLE for sub-register SR_RX_SAFE_MODE in register TRX_CTRL_2. More...
 
#define RX_SAFE_MODE_ENABLE   (1)
 Constant RX_SAFE_MODE_ENABLE for sub-register SR_RX_SAFE_MODE in register TRX_CTRL_2. More...
 
#define SLEEP_TO_TRX_OFF_MAX_US   (1000)
 
#define SLEEP_TO_TRX_OFF_TYP_US   (240)
 
#define SLOTTED_OPERATION_DISABLE   (0)
 Constant SLOTTED_OPERATION_DISABLE for sub-register SR_SLOTTED_OPERATION in register XAH_CTRL_0. More...
 
#define SLOTTED_OPERATION_EnABLE   (1)
 Constant SLOTTED_OPERATION_EnABLE for sub-register SR_SLOTTED_OPERATION in register XAH_CTRL_0. More...
 
#define SR_AACK_ACK_TIME   0x157, 0x04, 2
 Access parameters for sub-register AACK_ACK_TIME in register RG_XAH_CTRL_1. More...
 
#define SR_AACK_DIS_ACK   0x16E, 0x10, 4
 Access parameters for sub-register AACK_DIS_ACK in register RG_CSMA_SEED_1. More...
 
#define SR_AACK_FLTR_RES_FT   0x157, 0x20, 5
 Access parameters for sub-register AACK_FLTR_RES_FT in register RG_XAH_CTRL_1. More...
 
#define SR_AACK_FVN_MODE   0x16E, 0xC0, 6
 Access parameters for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1. More...
 
#define SR_AACK_I_AM_COORD   0x16E, 0x08, 3
 Access parameters for sub-register AACK_I_AM_COORD in register RG_CSMA_SEED_1. More...
 
#define SR_AACK_PROM_MODE   0x157, 0x02, 1
 Sub-registers of Register RG_XAH_CTRL_1. More...
 
#define SR_AACK_SET_PD   0x16E, 0x20, 5
 Access parameters for sub-register AACK_SET_PD in register RG_CSMA_SEED_1. More...
 
#define SR_AACK_UPLD_RES_FT   0x157, 0x10, 4
 Access parameters for sub-register AACK_UPLD_RES_FT in register RG_XAH_CTRL_1. More...
 
#define SR_AES_DIR   0x13C, 0x08, 3
 Access parameters for sub-register AES_DIR in register RG_AES_CTRL. More...
 
#define SR_AES_DONE   0x13D, 0x01, 0
 Sub-registers of Register RG_AES_STATUS. More...
 
#define SR_AES_ER   0x13D, 0x80, 7
 Access parameters for sub-register AES_ER in register RG_AES_STATUS. More...
 
#define SR_AES_IM   0x13C, 0x04, 2
 Sub-registers of Register RG_AES_CTRL. More...
 
#define SR_AES_MODE   0x13C, 0x20, 5
 Access parameters for sub-register AES_MODE in register RG_AES_CTRL. More...
 
#define SR_AES_REQUEST   0x13C, 0x80, 7
 Access parameters for sub-register AES_REQUEST in register RG_AES_CTRL. More...
 
#define SR_AMI   0x14F, 0x20, 5
 Access parameters for sub-register AMI in register RG_IRQ_STATUS. More...
 
#define SR_AMI_EN   0x14E, 0x20, 5
 Access parameters for sub-register AMI_EN in register RG_IRQ_MASK. More...
 
#define SR_ANT_CTRL   0x14D, 0x03, 0
 Sub-registers of Register RG_ANT_DIV. More...
 
#define SR_ANT_DIV_EN   0x14D, 0x08, 3
 Access parameters for sub-register ANT_DIV_EN in register RG_ANT_DIV. More...
 
#define SR_ANT_EXT_SW_EN   0x14D, 0x04, 2
 Access parameters for sub-register ANT_EXT_SW_EN in register RG_ANT_DIV. More...
 
#define SR_ANT_SEL   0x14D, 0x80, 7
 Access parameters for sub-register ANT_SEL in register RG_ANT_DIV. More...
 
#define SR_AVDD_OK   0x150, 0x40, 6
 Access parameters for sub-register AVDD_OK in register RG_VREG_CTRL. More...
 
#define SR_AVREG_EXT   0x150, 0x80, 7
 Access parameters for sub-register AVREG_EXT in register RG_VREG_CTRL. More...
 
#define SR_AWAKE   0x14F, 0x80, 7
 Access parameters for sub-register AWAKE in register RG_IRQ_STATUS. More...
 
#define SR_AWAKE_EN   0x14E, 0x80, 7
 Access parameters for sub-register AWAKE_EN in register RG_IRQ_MASK. More...
 
#define SR_BAT_LOW   0x151, 0x80, 7
 Access parameters for sub-register BAT_LOW in register RG_BATMON. More...
 
#define SR_BAT_LOW_EN   0x151, 0x40, 6
 Access parameters for sub-register BAT_LOW_EN in register RG_BATMON. More...
 
#define SR_BATMON_HR   0x151, 0x10, 4
 Access parameters for sub-register BATMON_HR in register RG_BATMON. More...
 
#define SR_BATMON_OK   0x151, 0x20, 5
 Access parameters for sub-register BATMON_OK in register RG_BATMON. More...
 
#define SR_BATMON_VTH   0x151, 0x0F, 0
 Sub-registers of Register RG_BATMON. More...
 
#define SR_CCA_CS_THRES   0x149, 0xF0, 4
 Access parameters for sub-register CCA_CS_THRES in register RG_CCA_THRES. More...
 
#define SR_CCA_DONE   0x141, 0x80, 7
 Access parameters for sub-register CCA_DONE in register RG_TRX_STATUS. More...
 
#define SR_CCA_ED_DONE   0x14F, 0x10, 4
 Access parameters for sub-register CCA_ED_DONE in register RG_IRQ_STATUS. More...
 
#define SR_CCA_ED_DONE_EN   0x14E, 0x10, 4
 Access parameters for sub-register CCA_ED_DONE_EN in register RG_IRQ_MASK. More...
 
#define SR_CCA_ED_THRES   0x149, 0x0F, 0
 Sub-registers of Register RG_CCA_THRES. More...
 
#define SR_CCA_MODE   0x148, 0x60, 5
 Access parameters for sub-register CCA_MODE in register RG_PHY_CC_CCA. More...
 
#define SR_CCA_REQUEST   0x148, 0x80, 7
 Access parameters for sub-register CCA_REQUEST in register RG_PHY_CC_CCA. More...
 
#define SR_CCA_STATUS   0x141, 0x40, 6
 Access parameters for sub-register CCA_STATUS in register RG_TRX_STATUS. More...
 
#define SR_CHANNEL   0x148, 0x1F, 0
 Sub-registers of Register RG_PHY_CC_CCA. More...
 
#define SR_CSMA_SEED_1   0x16E, 0x07, 0
 Sub-registers of Register RG_CSMA_SEED_1. More...
 
#define SR_DVDD_OK   0x150, 0x04, 2
 Sub-registers of Register RG_VREG_CTRL. More...
 
#define SR_DVREG_EXT   0x150, 0x08, 3
 Access parameters for sub-register DVREG_EXT in register RG_VREG_CTRL. More...
 
#define SR_FTN_START   0x158, 0x80, 7
 Sub-registers of Register RG_FTN_CTRL. More...
 
#define SR_IRQ_2_EXT_EN   0x144, 0x40, 6
 Access parameters for sub-register IRQ_2_EXT_EN in register RG_TRX_CTRL_1. More...
 
#define SR_MAX_BE   0x16F, 0xF0, 4
 Access parameters for sub-register MAX_BE in register RG_CSMA_BE. More...
 
#define SR_MAX_CSMA_RETRIES   0x16C, 0x0E, 1
 Access parameters for sub-register MAX_CSMA_RETRIES in register RG_XAH_CTRL_0. More...
 
#define SR_MAX_FRAME_RETRIES   0x16C, 0xF0, 4
 Access parameters for sub-register MAX_FRAME_RETRIES in register RG_XAH_CTRL_0. More...
 
#define SR_MIN_BE   0x16F, 0x0F, 0
 Sub-registers of Register RG_CSMA_BE. More...
 
#define SR_OQPSK_DATA_RATE   0x14C, 0x03, 0
 Sub-registers of Register RG_TRX_CTRL_2. More...
 
#define SR_PA_BUF_LT   0x145, 0xC0, 6
 Access parameters for sub-register PA_BUF_LT in register RG_PHY_TX_PWR. More...
 
#define SR_PA_EXT_EN   0x144, 0x80, 7
 Access parameters for sub-register PA_EXT_EN in register RG_TRX_CTRL_1. More...
 
#define SR_PA_LT   0x145, 0x30, 4
 Access parameters for sub-register PA_LT in register RG_PHY_TX_PWR. More...
 
#define SR_PDT_THRES   0x14A, 0x0F, 0
 Sub-registers of Register RG_RX_CTRL. More...
 
#define SR_PLL_CF_START   0x15A, 0x80, 7
 Sub-registers of Register RG_PLL_CF. More...
 
#define SR_PLL_DCU_START   0x15B, 0x80, 7
 Sub-registers of Register RG_PLL_DCU. More...
 
#define SR_PLL_LOCK   0x14F, 0x01, 0
 Sub-registers of Register RG_IRQ_STATUS. More...
 
#define SR_PLL_LOCK_EN   0x14E, 0x01, 0
 Sub-registers of Register RG_IRQ_MASK. More...
 
#define SR_PLL_UNLOCK   0x14F, 0x02, 1
 Access parameters for sub-register PLL_UNLOCK in register RG_IRQ_STATUS. More...
 
#define SR_PLL_UNLOCK_EN   0x14E, 0x02, 1
 Access parameters for sub-register PLL_UNLOCK_EN in register RG_IRQ_MASK. More...
 
#define SR_RND_VALUE   0x146, 0x60, 5
 Access parameters for sub-register RND_VALUE in register RG_PHY_RSSI. More...
 
#define SR_RSSI   0x146, 0x1F, 0
 Sub-registers of Register RG_PHY_RSSI. More...
 
#define SR_RX_CRC_VALID   0x146, 0x80, 7
 Access parameters for sub-register RX_CRC_VALID in register RG_PHY_RSSI. More...
 
#define SR_RX_END   0x14F, 0x08, 3
 Access parameters for sub-register RX_END in register RG_IRQ_STATUS. More...
 
#define SR_RX_END_EN   0x14E, 0x08, 3
 Access parameters for sub-register RX_END_EN in register RG_IRQ_MASK. More...
 
#define SR_RX_PDT_DIS   0x155, 0x80, 7
 Access parameters for sub-register RX_PDT_DIS in register RG_RX_SYN. More...
 
#define SR_RX_PDT_LEVEL   0x155, 0x0F, 0
 Sub-registers of Register RG_RX_SYN. More...
 
#define SR_RX_SAFE_MODE   0x14C, 0x80, 7
 Access parameters for sub-register RX_SAFE_MODE in register RG_TRX_CTRL_2. More...
 
#define SR_RX_START   0x14F, 0x04, 2
 Access parameters for sub-register RX_START in register RG_IRQ_STATUS. More...
 
#define SR_RX_START_EN   0x14E, 0x04, 2
 Access parameters for sub-register RX_START_EN in register RG_IRQ_MASK. More...
 
#define SR_SLOTTED_OPERATION   0x16C, 0x01, 0
 Sub-registers of Register RG_XAH_CTRL_0. More...
 
#define SR_TRAC_STATUS   0x142, 0xE0, 5
 Access parameters for sub-register TRAC_STATUS in register RG_TRX_STATE. More...
 
#define SR_TRX_CMD   0x142, 0x1F, 0
 Sub-registers of Register RG_TRX_STATE. More...
 
#define SR_TRX_STATUS   0x141, 0x1F, 0
 Sub-registers of Register RG_TRX_STATUS. More...
 
#define SR_TST_CTRL_DIG   0x176, 0x0F, 0
 Sub-registers of Register RG_TST_CTRL_DIGI. More...
 
#define SR_TST_STATUS   0x141, 0x20, 5
 Access parameters for sub-register TST_STATUS in register RG_TRX_STATUS. More...
 
#define SR_TX_AUTO_CRC_ON   0x144, 0x20, 5
 Sub-registers of Register RG_TRX_CTRL_1. More...
 
#define SR_TX_END   0x14F, 0x40, 6
 Access parameters for sub-register TX_END in register RG_IRQ_STATUS. More...
 
#define SR_TX_END_EN   0x14E, 0x40, 6
 Access parameters for sub-register TX_END_EN in register RG_IRQ_MASK. More...
 
#define SR_TX_PWR   0x145, 0x0F, 0
 Sub-registers of Register RG_PHY_TX_PWR. More...
 
#define SR_XTAL_MODE   0x152, 0xF0, 4
 Access parameters for sub-register XTAL_MODE in register RG_XOSC_CTRL. More...
 
#define SR_XTAL_TRIM   0x152, 0x0F, 0
 Sub-registers of Register RG_XOSC_CTRL. More...
 
#define THRES_ANT_DIV_DISABLE   (0x7)
 Constant THRES_ANT_DIV_DISABLE for sub-register SR_PDT_THRES in register RX_CTRL. More...
 
#define THRES_ANT_DIV_ENABLE   (0x3)
 Constant THRES_ANT_DIV_ENABLE for sub-register SR_PDT_THRES in register RX_CTRL. More...
 
#define TRANSCEIVER_NAME   "ATMEGARFA1"
 
#define TRX_IRQ_DELAY_US   (9)
 
#define TRX_OFF_TO_PLL_ON_TIME_US   (110)
 
#define TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES   (35)
 
#define TRX_SUPPORTED_CHANNELS   (0x07FFF800)
 Parameter definitions. More...
 
#define TX_AUTO_CRC_DISABLE   (0)
 Constant TX_AUTO_CRC_DISABLE for sub-register SR_TX_AUTO_CRC_ON in register TRX_CTRL_1. More...
 
#define TX_AUTO_CRC_ENABLE   (1)
 Constant TX_AUTO_CRC_ENABLE for sub-register SR_TX_AUTO_CRC_ON in register TRX_CTRL_1. More...
 
#define TX_PWR_TOLERANCE   (0x80)
 

Typedefs

typedef enum tal_trx_status_tag tal_trx_status_t
 Enumerations. More...
 
typedef enum trx_cmd_tag trx_cmd_t
 sub-register TRX_CMD in register TRX_STATE More...
 
typedef enum trx_trac_status_tag trx_trac_status_t
 sub-register TRAC_STATUS in register TRX_STATE More...
 

Enumerations

enum  tal_trx_status_tag {
  P_ON = (0x00),
  BUSY_RX = (0x01),
  BUSY_TX = (0x02),
  RX_ON = (0x06),
  TRX_OFF = (0x08),
  PLL_ON = (0x09),
  TRX_SLEEP = (0x0F),
  BUSY_RX_AACK = (0x11),
  BUSY_TX_ARET = (0x12),
  RX_AACK_ON = (0x16),
  TX_ARET_ON = (0x19),
  RX_ON_NOCLK = (0x1C),
  RX_AACK_ON_NOCLK = (0x1D),
  BUSY_RX_AACK_NOCLK = (0x1E),
  STATE_TRANSITION_IN_PROGRESS = (0x1F),
  P_ON = (0x00),
  BUSY_RX = (0x01),
  BUSY_TX = (0x02),
  RX_ON = (0x06),
  TRX_OFF = (0x08),
  PLL_ON = (0x09),
  TRX_SLEEP = (0x0F),
  BUSY_RX_AACK = (0x11),
  BUSY_TX_ARET = (0x12),
  RX_AACK_ON = (0x16),
  TX_ARET_ON = (0x19),
  RX_ON_NOCLK = (0x1C),
  RX_AACK_ON_NOCLK = (0x1D),
  BUSY_RX_AACK_NOCLK = (0x1E),
  STATE_TRANSITION_IN_PROGRESS = (0x1F),
  P_ON = (0),
  BUSY_RX = (1),
  BUSY_TX = (2),
  RX_ON = (6),
  TRX_OFF = (8),
  PLL_ON = (9),
  TRX_SLEEP = (15),
  BUSY_RX_AACK = (17),
  BUSY_TX_ARET = (18),
  RX_AACK_ON = (22),
  TX_ARET_ON = (25),
  RX_ON_NOCLK = (28),
  RX_AACK_ON_NOCLK = (29),
  BUSY_RX_AACK_NOCLK = (30),
  STATE_TRANSITION_IN_PROGRESS = (31)
}
 Enumerations. More...
 
enum  trx_cmd_tag {
  CMD_NOP = (0x00),
  CMD_TX_START = (0x02),
  CMD_FORCE_TRX_OFF = (0x03),
  CMD_FORCE_PLL_ON = (0x04),
  CMD_RX_ON = (0x06),
  CMD_TRX_OFF = (0x08),
  CMD_PLL_ON = (0x09),
  CMD_RX_AACK_ON = (0x16),
  CMD_TX_ARET_ON = (0x19),
  CMD_SLEEP = (0x0F),
  CMD_NOP = (0x00),
  CMD_TX_START = (0x02),
  CMD_FORCE_TRX_OFF = (0x03),
  CMD_FORCE_PLL_ON = (0x04),
  CMD_RX_ON = (0x06),
  CMD_TRX_OFF = (0x08),
  CMD_PLL_ON = (0x09),
  CMD_RX_AACK_ON = (0x16),
  CMD_TX_ARET_ON = (0x19),
  CMD_SLEEP = (0x0F),
  CMD_NOP = (0),
  CMD_TX_START = (2),
  CMD_FORCE_TRX_OFF = (3),
  CMD_FORCE_PLL_ON = (4),
  CMD_RX_ON = (6),
  CMD_TRX_OFF = (8),
  CMD_PLL_ON = (9),
  CMD_SLEEP = (15),
  CMD_RX_AACK_ON = (22),
  CMD_TX_ARET_ON = (25)
}
 sub-register TRX_CMD in register TRX_STATE More...
 
enum  trx_trac_status_tag {
  TRAC_SUCCESS = (0),
  TRAC_SUCCESS_DATA_PENDING = (1),
  TRAC_SUCCESS_WAIT_FOR_ACK = (2),
  TRAC_CHANNEL_ACCESS_FAILURE = (3),
  TRAC_NO_ACK = (5),
  TRAC_INVALID = (7),
  TRAC_SUCCESS = (0),
  TRAC_SUCCESS_DATA_PENDING = (1),
  TRAC_SUCCESS_WAIT_FOR_ACK = (2),
  TRAC_CHANNEL_ACCESS_FAILURE = (3),
  TRAC_NO_ACK = (5),
  TRAC_INVALID = (7),
  TRAC_SUCCESS = 0,
  TRAC_SUCCESS_DATA_PENDING = 1,
  TRAC_WAIT_FOR_ACK = 2,
  TRAC_CHANNEL_ACCESS_FAILURE = 3,
  TRAC_NO_ACK = 5,
  TRAC_INVALID = 7
}
 sub-register TRAC_STATUS in register TRX_STATE More...
 

#define ACK_DISABLE   (1)

Constant ACK_DISABLE for sub-register SR_AACK_DIS_ACK in register CSMA_SEED_1.

#define ACK_ENABLE   (0)

Constant ACK_ENABLE for sub-register SR_AACK_DIS_ACK in register CSMA_SEED_1.

#define ACK_TIME_12_SYMBOLS   (0)

Constant ACK_TIME_12_SYMBOLS for sub-register SR_AACK_ACK_TIME in register XAH_CTRL_1.

#define ACK_TIME_2_SYMBOLS   (1)

Constant ACK_TIME_2_SYMBOLS for sub-register SR_AACK_ACK_TIME in register XAH_CTRL_1.

#define AES_COMPLETED   (1)

Constant AES_COMPLETED for sub-register SR_AES_DONE in register AES_STATUS.

#define AES_DIR_DECRYPT   (1)

Constant AES_DIR_DECRYPT for sub-register SR_AES_DIR in register AES_CTRL.

#define AES_DIR_ENCRYPT   (0)

Constant AES_DIR_ENCRYPT for sub-register SR_AES_DIR in register AES_CTRL.

#define AES_NOT_COMPLETED   (0)

Constant AES_NOT_COMPLETED for sub-register SR_AES_DONE in register AES_STATUS.

#define AES_START   (1)

Constant AES_START for sub-register SR_AES_REQUEST in register AES_CTRL.

#define ANT_DIV_DISABLE   (0)

Constant ANT_DIV_DISABLE for sub-register SR_ANT_DIV_EN in register ANT_DIV.

#define ANT_DIV_ENABLE   (1)

Constant ANT_DIV_ENABLE for sub-register SR_ANT_DIV_EN in register ANT_DIV.

#define ANT_EXT_SW_DISABLE   (0)

Constant ANT_EXT_SW_DISABLE for sub-register SR_ANT_EXT_SW_EN in register ANT_DIV.

#define ANT_EXT_SW_ENABLE   (1)

Constant ANT_EXT_SW_ENABLE for sub-register SR_ANT_EXT_SW_EN in register ANT_DIV.

#define ATMEGA128RFA1_PART_NUM   (0x83)

Constant ATMEGA128RFA1_PART_NUM for sub-register SR_PART_NUM in register PART_NUM.

Referenced by trx_init().

#define BATMON_ABOVE_THRES   (1)

Constant BATMON_ABOVE_THRES for sub-register SR_BATMON_OK in register BATMON.

#define BATMON_BELOW_THRES   (0)

Constant BATMON_BELOW_THRES for sub-register SR_BATMON_OK in register BATMON.

#define BATMON_HIGH_RANGE   (1)

Constant BATMON_HIGH_RANGE for sub-register SR_BATMON_HR in register BATMON.

#define BATMON_LOW_RANGE   (0)

Constant BATMON_LOW_RANGE for sub-register SR_BATMON_HR in register BATMON.

#define CCA_CH_BUSY   (0)

Constant CCA_CH_BUSY for sub-register SR_CCA_STATUS in register TRX_STATUS.

#define CCA_CH_IDLE   (1)

Constant CCA_CH_IDLE for sub-register SR_CCA_STATUS in register TRX_STATUS.

#define CCA_COMPLETED   (1)

Constant CCA_COMPLETED for sub-register SR_CCA_DONE in register TRX_STATUS.

#define CCA_DETECTION_TIME_SYM   (8)

CSMA timimg parameters.

#define CCA_DURATION_SYM
Value:
( \
CCA_DETECTION_TIME_SYM + CCA_PROCESS_TIME_SYM)
CCA_PROCESS_TIME_SYM
#define CCA_PROCESS_TIME_SYM
Definition: wireless/avr2025_mac/source/tal/atmegarfa1/inc/atmega128rfa1.h:130
CCA_DETECTION_TIME_SYM
#define CCA_DETECTION_TIME_SYM
CSMA timimg parameters.
Definition: wireless/avr2025_mac/source/tal/atmegarfa1/inc/atmega128rfa1.h:126
#define CCA_MODE_0   (0)

Constant CCA_MODE_0 for sub-register SR_CCA_MODE in register PHY_CC_CCA.

#define CCA_MODE_1   (1)

Constant CCA_MODE_1 for sub-register SR_CCA_MODE in register PHY_CC_CCA.

#define CCA_MODE_2   (2)

Constant CCA_MODE_2 for sub-register SR_CCA_MODE in register PHY_CC_CCA.

#define CCA_MODE_3   (3)

Constant CCA_MODE_3 for sub-register SR_CCA_MODE in register PHY_CC_CCA.

#define CCA_NOT_COMPLETED   (0)

Constant CCA_NOT_COMPLETED for sub-register SR_CCA_DONE in register TRX_STATUS.

#define CCA_PRE_START_DURATION_US   (20)
#define CCA_PREPARATION_DURATION_US   (50)
#define CCA_PROCESS_TIME_SYM   (1)
#define CCA_START   (1)

Constant CCA_START for sub-register SR_CCA_REQUEST in register PHY_CC_CCA.

#define CRC16_NOT_VALID   (0)

Constant CRC16_NOT_VALID for sub-register SR_RX_CRC_VALID in register PHY_RSSI.

#define CRC16_VALID   (1)

Constant CRC16_VALID for sub-register SR_RX_CRC_VALID in register PHY_RSSI.

#define FRAME_VERSION_0   (0)

Constant FRAME_VERSION_0 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1.

#define FRAME_VERSION_01   (1)

Constant FRAME_VERSION_01 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1.

#define FRAME_VERSION_012   (2)

Constant FRAME_VERSION_012 for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1.

#define FRAME_VERSION_IGNORED   (3)

Constant FRAME_VERSION_IGNORED for sub-register SR_AACK_FVN_MODE in register CSMA_SEED_1.

#define I_AM_COORD_DISABLE   (0)

Constant I_AM_COORD_DISABLE for sub-register SR_AACK_I_AM_COORD in register CSMA_SEED_1.

#define I_AM_COORD_ENABLE   (1)

Constant I_AM_COORD_ENABLE for sub-register SR_AACK_I_AM_COORD in register CSMA_SEED_1.

#define IRQ_PROCESSING_DLY_US   (32)
#define P_ON_TO_CLKM_AVAILABLE_MAX_US   (1000)
#define P_ON_TO_CLKM_AVAILABLE_TYP_US   (380)
#define PA_LT_2_US   (0)

Constant PA_LT_2_US for sub-register SR_PA_LT in register PHY_TX_PWR.

#define PA_LT_4_US   (1)

Constant PA_LT_4_US for sub-register SR_PA_LT in register PHY_TX_PWR.

#define PA_LT_6_US   (2)

Constant PA_LT_6_US for sub-register SR_PA_LT in register PHY_TX_PWR.

#define PA_LT_8_US   (3)

Constant PA_LT_8_US for sub-register SR_PA_LT in register PHY_TX_PWR.

#define PD_ACK_BIT_SET_DISABLE   (0)

Constant PD_ACK_BIT_SET_DISABLE for sub-register SR_AACK_SET_PD in register CSMA_SEED_1.

#define PD_ACK_BIT_SET_ENABLE   (1)

Constant PD_ACK_BIT_SET_ENABLE for sub-register SR_AACK_SET_PD in register CSMA_SEED_1.

#define PRE_TX_DURATION_US   (32)
#define PROM_MODE_DISABLE   (0)

Constant PROM_MODE_DISABLE for sub-register SR_AACK_PROM_MODE in register XAH_CTRL_1.

#define PROM_MODE_ENABLE   (1)

Constant PROM_MODE_ENABLE for sub-register SR_AACK_PROM_MODE in register XAH_CTRL_1.

#define RATE_1_MBPS   (2)

Constant RATE_1_MBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2.

#define RATE_250_KBPS   (0)

Constant RATE_250_KBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2.

#define RATE_2_MBPS   (3)

Constant RATE_2_MBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2.

#define RATE_500_KBPS   (1)

Constant RATE_500_KBPS for sub-register SR_OQPSK_DATA_RATE in register TRX_CTRL_2.

#define RESET_TO_TRX_OFF_MAX_US   (1000)
#define RESET_TO_TRX_OFF_TYP_US   (37)
#define REV_AB   (2)

Constant REV_AB for sub-register SR_VERSION_NUM in register VERSION_NUM.

#define REV_C   (3)

Constant REV_C for sub-register SR_VERSION_NUM in register VERSION_NUM.

#define REV_D   (4)

Constant REV_D for sub-register SR_VERSION_NUM in register VERSION_NUM.

#define REV_F   (12)

Constant REV_F for sub-register SR_VERSION_NUM in register VERSION_NUM.

#define RG_AES_CTRL   (0x13C)

Register addresses.

Offset for register AES_CTRL

#define RG_AES_KEY   (0x13F)

Offset for register AES_KEY.

#define RG_AES_STATE   (0x13E)

Offset for register AES_STATE.

#define RG_AES_STATUS   (0x13D)

Offset for register AES_STATUS.

#define RG_ANT_DIV   (0x14D)

Offset for register ANT_DIV.

#define RG_BATMON   (0x151)

Offset for register BATMON.

#define RG_CCA_THRES   (0x149)

Offset for register CCA_THRES.

#define RG_CSMA_BE   (0x16F)

Offset for register CSMA_BE.

#define RG_CSMA_SEED_0   (0x16D)

Offset for register CSMA_SEED_0.

#define RG_CSMA_SEED_1   (0x16E)

Offset for register CSMA_SEED_1.

#define RG_FTN_CTRL   (0x158)

Offset for register FTN_CTRL.

#define RG_IEEE_ADDR_0   (0x164)

Offset for register IEEE_ADDR_0.

#define RG_IEEE_ADDR_1   (0x165)

Offset for register IEEE_ADDR_1.

#define RG_IEEE_ADDR_2   (0x166)

Offset for register IEEE_ADDR_2.

#define RG_IEEE_ADDR_3   (0x167)

Offset for register IEEE_ADDR_3.

#define RG_IEEE_ADDR_4   (0x168)

Offset for register IEEE_ADDR_4.

#define RG_IEEE_ADDR_5   (0x169)

Offset for register IEEE_ADDR_5.

#define RG_IEEE_ADDR_6   (0x16A)

Offset for register IEEE_ADDR_6.

#define RG_IEEE_ADDR_7   (0x16B)

Offset for register IEEE_ADDR_7.

#define RG_IRQ_MASK   (0x14E)

Offset for register IRQ_MASK.

#define RG_IRQ_STATUS   (0x14F)

Offset for register IRQ_STATUS.

#define RG_MAN_ID_0   (0x15E)

Offset for register MAN_ID_0.

#define RG_MAN_ID_1   (0x15F)

Offset for register MAN_ID_1.

#define RG_PAN_ID_0   (0x162)

Offset for register PAN_ID_0.

#define RG_PAN_ID_1   (0x163)

Offset for register PAN_ID_1.

#define RG_PART_NUM   (0x15C)

Offset for register PART_NUM.

#define RG_PHY_CC_CCA   (0x148)

Offset for register PHY_CC_CCA.

#define RG_PHY_ED_LEVEL   (0x147)

Offset for register PHY_ED_LEVEL.

#define RG_PHY_RSSI   (0x146)

Offset for register PHY_RSSI.

#define RG_PHY_TX_PWR   (0x145)

Offset for register PHY_TX_PWR.

#define RG_PLL_CF   (0x15A)

Offset for register PLL_CF.

#define RG_PLL_DCU   (0x15B)

Offset for register PLL_DCU.

#define RG_RX_CTRL   (0x14A)

Offset for register RX_CTRL.

#define RG_RX_SYN   (0x155)

Offset for register RX_SYN.

#define RG_SFD_VALUE   (0x14B)

Offset for register SFD_VALUE.

#define RG_SHORT_ADDR_0   (0x160)

Offset for register SHORT_ADDR_0.

#define RG_SHORT_ADDR_1   (0x161)

Offset for register SHORT_ADDR_1.

#define RG_TRX_CTRL_0   (0x143)

Offset for register TRX_CTRL_0.

#define RG_TRX_CTRL_1   (0x144)

Offset for register TRX_CTRL_1.

#define RG_TRX_CTRL_2   (0x14C)

Offset for register TRX_CTRL_2.

#define RG_TRX_STATE   (0x142)

Offset for register TRX_STATE.

#define RG_TRX_STATUS   (0x141)

Offset for register TRX_STATUS.

#define RG_TRXFBEND   (0x1FF)

Offset for register TRXFBEND.

#define RG_TRXFBST   (0x180)

Offset for register TRXFBST.

#define RG_TST_CTRL_DIGI   (0x176)

Offset for register TST_CTRL_DIGI.

#define RG_TST_RX_LENGTH   (0x17B)

Offset for register TST_RX_LENGTH.

#define RG_VERSION_NUM   (0x15D)

Offset for register VERSION_NUM.

#define RG_VREG_CTRL   (0x150)

Offset for register VREG_CTRL.

#define RG_XAH_CTRL_0   (0x16C)

Offset for register XAH_CTRL_0.

#define RG_XAH_CTRL_1   (0x157)

Offset for register XAH_CTRL_1.

#define RG_XOSC_CTRL   (0x152)

Offset for register XOSC_CTRL.

#define RSSI_BASE_VAL_DBM   (-90)
#define RST_PULSE_WIDTH_US   (1)

Typical timing values.

#define RX_DISABLE   (1)

Constant RX_DISABLE for sub-register SR_RX_PDT_DIS in register RX_SYN.

#define RX_ENABLE   (0)

Constant RX_ENABLE for sub-register SR_RX_PDT_DIS in register RX_SYN.

#define RX_SAFE_MODE_DISABLE   (0)

Constant RX_SAFE_MODE_DISABLE for sub-register SR_RX_SAFE_MODE in register TRX_CTRL_2.

#define RX_SAFE_MODE_ENABLE   (1)

Constant RX_SAFE_MODE_ENABLE for sub-register SR_RX_SAFE_MODE in register TRX_CTRL_2.

#define SLEEP_TO_TRX_OFF_MAX_US   (1000)
#define SLEEP_TO_TRX_OFF_TYP_US   (240)
#define SLOTTED_OPERATION_DISABLE   (0)

Constant SLOTTED_OPERATION_DISABLE for sub-register SR_SLOTTED_OPERATION in register XAH_CTRL_0.

#define SLOTTED_OPERATION_EnABLE   (1)

Constant SLOTTED_OPERATION_EnABLE for sub-register SR_SLOTTED_OPERATION in register XAH_CTRL_0.

#define SR_AACK_ACK_TIME   0x157, 0x04, 2

Access parameters for sub-register AACK_ACK_TIME in register RG_XAH_CTRL_1.

#define SR_AACK_DIS_ACK   0x16E, 0x10, 4

Access parameters for sub-register AACK_DIS_ACK in register RG_CSMA_SEED_1.

#define SR_AACK_FLTR_RES_FT   0x157, 0x20, 5

Access parameters for sub-register AACK_FLTR_RES_FT in register RG_XAH_CTRL_1.

#define SR_AACK_FVN_MODE   0x16E, 0xC0, 6

Access parameters for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1.

#define SR_AACK_I_AM_COORD   0x16E, 0x08, 3

Access parameters for sub-register AACK_I_AM_COORD in register RG_CSMA_SEED_1.

#define SR_AACK_PROM_MODE   0x157, 0x02, 1

Sub-registers of Register RG_XAH_CTRL_1.

Access parameters for sub-register AACK_PROM_MODE in register RG_XAH_CTRL_1

#define SR_AACK_SET_PD   0x16E, 0x20, 5

Access parameters for sub-register AACK_SET_PD in register RG_CSMA_SEED_1.

#define SR_AACK_UPLD_RES_FT   0x157, 0x10, 4

Access parameters for sub-register AACK_UPLD_RES_FT in register RG_XAH_CTRL_1.

#define SR_AES_DIR   0x13C, 0x08, 3

Access parameters for sub-register AES_DIR in register RG_AES_CTRL.

#define SR_AES_DONE   0x13D, 0x01, 0

Sub-registers of Register RG_AES_STATUS.

Access parameters for sub-register AES_DONE in register RG_AES_STATUS

#define SR_AES_ER   0x13D, 0x80, 7

Access parameters for sub-register AES_ER in register RG_AES_STATUS.

#define SR_AES_IM   0x13C, 0x04, 2

Sub-registers of Register RG_AES_CTRL.

Access parameters for sub-register AES_IM in register RG_AES_CTRL

#define SR_AES_MODE   0x13C, 0x20, 5

Access parameters for sub-register AES_MODE in register RG_AES_CTRL.

#define SR_AES_REQUEST   0x13C, 0x80, 7

Access parameters for sub-register AES_REQUEST in register RG_AES_CTRL.

#define SR_AMI   0x14F, 0x20, 5

Access parameters for sub-register AMI in register RG_IRQ_STATUS.

#define SR_AMI_EN   0x14E, 0x20, 5

Access parameters for sub-register AMI_EN in register RG_IRQ_MASK.

#define SR_ANT_CTRL   0x14D, 0x03, 0

Sub-registers of Register RG_ANT_DIV.

Access parameters for sub-register ANT_CTRL in register RG_ANT_DIV

#define SR_ANT_DIV_EN   0x14D, 0x08, 3

Access parameters for sub-register ANT_DIV_EN in register RG_ANT_DIV.

#define SR_ANT_EXT_SW_EN   0x14D, 0x04, 2

Access parameters for sub-register ANT_EXT_SW_EN in register RG_ANT_DIV.

#define SR_ANT_SEL   0x14D, 0x80, 7

Access parameters for sub-register ANT_SEL in register RG_ANT_DIV.

#define SR_AVDD_OK   0x150, 0x40, 6

Access parameters for sub-register AVDD_OK in register RG_VREG_CTRL.

#define SR_AVREG_EXT   0x150, 0x80, 7

Access parameters for sub-register AVREG_EXT in register RG_VREG_CTRL.

#define SR_AWAKE   0x14F, 0x80, 7

Access parameters for sub-register AWAKE in register RG_IRQ_STATUS.

#define SR_AWAKE_EN   0x14E, 0x80, 7

Access parameters for sub-register AWAKE_EN in register RG_IRQ_MASK.

#define SR_BAT_LOW   0x151, 0x80, 7

Access parameters for sub-register BAT_LOW in register RG_BATMON.

#define SR_BAT_LOW_EN   0x151, 0x40, 6

Access parameters for sub-register BAT_LOW_EN in register RG_BATMON.

#define SR_BATMON_HR   0x151, 0x10, 4

Access parameters for sub-register BATMON_HR in register RG_BATMON.

#define SR_BATMON_OK   0x151, 0x20, 5

Access parameters for sub-register BATMON_OK in register RG_BATMON.

#define SR_BATMON_VTH   0x151, 0x0F, 0

Sub-registers of Register RG_BATMON.

Access parameters for sub-register BATMON_VTH in register RG_BATMON

#define SR_CCA_CS_THRES   0x149, 0xF0, 4

Access parameters for sub-register CCA_CS_THRES in register RG_CCA_THRES.

#define SR_CCA_DONE   0x141, 0x80, 7

Access parameters for sub-register CCA_DONE in register RG_TRX_STATUS.

#define SR_CCA_ED_DONE   0x14F, 0x10, 4

Access parameters for sub-register CCA_ED_DONE in register RG_IRQ_STATUS.

#define SR_CCA_ED_DONE_EN   0x14E, 0x10, 4

Access parameters for sub-register CCA_ED_DONE_EN in register RG_IRQ_MASK.

#define SR_CCA_ED_THRES   0x149, 0x0F, 0

Sub-registers of Register RG_CCA_THRES.

Access parameters for sub-register CCA_ED_THRES in register RG_CCA_THRES

#define SR_CCA_MODE   0x148, 0x60, 5

Access parameters for sub-register CCA_MODE in register RG_PHY_CC_CCA.

#define SR_CCA_REQUEST   0x148, 0x80, 7

Access parameters for sub-register CCA_REQUEST in register RG_PHY_CC_CCA.

#define SR_CCA_STATUS   0x141, 0x40, 6

Access parameters for sub-register CCA_STATUS in register RG_TRX_STATUS.

#define SR_CHANNEL   0x148, 0x1F, 0

Sub-registers of Register RG_PHY_CC_CCA.

Access parameters for sub-register CHANNEL in register RG_PHY_CC_CCA

#define SR_CSMA_SEED_1   0x16E, 0x07, 0

Sub-registers of Register RG_CSMA_SEED_1.

Access parameters for sub-register CSMA_SEED_1 in register RG_CSMA_SEED_1

#define SR_DVDD_OK   0x150, 0x04, 2

Sub-registers of Register RG_VREG_CTRL.

Access parameters for sub-register DVDD_OK in register RG_VREG_CTRL

#define SR_DVREG_EXT   0x150, 0x08, 3

Access parameters for sub-register DVREG_EXT in register RG_VREG_CTRL.

#define SR_FTN_START   0x158, 0x80, 7

Sub-registers of Register RG_FTN_CTRL.

Access parameters for sub-register FTN_START in register RG_FTN_CTRL

#define SR_IRQ_2_EXT_EN   0x144, 0x40, 6

Access parameters for sub-register IRQ_2_EXT_EN in register RG_TRX_CTRL_1.

#define SR_MAX_BE   0x16F, 0xF0, 4

Access parameters for sub-register MAX_BE in register RG_CSMA_BE.

#define SR_MAX_CSMA_RETRIES   0x16C, 0x0E, 1

Access parameters for sub-register MAX_CSMA_RETRIES in register RG_XAH_CTRL_0.

#define SR_MAX_FRAME_RETRIES   0x16C, 0xF0, 4

Access parameters for sub-register MAX_FRAME_RETRIES in register RG_XAH_CTRL_0.

#define SR_MIN_BE   0x16F, 0x0F, 0

Sub-registers of Register RG_CSMA_BE.

Access parameters for sub-register MIN_BE in register RG_CSMA_BE

#define SR_OQPSK_DATA_RATE   0x14C, 0x03, 0

Sub-registers of Register RG_TRX_CTRL_2.

Access parameters for sub-register OQPSK_DATA_RATE in register RG_TRX_CTRL_2

#define SR_PA_BUF_LT   0x145, 0xC0, 6

Access parameters for sub-register PA_BUF_LT in register RG_PHY_TX_PWR.

#define SR_PA_EXT_EN   0x144, 0x80, 7

Access parameters for sub-register PA_EXT_EN in register RG_TRX_CTRL_1.

#define SR_PA_LT   0x145, 0x30, 4

Access parameters for sub-register PA_LT in register RG_PHY_TX_PWR.

#define SR_PDT_THRES   0x14A, 0x0F, 0

Sub-registers of Register RG_RX_CTRL.

Access parameters for sub-register PDT_THRES in register RG_RX_CTRL

#define SR_PLL_CF_START   0x15A, 0x80, 7

Sub-registers of Register RG_PLL_CF.

Access parameters for sub-register PLL_CF_START in register RG_PLL_CF

#define SR_PLL_DCU_START   0x15B, 0x80, 7

Sub-registers of Register RG_PLL_DCU.

Access parameters for sub-register PLL_DCU_START in register RG_PLL_DCU

#define SR_PLL_LOCK   0x14F, 0x01, 0

Sub-registers of Register RG_IRQ_STATUS.

Access parameters for sub-register PLL_LOCK in register RG_IRQ_STATUS

#define SR_PLL_LOCK_EN   0x14E, 0x01, 0

Sub-registers of Register RG_IRQ_MASK.

Access parameters for sub-register PLL_LOCK_EN in register RG_IRQ_MASK

#define SR_PLL_UNLOCK   0x14F, 0x02, 1

Access parameters for sub-register PLL_UNLOCK in register RG_IRQ_STATUS.

#define SR_PLL_UNLOCK_EN   0x14E, 0x02, 1

Access parameters for sub-register PLL_UNLOCK_EN in register RG_IRQ_MASK.

#define SR_RND_VALUE   0x146, 0x60, 5

Access parameters for sub-register RND_VALUE in register RG_PHY_RSSI.

#define SR_RSSI   0x146, 0x1F, 0

Sub-registers of Register RG_PHY_RSSI.

Access parameters for sub-register RSSI in register RG_PHY_RSSI

#define SR_RX_CRC_VALID   0x146, 0x80, 7

Access parameters for sub-register RX_CRC_VALID in register RG_PHY_RSSI.

#define SR_RX_END   0x14F, 0x08, 3

Access parameters for sub-register RX_END in register RG_IRQ_STATUS.

#define SR_RX_END_EN   0x14E, 0x08, 3

Access parameters for sub-register RX_END_EN in register RG_IRQ_MASK.

#define SR_RX_PDT_DIS   0x155, 0x80, 7

Access parameters for sub-register RX_PDT_DIS in register RG_RX_SYN.

#define SR_RX_PDT_LEVEL   0x155, 0x0F, 0

Sub-registers of Register RG_RX_SYN.

Access parameters for sub-register RX_PDT_LEVEL in register RG_RX_SYN

#define SR_RX_SAFE_MODE   0x14C, 0x80, 7

Access parameters for sub-register RX_SAFE_MODE in register RG_TRX_CTRL_2.

#define SR_RX_START   0x14F, 0x04, 2

Access parameters for sub-register RX_START in register RG_IRQ_STATUS.

#define SR_RX_START_EN   0x14E, 0x04, 2

Access parameters for sub-register RX_START_EN in register RG_IRQ_MASK.

#define SR_SLOTTED_OPERATION   0x16C, 0x01, 0

Sub-registers of Register RG_XAH_CTRL_0.

Access parameters for sub-register SLOTTED_OPERATION in register RG_XAH_CTRL_0

#define SR_TRAC_STATUS   0x142, 0xE0, 5

Access parameters for sub-register TRAC_STATUS in register RG_TRX_STATE.

#define SR_TRX_CMD   0x142, 0x1F, 0

Sub-registers of Register RG_TRX_STATE.

Access parameters for sub-register TRX_CMD in register RG_TRX_STATE

#define SR_TRX_STATUS   0x141, 0x1F, 0

Sub-registers of Register RG_TRX_STATUS.

Access parameters for sub-register TRX_STATUS in register RG_TRX_STATUS

#define SR_TST_CTRL_DIG   0x176, 0x0F, 0

Sub-registers of Register RG_TST_CTRL_DIGI.

Access parameters for sub-register TST_CTRL_DIG in register RG_TST_CTRL_DIGI

#define SR_TST_STATUS   0x141, 0x20, 5

Access parameters for sub-register TST_STATUS in register RG_TRX_STATUS.

#define SR_TX_AUTO_CRC_ON   0x144, 0x20, 5

Sub-registers of Register RG_TRX_CTRL_1.

Access parameters for sub-register TX_AUTO_CRC_ON in register RG_TRX_CTRL_1

#define SR_TX_END   0x14F, 0x40, 6

Access parameters for sub-register TX_END in register RG_IRQ_STATUS.

#define SR_TX_END_EN   0x14E, 0x40, 6

Access parameters for sub-register TX_END_EN in register RG_IRQ_MASK.

#define SR_TX_PWR   0x145, 0x0F, 0

Sub-registers of Register RG_PHY_TX_PWR.

Access parameters for sub-register TX_PWR in register RG_PHY_TX_PWR

#define SR_XTAL_MODE   0x152, 0xF0, 4

Access parameters for sub-register XTAL_MODE in register RG_XOSC_CTRL.

#define SR_XTAL_TRIM   0x152, 0x0F, 0

Sub-registers of Register RG_XOSC_CTRL.

Access parameters for sub-register XTAL_TRIM in register RG_XOSC_CTRL

#define THRES_ANT_DIV_DISABLE   (0x7)

Constant THRES_ANT_DIV_DISABLE for sub-register SR_PDT_THRES in register RX_CTRL.

#define THRES_ANT_DIV_ENABLE   (0x3)

Constant THRES_ANT_DIV_ENABLE for sub-register SR_PDT_THRES in register RX_CTRL.

#define TRANSCEIVER_NAME   "ATMEGARFA1"
#define TRX_IRQ_DELAY_US   (9)
#define TRX_OFF_TO_PLL_ON_TIME_US   (110)
#define TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES   (35)
#define TRX_SUPPORTED_CHANNELS   (0x07FFF800)

Parameter definitions.

deactivate macros defined in iom header file Important parameters.

#define TX_AUTO_CRC_DISABLE   (0)

Constant TX_AUTO_CRC_DISABLE for sub-register SR_TX_AUTO_CRC_ON in register TRX_CTRL_1.

#define TX_AUTO_CRC_ENABLE   (1)

Constant TX_AUTO_CRC_ENABLE for sub-register SR_TX_AUTO_CRC_ON in register TRX_CTRL_1.

#define TX_PWR_TOLERANCE   (0x80)

typedef enum tal_trx_status_tag tal_trx_status_t

Enumerations.

Transceiver states

typedef enum trx_cmd_tag trx_cmd_t

sub-register TRX_CMD in register TRX_STATE

typedef enum trx_trac_status_tag trx_trac_status_t

sub-register TRAC_STATUS in register TRX_STATE

enum tal_trx_status_tag

Enumerations.

Transceiver states

Enumerator
P_ON 

Constant P_ON for sub-register SR_TRX_STATUS.

BUSY_RX 

Constant BUSY_RX for sub-register SR_TRX_STATUS.

BUSY_TX 

Constant BUSY_TX for sub-register SR_TRX_STATUS.

RX_ON 

Constant RX_ON for sub-register SR_TRX_STATUS.

TRX_OFF 

Constant TRX_OFF for sub-register SR_TRX_STATUS.

PLL_ON 

Constant PLL_ON for sub-register SR_TRX_STATUS.

TRX_SLEEP 

Constant TRX_SLEEP for sub-register SR_TRX_STATUS.

BUSY_RX_AACK 

Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS.

BUSY_TX_ARET 

Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS.

RX_AACK_ON 

Constant RX_AACK_ON for sub-register SR_TRX_STATUS.

TX_ARET_ON 

Constant TX_ARET_ON for sub-register SR_TRX_STATUS.

RX_ON_NOCLK 

Constant RX_ON_NOCLK for sub-register SR_TRX_STATUS.

RX_AACK_ON_NOCLK 

Constant RX_AACK_ON_NOCLK for sub-register SR_TRX_STATUS.

BUSY_RX_AACK_NOCLK 

Constant BUSY_RX_AACK_NOCLK for sub-register SR_TRX_STATUS.

STATE_TRANSITION_IN_PROGRESS 

Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS.

P_ON 

Constant P_ON for sub-register SR_TRX_STATUS.

BUSY_RX 

Constant BUSY_RX for sub-register SR_TRX_STATUS.

BUSY_TX 

Constant BUSY_TX for sub-register SR_TRX_STATUS.

RX_ON 

Constant RX_ON for sub-register SR_TRX_STATUS.

TRX_OFF 

Constant TRX_OFF for sub-register SR_TRX_STATUS.

PLL_ON 

Constant PLL_ON for sub-register SR_TRX_STATUS.

TRX_SLEEP 

Constant TRX_SLEEP for sub-register SR_TRX_STATUS.

BUSY_RX_AACK 

Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS.

BUSY_TX_ARET 

Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS.

RX_AACK_ON 

Constant RX_AACK_ON for sub-register SR_TRX_STATUS.

TX_ARET_ON 

Constant TX_ARET_ON for sub-register SR_TRX_STATUS.

RX_ON_NOCLK 

Constant RX_ON_NOCLK for sub-register SR_TRX_STATUS.

RX_AACK_ON_NOCLK 

Constant RX_AACK_ON_NOCLK for sub-register SR_TRX_STATUS.

BUSY_RX_AACK_NOCLK 

Constant BUSY_RX_AACK_NOCLK for sub-register SR_TRX_STATUS.

STATE_TRANSITION_IN_PROGRESS 

Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS.

P_ON 

Constant P_ON for sub-register SR_TRX_STATUS.

BUSY_RX 

Constant BUSY_RX for sub-register SR_TRX_STATUS.

BUSY_TX 

Constant BUSY_TX for sub-register SR_TRX_STATUS.

RX_ON 

Constant RX_ON for sub-register SR_TRX_STATUS.

TRX_OFF 

Constant TRX_OFF for sub-register SR_TRX_STATUS.

PLL_ON 

Constant PLL_ON for sub-register SR_TRX_STATUS.

TRX_SLEEP 

Constant SLEEP for sub-register SR_TRX_STATUS.

BUSY_RX_AACK 

Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS.

BUSY_TX_ARET 

Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS.

RX_AACK_ON 

Constant RX_AACK_ON for sub-register SR_TRX_STATUS.

TX_ARET_ON 

Constant TX_ARET_ON for sub-register SR_TRX_STATUS.

RX_ON_NOCLK 

Constant RX_ON_NOCLK for sub-register SR_TRX_STATUS.

RX_AACK_ON_NOCLK 

Constant RX_AACK_ON_NOCLK for sub-register SR_TRX_STATUS.

BUSY_RX_AACK_NOCLK 

Constant BUSY_RX_AACK_NOCLK for sub-register SR_TRX_STATUS.

STATE_TRANSITION_IN_PROGRESS 

Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS.

enum trx_cmd_tag

sub-register TRX_CMD in register TRX_STATE

Enumerator
CMD_NOP 

Constant CMD_NOP for sub-register SR_TRX_CMD.

CMD_TX_START 

Constant CMD_TX_START for sub-register SR_TRX_CMD.

CMD_FORCE_TRX_OFF 

Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD.

CMD_FORCE_PLL_ON 

Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD.

CMD_RX_ON 

Constant CMD_RX_ON for sub-register SR_TRX_CMD.

CMD_TRX_OFF 

Constant CMD_TRX_OFF for sub-register SR_TRX_CMD.

CMD_PLL_ON 

Constant CMD_PLL_ON for sub-register SR_TRX_CMD.

CMD_RX_AACK_ON 

Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD.

CMD_TX_ARET_ON 

Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD.

CMD_SLEEP 

Software implemented command.

CMD_NOP 

Constant CMD_NOP for sub-register SR_TRX_CMD.

CMD_TX_START 

Constant CMD_TX_START for sub-register SR_TRX_CMD.

CMD_FORCE_TRX_OFF 

Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD.

CMD_FORCE_PLL_ON 

Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD.

CMD_RX_ON 

Constant CMD_RX_ON for sub-register SR_TRX_CMD.

CMD_TRX_OFF 

Constant CMD_TRX_OFF for sub-register SR_TRX_CMD.

CMD_PLL_ON 

Constant CMD_PLL_ON for sub-register SR_TRX_CMD.

CMD_RX_AACK_ON 

Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD.

CMD_TX_ARET_ON 

Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD.

CMD_SLEEP 

Software implemented command.

CMD_NOP 

Constant CMD_NOP for sub-register SR_TRX_CMD.

CMD_TX_START 

Constant CMD_TX_START for sub-register SR_TRX_CMD.

CMD_FORCE_TRX_OFF 

Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD.

CMD_FORCE_PLL_ON 

Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD.

CMD_RX_ON 

Constant CMD_RX_ON for sub-register SR_TRX_CMD.

CMD_TRX_OFF 

Constant CMD_TRX_OFF for sub-register SR_TRX_CMD.

CMD_PLL_ON 

Constant CMD_PLL_ON for sub-register SR_TRX_CMD.

CMD_SLEEP 

Software implemented command.

CMD_RX_AACK_ON 

Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD.

CMD_TX_ARET_ON 

Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD.

enum trx_trac_status_tag

sub-register TRAC_STATUS in register TRX_STATE

Enumerator
TRAC_SUCCESS 

Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS_DATA_PENDING 

Constant TRAC_SUCCESS_DATA_PENDING for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS_WAIT_FOR_ACK 

Constant TRAC_SUCCESS_WAIT_FOR_ACK for sub-register SR_TRAC_STATUS.

TRAC_CHANNEL_ACCESS_FAILURE 

Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register SR_TRAC_STATUS.

TRAC_NO_ACK 

Constant TRAC_NO_ACK for sub-register SR_TRAC_STATUS.

TRAC_INVALID 

Constant TRAC_INVALID for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS 

Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS_DATA_PENDING 

Constant TRAC_SUCCESS_DATA_PENDING for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS_WAIT_FOR_ACK 

Constant TRAC_SUCCESS_WAIT_FOR_ACK for sub-register SR_TRAC_STATUS.

TRAC_CHANNEL_ACCESS_FAILURE 

Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register SR_TRAC_STATUS.

TRAC_NO_ACK 

Constant TRAC_NO_ACK for sub-register SR_TRAC_STATUS.

TRAC_INVALID 

Constant TRAC_INVALID for sub-register SR_TRAC_STATUS.

TRAC_SUCCESS 
TRAC_SUCCESS_DATA_PENDING 
TRAC_WAIT_FOR_ACK 
TRAC_CHANNEL_ACCESS_FAILURE 
TRAC_NO_ACK 
TRAC_INVALID 
Generated on Sat Mar 5 2022 01:06:21 for megaAVR by   doxygen 1.8.5