File contains register and command defines specific for RF215.
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
#include "tal_types.h"Macros | |
| #define | AFC0_AFEN0_MASK 0x01 |
| Sub-registers of Register AFC0. More... | |
| #define | AFC0_AFEN0_SHIFT 0 |
| Bit Offset for Sub-Register AFC0.AFEN0. More... | |
| #define | AFC0_AFEN1_MASK 0x02 |
| Bit Mask for Sub-Register AFC0.AFEN1. More... | |
| #define | AFC0_AFEN1_SHIFT 1 |
| Bit Offset for Sub-Register AFC0.AFEN1. More... | |
| #define | AFC0_AFEN2_MASK 0x04 |
| Bit Mask for Sub-Register AFC0.AFEN2. More... | |
| #define | AFC0_AFEN2_SHIFT 2 |
| Bit Offset for Sub-Register AFC0.AFEN2. More... | |
| #define | AFC0_AFEN3_MASK 0x08 |
| Bit Mask for Sub-Register AFC0.AFEN3. More... | |
| #define | AFC0_AFEN3_SHIFT 3 |
| Bit Offset for Sub-Register AFC0.AFEN3. More... | |
| #define | AFC0_PM_MASK 0x10 |
| Bit Mask for Sub-Register AFC0.PM. More... | |
| #define | AFC0_PM_SHIFT 4 |
| Bit Offset for Sub-Register AFC0.PM. More... | |
| #define | AFC1_MRFT0_MASK 0x10 |
| Bit Mask for Sub-Register AFC1.MRFT0. More... | |
| #define | AFC1_MRFT0_SHIFT 4 |
| Bit Offset for Sub-Register AFC1.MRFT0. More... | |
| #define | AFC1_MRFT1_MASK 0x20 |
| Bit Mask for Sub-Register AFC1.MRFT1. More... | |
| #define | AFC1_MRFT1_SHIFT 5 |
| Bit Offset for Sub-Register AFC1.MRFT1. More... | |
| #define | AFC1_MRFT2_MASK 0x40 |
| Bit Mask for Sub-Register AFC1.MRFT2. More... | |
| #define | AFC1_MRFT2_SHIFT 6 |
| Bit Offset for Sub-Register AFC1.MRFT2. More... | |
| #define | AFC1_MRFT3_MASK 0x80 |
| Bit Mask for Sub-Register AFC1.MRFT3. More... | |
| #define | AFC1_MRFT3_SHIFT 7 |
| Bit Offset for Sub-Register AFC1.MRFT3. More... | |
| #define | AFC1_PANC0_MASK 0x01 |
| Sub-registers of Register AFC1. More... | |
| #define | AFC1_PANC0_SHIFT 0 |
| Bit Offset for Sub-Register AFC1.PANC0. More... | |
| #define | AFC1_PANC1_MASK 0x02 |
| Bit Mask for Sub-Register AFC1.PANC1. More... | |
| #define | AFC1_PANC1_SHIFT 1 |
| Bit Offset for Sub-Register AFC1.PANC1. More... | |
| #define | AFC1_PANC2_MASK 0x04 |
| Bit Mask for Sub-Register AFC1.PANC2. More... | |
| #define | AFC1_PANC2_SHIFT 2 |
| Bit Offset for Sub-Register AFC1.PANC2. More... | |
| #define | AFC1_PANC3_MASK 0x08 |
| Bit Mask for Sub-Register AFC1.PANC3. More... | |
| #define | AFC1_PANC3_SHIFT 3 |
| Bit Offset for Sub-Register AFC1.PANC3. More... | |
| #define | AFFTM_AFFTM_MASK 0xFF |
| Sub-registers of Register AFFTM. More... | |
| #define | AFFTM_AFFTM_SHIFT 0 |
| Bit Offset for Sub-Register AFFTM.AFFTM. More... | |
| #define | AFFVM_AFFVM_MASK 0x0F |
| Sub-registers of Register AFFVM. More... | |
| #define | AFFVM_AFFVM_SHIFT 0 |
| Bit Offset for Sub-Register AFFVM.AFFVM. More... | |
| #define | AFS_AM0_MASK 0x01 |
| Sub-registers of Register AFS. More... | |
| #define | AFS_AM0_SHIFT 0 |
| Bit Offset for Sub-Register AFS.AM0. More... | |
| #define | AFS_AM1_MASK 0x02 |
| Bit Mask for Sub-Register AFS.AM1. More... | |
| #define | AFS_AM1_SHIFT 1 |
| Bit Offset for Sub-Register AFS.AM1. More... | |
| #define | AFS_AM2_MASK 0x04 |
| Bit Mask for Sub-Register AFS.AM2. More... | |
| #define | AFS_AM2_SHIFT 2 |
| Bit Offset for Sub-Register AFS.AM2. More... | |
| #define | AFS_AM3_MASK 0x08 |
| Bit Mask for Sub-Register AFS.AM3. More... | |
| #define | AFS_AM3_SHIFT 3 |
| Bit Offset for Sub-Register AFS.AM3. More... | |
| #define | AFS_EM_MASK 0x10 |
| Bit Mask for Sub-Register AFS.EM. More... | |
| #define | AFS_EM_SHIFT 4 |
| Bit Offset for Sub-Register AFS.EM. More... | |
| #define | AGCC_AGCI_MASK 0x40 |
| Bit Mask for Sub-Register AGCC.AGCI. More... | |
| #define | AGCC_AGCI_SHIFT 6 |
| Bit Offset for Sub-Register AGCC.AGCI. More... | |
| #define | AGCC_AVGS_MASK 0x30 |
| Bit Mask for Sub-Register AGCC.AVGS. More... | |
| #define | AGCC_AVGS_SHIFT 4 |
| Bit Offset for Sub-Register AGCC.AVGS. More... | |
| #define | AGCC_EN_MASK 0x01 |
| Sub-registers of Register AGCC. More... | |
| #define | AGCC_EN_SHIFT 0 |
| Bit Offset for Sub-Register AGCC.EN. More... | |
| #define | AGCC_FRZC_MASK 0x02 |
| Bit Mask for Sub-Register AGCC.FRZC. More... | |
| #define | AGCC_FRZC_SHIFT 1 |
| Bit Offset for Sub-Register AGCC.FRZC. More... | |
| #define | AGCC_FRZS_MASK 0x04 |
| Bit Mask for Sub-Register AGCC.FRZS. More... | |
| #define | AGCC_FRZS_SHIFT 2 |
| Bit Offset for Sub-Register AGCC.FRZS. More... | |
| #define | AGCC_RST_MASK 0x08 |
| Bit Mask for Sub-Register AGCC.RST. More... | |
| #define | AGCC_RST_SHIFT 3 |
| Bit Offset for Sub-Register AGCC.RST. More... | |
| #define | AGCS_GCW_MASK 0x1F |
| Sub-registers of Register AGCS. More... | |
| #define | AGCS_GCW_SHIFT 0 |
| Bit Offset for Sub-Register AGCS.GCW. More... | |
| #define | AGCS_TGT_MASK 0xE0 |
| Bit Mask for Sub-Register AGCS.TGT. More... | |
| #define | AGCS_TGT_SHIFT 5 |
| Bit Offset for Sub-Register AGCS.TGT. More... | |
| #define | AMAACKPD_PD0_MASK 0x01 |
| Sub-registers of Register AMAACKPD. More... | |
| #define | AMAACKPD_PD0_SHIFT 0 |
| Bit Offset for Sub-Register AMAACKPD.PD0. More... | |
| #define | AMAACKPD_PD1_MASK 0x02 |
| Bit Mask for Sub-Register AMAACKPD.PD1. More... | |
| #define | AMAACKPD_PD1_SHIFT 1 |
| Bit Offset for Sub-Register AMAACKPD.PD1. More... | |
| #define | AMAACKPD_PD2_MASK 0x04 |
| Bit Mask for Sub-Register AMAACKPD.PD2. More... | |
| #define | AMAACKPD_PD2_SHIFT 2 |
| Bit Offset for Sub-Register AMAACKPD.PD2. More... | |
| #define | AMAACKPD_PD3_MASK 0x08 |
| Bit Mask for Sub-Register AMAACKPD.PD3. More... | |
| #define | AMAACKPD_PD3_SHIFT 3 |
| Bit Offset for Sub-Register AMAACKPD.PD3. More... | |
| #define | AMAACKTH_AMAACKTH_MASK 0x07 |
| Sub-registers of Register AMAACKTH. More... | |
| #define | AMAACKTH_AMAACKTH_SHIFT 0 |
| Bit Offset for Sub-Register AMAACKTH.AMAACKTH. More... | |
| #define | AMAACKTL_AMAACKTL_MASK 0xFF |
| Sub-registers of Register AMAACKTL. More... | |
| #define | AMAACKTL_AMAACKTL_SHIFT 0 |
| Bit Offset for Sub-Register AMAACKTL.AMAACKTL. More... | |
| #define | AMCS_AACK_MASK 0x08 |
| Bit Mask for Sub-Register AMCS.AACK. More... | |
| #define | AMCS_AACK_SHIFT 3 |
| Bit Offset for Sub-Register AMCS.AACK. More... | |
| #define | AMCS_AACKDR_MASK 0x20 |
| Bit Mask for Sub-Register AMCS.AACKDR. More... | |
| #define | AMCS_AACKDR_SHIFT 5 |
| Bit Offset for Sub-Register AMCS.AACKDR. More... | |
| #define | AMCS_AACKFA_MASK 0x40 |
| Bit Mask for Sub-Register AMCS.AACKFA. More... | |
| #define | AMCS_AACKFA_SHIFT 6 |
| Bit Offset for Sub-Register AMCS.AACKFA. More... | |
| #define | AMCS_AACKFT_MASK 0x80 |
| Bit Mask for Sub-Register AMCS.AACKFT. More... | |
| #define | AMCS_AACKFT_SHIFT 7 |
| Bit Offset for Sub-Register AMCS.AACKFT. More... | |
| #define | AMCS_AACKS_MASK 0x10 |
| Bit Mask for Sub-Register AMCS.AACKS. More... | |
| #define | AMCS_AACKS_SHIFT 4 |
| Bit Offset for Sub-Register AMCS.AACKS. More... | |
| #define | AMCS_CCAED_MASK 0x04 |
| Bit Mask for Sub-Register AMCS.CCAED. More... | |
| #define | AMCS_CCAED_SHIFT 2 |
| Bit Offset for Sub-Register AMCS.CCAED. More... | |
| #define | AMCS_CCATX_MASK 0x02 |
| Bit Mask for Sub-Register AMCS.CCATX. More... | |
| #define | AMCS_CCATX_SHIFT 1 |
| Bit Offset for Sub-Register AMCS.CCATX. More... | |
| #define | AMCS_TX2RX_MASK 0x01 |
| Sub-registers of Register AMCS. More... | |
| #define | AMCS_TX2RX_SHIFT 0 |
| Bit Offset for Sub-Register AMCS.TX2RX. More... | |
| #define | AMEDT_AMEDT_MASK 0xFF |
| Sub-registers of Register AMEDT. More... | |
| #define | AMEDT_AMEDT_SHIFT 0 |
| Bit Offset for Sub-Register AMEDT.AMEDT. More... | |
| #define | AUXS_AGCMAP_MASK 0x60 |
| Bit Mask for Sub-Register AUXS.AGCMAP. More... | |
| #define | AUXS_AGCMAP_SHIFT 5 |
| Bit Offset for Sub-Register AUXS.AGCMAP. More... | |
| #define | AUXS_AVEN_MASK 0x08 |
| Bit Mask for Sub-Register AUXS.AVEN. More... | |
| #define | AUXS_AVEN_SHIFT 3 |
| Bit Offset for Sub-Register AUXS.AVEN. More... | |
| #define | AUXS_AVEXT_MASK 0x10 |
| Bit Mask for Sub-Register AUXS.AVEXT. More... | |
| #define | AUXS_AVEXT_SHIFT 4 |
| Bit Offset for Sub-Register AUXS.AVEXT. More... | |
| #define | AUXS_AVS_MASK 0x04 |
| Bit Mask for Sub-Register AUXS.AVS. More... | |
| #define | AUXS_AVS_SHIFT 2 |
| Bit Offset for Sub-Register AUXS.AVS. More... | |
| #define | AUXS_EXTLNABYP_MASK 0x80 |
| Bit Mask for Sub-Register AUXS.EXTLNABYP. More... | |
| #define | AUXS_EXTLNABYP_SHIFT 7 |
| Bit Offset for Sub-Register AUXS.EXTLNABYP. More... | |
| #define | AUXS_PAVC_MASK 0x03 |
| Sub-registers of Register AUXS. More... | |
| #define | AUXS_PAVC_SHIFT 0 |
| Bit Offset for Sub-Register AUXS.PAVC. More... | |
| #define | BASE_ADDR_BBC0_CORE0 (0x0300) |
| Base address for BBC0_CORE0 register set. More... | |
| #define | BASE_ADDR_BBC0_CORE0_IRQS (0x0002) |
| Base address for BBC0_CORE0_IRQS register set. More... | |
| #define | BASE_ADDR_BBC0_FB0 (0x2000) |
| Base address for BBC0_FB0 register set. More... | |
| #define | BASE_ADDR_BBC1_CORE1 (0x0400) |
| Base address for BBC1_CORE1 register set. More... | |
| #define | BASE_ADDR_BBC1_CORE1_IRQS (0x0003) |
| Base address for BBC1_CORE1_IRQS register set. More... | |
| #define | BASE_ADDR_BBC1_FB1 (0x3000) |
| Base address for BBC1_FB1 register set. More... | |
| #define | BASE_ADDR_RF09_RF09 (0x0100) |
| Base address for RF09_RF09 register set. More... | |
| #define | BASE_ADDR_RF09_RFIRQS09 (0x0000) |
| Register group base addresses. More... | |
| #define | BASE_ADDR_RF24_RF24 (0x0200) |
| Base address for RF24_RF24 register set. More... | |
| #define | BASE_ADDR_RF24_RFIRQS24 (0x0001) |
| Base address for RF24_RFIRQS24 register set. More... | |
| #define | BASE_ADDR_RF_RFCOMMON (0x0005) |
| Base address for RF_RFCOMMON register set. More... | |
| #define | BASE_ADDR_RFT09_RFT09 (0x0100) |
| Base address for RFT09_RFT09 register set. More... | |
| #define | BASE_ADDR_RFT24_RFT24 (0x0200) |
| Base address for RFT24_RFT24 register set. More... | |
| #define | BASE_ADDR_RFT_RFTESTCOMMON (0x0005) |
| Base address for RFT_RFTESTCOMMON register set. More... | |
| #define | BB_CH_BUSY (0x1) |
| Constant CH_BUSY for sub-register SR_CCAED in register BBC0_AMCS. More... | |
| #define | BB_CH_CLEAR (0x0) |
| Constant CH_CLEAR for sub-register SR_CCAED in register BBC0_AMCS. More... | |
| #define | BB_FCHIP100 (0x0) |
| Constant FCHIP100 for sub-register SR_FCHIP in register BBC0_OQPSKC0. More... | |
| #define | BB_FCHIP1000 (0x2) |
| Constant FCHIP1000 for sub-register SR_FCHIP in register BBC0_OQPSKC0. More... | |
| #define | BB_FCHIP200 (0x1) |
| Constant FCHIP200 for sub-register SR_FCHIP in register BBC0_OQPSKC0. More... | |
| #define | BB_FCHIP2000 (0x3) |
| Constant FCHIP2000 for sub-register SR_FCHIP in register BBC0_OQPSKC0. More... | |
| #define | BB_MRFSK (0x1) |
| Constant MRFSK for sub-register SR_PT in register BBC0_PC. More... | |
| #define | BB_MROFDM (0x2) |
| Constant MROFDM for sub-register SR_PT in register BBC0_PC. More... | |
| #define | BB_MROQPSK (0x3) |
| Constant MROQPSK for sub-register SR_PT in register BBC0_PC. More... | |
| #define | BB_PHYOFF (0x0) |
| Constant PHYOFF for sub-register SR_PT in register BBC0_PC. More... | |
| #define | BB_RC08 (0x0) |
| Constant RC08 for sub-register SR_MOD in register BBC0_OQPSKC0. More... | |
| #define | BB_RRC08 (0x1) |
| Constant RRC08 for sub-register SR_MOD in register BBC0_OQPSKC0. More... | |
| #define | BMDVC_BMHR_MASK 0x10 |
| Bit Mask for Sub-Register BMDVC.BMHR. More... | |
| #define | BMDVC_BMHR_SHIFT 4 |
| Bit Offset for Sub-Register BMDVC.BMHR. More... | |
| #define | BMDVC_BMS_MASK 0x20 |
| Bit Mask for Sub-Register BMDVC.BMS. More... | |
| #define | BMDVC_BMS_SHIFT 5 |
| Bit Offset for Sub-Register BMDVC.BMS. More... | |
| #define | BMDVC_BMVTH_MASK 0x0F |
| Sub-registers of Register BMDVC. More... | |
| #define | BMDVC_BMVTH_SHIFT 0 |
| Bit Offset for Sub-Register BMDVC.BMVTH. More... | |
| #define | CCF0H_CCF0H_MASK 0xFF |
| Sub-registers of Register CCF0H. More... | |
| #define | CCF0H_CCF0H_SHIFT 0 |
| Bit Offset for Sub-Register CCF0H.CCF0H. More... | |
| #define | CCF0L_CCF0L_MASK 0xFF |
| Sub-registers of Register CCF0L. More... | |
| #define | CCF0L_CCF0L_SHIFT 0 |
| Bit Offset for Sub-Register CCF0L.CCF0L. More... | |
| #define | CFG_DRV_MASK 0x03 |
| Sub-registers of Register CFG. More... | |
| #define | CFG_DRV_SHIFT 0 |
| Bit Offset for Sub-Register CFG.DRV. More... | |
| #define | CFG_IRQMM_MASK 0x08 |
| Bit Mask for Sub-Register CFG.IRQMM. More... | |
| #define | CFG_IRQMM_SHIFT 3 |
| Bit Offset for Sub-Register CFG.IRQMM. More... | |
| #define | CFG_IRQP_MASK 0x04 |
| Bit Mask for Sub-Register CFG.IRQP. More... | |
| #define | CFG_IRQP_SHIFT 2 |
| Bit Offset for Sub-Register CFG.IRQP. More... | |
| #define | CLKO_DRV_MASK 0x18 |
| Bit Mask for Sub-Register CLKO.DRV. More... | |
| #define | CLKO_DRV_SHIFT 3 |
| Bit Offset for Sub-Register CLKO.DRV. More... | |
| #define | CLKO_OS_MASK 0x07 |
| Sub-registers of Register CLKO. More... | |
| #define | CLKO_OS_SHIFT 0 |
| Bit Offset for Sub-Register CLKO.OS. More... | |
| #define | CMD_CMD_MASK 0x07 |
| Sub-registers of Register CMD. More... | |
| #define | CMD_CMD_SHIFT 0 |
| Bit Offset for Sub-Register CMD.CMD. More... | |
| #define | CNL_CNL_MASK 0xFF |
| Sub-registers of Register CNL. More... | |
| #define | CNL_CNL_SHIFT 0 |
| Bit Offset for Sub-Register CNL.CNL. More... | |
| #define | CNM_CM_MASK 0xC0 |
| Bit Mask for Sub-Register CNM.CM. More... | |
| #define | CNM_CM_SHIFT 6 |
| Bit Offset for Sub-Register CNM.CM. More... | |
| #define | CNM_CNH_MASK 0x01 |
| Sub-registers of Register CNM. More... | |
| #define | CNM_CNH_SHIFT 0 |
| Bit Offset for Sub-Register CNM.CNH. More... | |
| #define | CNT0_CNT0_MASK 0xFF |
| Sub-registers of Register CNT0. More... | |
| #define | CNT0_CNT0_SHIFT 0 |
| Bit Offset for Sub-Register CNT0.CNT0. More... | |
| #define | CNT1_CNT1_MASK 0xFF |
| Sub-registers of Register CNT1. More... | |
| #define | CNT1_CNT1_SHIFT 0 |
| Bit Offset for Sub-Register CNT1.CNT1. More... | |
| #define | CNT2_CNT2_MASK 0xFF |
| Sub-registers of Register CNT2. More... | |
| #define | CNT2_CNT2_SHIFT 0 |
| Bit Offset for Sub-Register CNT2.CNT2. More... | |
| #define | CNT3_CNT3_MASK 0xFF |
| Sub-registers of Register CNT3. More... | |
| #define | CNT3_CNT3_SHIFT 0 |
| Bit Offset for Sub-Register CNT3.CNT3. More... | |
| #define | CNTC_CAPRXS_MASK 0x08 |
| Bit Mask for Sub-Register CNTC.CAPRXS. More... | |
| #define | CNTC_CAPRXS_SHIFT 3 |
| Bit Offset for Sub-Register CNTC.CAPRXS. More... | |
| #define | CNTC_CAPTXS_MASK 0x10 |
| Bit Mask for Sub-Register CNTC.CAPTXS. More... | |
| #define | CNTC_CAPTXS_SHIFT 4 |
| Bit Offset for Sub-Register CNTC.CAPTXS. More... | |
| #define | CNTC_EN_MASK 0x01 |
| Sub-registers of Register CNTC. More... | |
| #define | CNTC_EN_SHIFT 0 |
| Bit Offset for Sub-Register CNTC.EN. More... | |
| #define | CNTC_RSTRXS_MASK 0x02 |
| Bit Mask for Sub-Register CNTC.RSTRXS. More... | |
| #define | CNTC_RSTRXS_SHIFT 1 |
| Bit Offset for Sub-Register CNTC.RSTRXS. More... | |
| #define | CNTC_RSTTXS_MASK 0x04 |
| Bit Mask for Sub-Register CNTC.RSTTXS. More... | |
| #define | CNTC_RSTTXS_SHIFT 2 |
| Bit Offset for Sub-Register CNTC.RSTTXS. More... | |
| #define | CS_CS_MASK 0xFF |
| Sub-registers of Register CS. More... | |
| #define | CS_CS_SHIFT 0 |
| Bit Offset for Sub-Register CS.CS. More... | |
| #define | EDC_EDM_MASK 0x03 |
| Sub-registers of Register EDC. More... | |
| #define | EDC_EDM_SHIFT 0 |
| Bit Offset for Sub-Register EDC.EDM. More... | |
| #define | EDD_DF_MASK 0xFC |
| Bit Mask for Sub-Register EDD.DF. More... | |
| #define | EDD_DF_SHIFT 2 |
| Bit Offset for Sub-Register EDD.DF. More... | |
| #define | EDD_DTB_MASK 0x03 |
| Sub-registers of Register EDD. More... | |
| #define | EDD_DTB_SHIFT 0 |
| Bit Offset for Sub-Register EDD.DTB. More... | |
| #define | EDV_EDV_MASK 0xFF |
| Sub-registers of Register EDV. More... | |
| #define | EDV_EDV_SHIFT 0 |
| Bit Offset for Sub-Register EDV.EDV. More... | |
| #define | FBLH_FBLH_MASK 0x07 |
| Sub-registers of Register FBLH. More... | |
| #define | FBLH_FBLH_SHIFT 0 |
| Bit Offset for Sub-Register FBLH.FBLH. More... | |
| #define | FBLIH_FBLIH_MASK 0x07 |
| Sub-registers of Register FBLIH. More... | |
| #define | FBLIH_FBLIH_SHIFT 0 |
| Bit Offset for Sub-Register FBLIH.FBLIH. More... | |
| #define | FBLIL_FBLIL_MASK 0xFF |
| Sub-registers of Register FBLIL. More... | |
| #define | FBLIL_FBLIL_SHIFT 0 |
| Bit Offset for Sub-Register FBLIL.FBLIL. More... | |
| #define | FBLL_FBLL_MASK 0xFF |
| Sub-registers of Register FBLL. More... | |
| #define | FBLL_FBLL_SHIFT 0 |
| Bit Offset for Sub-Register FBLL.FBLL. More... | |
| #define | FBRXE_FBRXE_MASK 0xFF |
| Sub-registers of Register FBRXE. More... | |
| #define | FBRXE_FBRXE_SHIFT 0 |
| Bit Offset for Sub-Register FBRXE.FBRXE. More... | |
| #define | FBRXS_FBRXS_MASK 0xFF |
| Sub-registers of Register FBRXS. More... | |
| #define | FBRXS_FBRXS_SHIFT 0 |
| Bit Offset for Sub-Register FBRXS.FBRXS. More... | |
| #define | FBTXE_FBTXE_MASK 0xFF |
| Sub-registers of Register FBTXE. More... | |
| #define | FBTXE_FBTXE_SHIFT 0 |
| Bit Offset for Sub-Register FBTXE.FBTXE. More... | |
| #define | FBTXS_FBTXS_MASK 0xFF |
| Sub-registers of Register FBTXS. More... | |
| #define | FBTXS_FBTXS_SHIFT 0 |
| Bit Offset for Sub-Register FBTXS.FBTXS. More... | |
| #define | FSKC0_BT_MASK 0xC0 |
| Bit Mask for Sub-Register FSKC0.BT. More... | |
| #define | FSKC0_BT_SHIFT 6 |
| Bit Offset for Sub-Register FSKC0.BT. More... | |
| #define | FSKC0_MIDX_MASK 0x0E |
| Bit Mask for Sub-Register FSKC0.MIDX. More... | |
| #define | FSKC0_MIDX_SHIFT 1 |
| Bit Offset for Sub-Register FSKC0.MIDX. More... | |
| #define | FSKC0_MIDXS_MASK 0x30 |
| Bit Mask for Sub-Register FSKC0.MIDXS. More... | |
| #define | FSKC0_MIDXS_SHIFT 4 |
| Bit Offset for Sub-Register FSKC0.MIDXS. More... | |
| #define | FSKC0_MORD_MASK 0x01 |
| Sub-registers of Register FSKC0. More... | |
| #define | FSKC0_MORD_SHIFT 0 |
| Bit Offset for Sub-Register FSKC0.MORD. More... | |
| #define | FSKC1_FI_MASK 0x20 |
| Bit Mask for Sub-Register FSKC1.FI. More... | |
| #define | FSKC1_FI_SHIFT 5 |
| Bit Offset for Sub-Register FSKC1.FI. More... | |
| #define | FSKC1_FSKPLH_MASK 0xC0 |
| Bit Mask for Sub-Register FSKC1.FSKPLH. More... | |
| #define | FSKC1_FSKPLH_SHIFT 6 |
| Bit Offset for Sub-Register FSKC1.FSKPLH. More... | |
| #define | FSKC1_SRATE_MASK 0x0F |
| Sub-registers of Register FSKC1. More... | |
| #define | FSKC1_SRATE_SHIFT 0 |
| Bit Offset for Sub-Register FSKC1.SRATE. More... | |
| #define | FSKC2_FECIE_MASK 0x01 |
| Sub-registers of Register FSKC2. More... | |
| #define | FSKC2_FECIE_SHIFT 0 |
| Bit Offset for Sub-Register FSKC2.FECIE. More... | |
| #define | FSKC2_FECS_MASK 0x02 |
| Bit Mask for Sub-Register FSKC2.FECS. More... | |
| #define | FSKC2_FECS_SHIFT 1 |
| Bit Offset for Sub-Register FSKC2.FECS. More... | |
| #define | FSKC2_MSE_MASK 0x08 |
| Bit Mask for Sub-Register FSKC2.MSE. More... | |
| #define | FSKC2_MSE_SHIFT 3 |
| Bit Offset for Sub-Register FSKC2.MSE. More... | |
| #define | FSKC2_PDTM_MASK 0x80 |
| Bit Mask for Sub-Register FSKC2.PDTM. More... | |
| #define | FSKC2_PDTM_SHIFT 7 |
| Bit Offset for Sub-Register FSKC2.PDTM. More... | |
| #define | FSKC2_PRI_MASK 0x04 |
| Bit Mask for Sub-Register FSKC2.PRI. More... | |
| #define | FSKC2_PRI_SHIFT 2 |
| Bit Offset for Sub-Register FSKC2.PRI. More... | |
| #define | FSKC2_RXO_MASK 0x60 |
| Bit Mask for Sub-Register FSKC2.RXO. More... | |
| #define | FSKC2_RXO_SHIFT 5 |
| Bit Offset for Sub-Register FSKC2.RXO. More... | |
| #define | FSKC2_RXPTO_MASK 0x10 |
| Bit Mask for Sub-Register FSKC2.RXPTO. More... | |
| #define | FSKC2_RXPTO_SHIFT 4 |
| Bit Offset for Sub-Register FSKC2.RXPTO. More... | |
| #define | FSKC3_PDT_MASK 0x0F |
| Sub-registers of Register FSKC3. More... | |
| #define | FSKC3_PDT_SHIFT 0 |
| Bit Offset for Sub-Register FSKC3.PDT. More... | |
| #define | FSKC3_SFDT_MASK 0xF0 |
| Bit Mask for Sub-Register FSKC3.SFDT. More... | |
| #define | FSKC3_SFDT_SHIFT 4 |
| Bit Offset for Sub-Register FSKC3.SFDT. More... | |
| #define | FSKC4_CSFD0_MASK 0x03 |
| Sub-registers of Register FSKC4. More... | |
| #define | FSKC4_CSFD0_SHIFT 0 |
| Bit Offset for Sub-Register FSKC4.CSFD0. More... | |
| #define | FSKC4_CSFD1_MASK 0x0C |
| Bit Mask for Sub-Register FSKC4.CSFD1. More... | |
| #define | FSKC4_CSFD1_SHIFT 2 |
| Bit Offset for Sub-Register FSKC4.CSFD1. More... | |
| #define | FSKC4_RAWRBIT_MASK 0x10 |
| Bit Mask for Sub-Register FSKC4.RAWRBIT. More... | |
| #define | FSKC4_RAWRBIT_SHIFT 4 |
| Bit Offset for Sub-Register FSKC4.RAWRBIT. More... | |
| #define | FSKC4_SFD32_MASK 0x20 |
| Bit Mask for Sub-Register FSKC4.SFD32. More... | |
| #define | FSKC4_SFD32_SHIFT 5 |
| Bit Offset for Sub-Register FSKC4.SFD32. More... | |
| #define | FSKC4_SFDQ_MASK 0x40 |
| Bit Mask for Sub-Register FSKC4.SFDQ. More... | |
| #define | FSKC4_SFDQ_SHIFT 6 |
| Bit Offset for Sub-Register FSKC4.SFDQ. More... | |
| #define | FSKDM_EN_MASK 0x01 |
| Sub-registers of Register FSKDM. More... | |
| #define | FSKDM_EN_SHIFT 0 |
| Bit Offset for Sub-Register FSKDM.EN. More... | |
| #define | FSKDM_PE_MASK 0x02 |
| Bit Mask for Sub-Register FSKDM.PE. More... | |
| #define | FSKDM_PE_SHIFT 1 |
| Bit Offset for Sub-Register FSKDM.PE. More... | |
| #define | FSKPE0_FSKPE0_MASK 0xFF |
| Sub-registers of Register FSKPE0. More... | |
| #define | FSKPE0_FSKPE0_SHIFT 0 |
| Bit Offset for Sub-Register FSKPE0.FSKPE0. More... | |
| #define | FSKPE1_FSKPE1_MASK 0xFF |
| Sub-registers of Register FSKPE1. More... | |
| #define | FSKPE1_FSKPE1_SHIFT 0 |
| Bit Offset for Sub-Register FSKPE1.FSKPE1. More... | |
| #define | FSKPE2_FSKPE2_MASK 0xFF |
| Sub-registers of Register FSKPE2. More... | |
| #define | FSKPE2_FSKPE2_SHIFT 0 |
| Bit Offset for Sub-Register FSKPE2.FSKPE2. More... | |
| #define | FSKPHRRX_DW_MASK 0x04 |
| Bit Mask for Sub-Register FSKPHRRX.DW. More... | |
| #define | FSKPHRRX_DW_SHIFT 2 |
| Bit Offset for Sub-Register FSKPHRRX.DW. More... | |
| #define | FSKPHRRX_FCST_MASK 0x80 |
| Bit Mask for Sub-Register FSKPHRRX.FCST. More... | |
| #define | FSKPHRRX_FCST_SHIFT 7 |
| Bit Offset for Sub-Register FSKPHRRX.FCST. More... | |
| #define | FSKPHRRX_MS_MASK 0x40 |
| Bit Mask for Sub-Register FSKPHRRX.MS. More... | |
| #define | FSKPHRRX_MS_SHIFT 6 |
| Bit Offset for Sub-Register FSKPHRRX.MS. More... | |
| #define | FSKPHRRX_RB1_MASK 0x01 |
| Sub-registers of Register FSKPHRRX. More... | |
| #define | FSKPHRRX_RB1_SHIFT 0 |
| Bit Offset for Sub-Register FSKPHRRX.RB1. More... | |
| #define | FSKPHRRX_RB2_MASK 0x02 |
| Bit Mask for Sub-Register FSKPHRRX.RB2. More... | |
| #define | FSKPHRRX_RB2_SHIFT 1 |
| Bit Offset for Sub-Register FSKPHRRX.RB2. More... | |
| #define | FSKPHRRX_SFD_MASK 0x08 |
| Bit Mask for Sub-Register FSKPHRRX.SFD. More... | |
| #define | FSKPHRRX_SFD_SHIFT 3 |
| Bit Offset for Sub-Register FSKPHRRX.SFD. More... | |
| #define | FSKPHRTX_DW_MASK 0x04 |
| Bit Mask for Sub-Register FSKPHRTX.DW. More... | |
| #define | FSKPHRTX_DW_SHIFT 2 |
| Bit Offset for Sub-Register FSKPHRTX.DW. More... | |
| #define | FSKPHRTX_RB1_MASK 0x01 |
| Sub-registers of Register FSKPHRTX. More... | |
| #define | FSKPHRTX_RB1_SHIFT 0 |
| Bit Offset for Sub-Register FSKPHRTX.RB1. More... | |
| #define | FSKPHRTX_RB2_MASK 0x02 |
| Bit Mask for Sub-Register FSKPHRTX.RB2. More... | |
| #define | FSKPHRTX_RB2_SHIFT 1 |
| Bit Offset for Sub-Register FSKPHRTX.RB2. More... | |
| #define | FSKPHRTX_SFD_MASK 0x08 |
| Bit Mask for Sub-Register FSKPHRTX.SFD. More... | |
| #define | FSKPHRTX_SFD_SHIFT 3 |
| Bit Offset for Sub-Register FSKPHRTX.SFD. More... | |
| #define | FSKPLL_FSKPLL_MASK 0xFF |
| Sub-registers of Register FSKPLL. More... | |
| #define | FSKPLL_FSKPLL_SHIFT 0 |
| Bit Offset for Sub-Register FSKPLL.FSKPLL. More... | |
| #define | FSKRPC_BASET_MASK 0x07 |
| Sub-registers of Register FSKRPC. More... | |
| #define | FSKRPC_BASET_SHIFT 0 |
| Bit Offset for Sub-Register FSKRPC.BASET. More... | |
| #define | FSKRPC_EN_MASK 0x08 |
| Bit Mask for Sub-Register FSKRPC.EN. More... | |
| #define | FSKRPC_EN_SHIFT 3 |
| Bit Offset for Sub-Register FSKRPC.EN. More... | |
| #define | FSKRPCOFFT_FSKRPCOFFT_MASK 0xFF |
| Sub-registers of Register FSKRPCOFFT. More... | |
| #define | FSKRPCOFFT_FSKRPCOFFT_SHIFT 0 |
| Bit Offset for Sub-Register FSKRPCOFFT.FSKRPCOFFT. More... | |
| #define | FSKRPCONT_FSKRPCONT_MASK 0xFF |
| Sub-registers of Register FSKRPCONT. More... | |
| #define | FSKRPCONT_FSKRPCONT_SHIFT 0 |
| Bit Offset for Sub-Register FSKRPCONT.FSKRPCONT. More... | |
| #define | FSKRRXFLH_FSKRRXFLH_MASK 0x07 |
| Sub-registers of Register FSKRRXFLH. More... | |
| #define | FSKRRXFLH_FSKRRXFLH_SHIFT 0 |
| Bit Offset for Sub-Register FSKRRXFLH.FSKRRXFLH. More... | |
| #define | FSKRRXFLL_FSKRRXFLL_MASK 0xFF |
| Sub-registers of Register FSKRRXFLL. More... | |
| #define | FSKRRXFLL_FSKRRXFLL_SHIFT 0 |
| Bit Offset for Sub-Register FSKRRXFLL.FSKRRXFLL. More... | |
| #define | FSKSFD0H_FSKSFD0H_MASK 0xFF |
| Sub-registers of Register FSKSFD0H. More... | |
| #define | FSKSFD0H_FSKSFD0H_SHIFT 0 |
| Bit Offset for Sub-Register FSKSFD0H.FSKSFD0H. More... | |
| #define | FSKSFD0L_FSKSFD0L_MASK 0xFF |
| Sub-registers of Register FSKSFD0L. More... | |
| #define | FSKSFD0L_FSKSFD0L_SHIFT 0 |
| Bit Offset for Sub-Register FSKSFD0L.FSKSFD0L. More... | |
| #define | FSKSFD1H_FSKSFD1H_MASK 0xFF |
| Sub-registers of Register FSKSFD1H. More... | |
| #define | FSKSFD1H_FSKSFD1H_SHIFT 0 |
| Bit Offset for Sub-Register FSKSFD1H.FSKSFD1H. More... | |
| #define | FSKSFD1L_FSKSFD1L_MASK 0xFF |
| Sub-registers of Register FSKSFD1L. More... | |
| #define | FSKSFD1L_FSKSFD1L_SHIFT 0 |
| Bit Offset for Sub-Register FSKSFD1L.FSKSFD1L. More... | |
| #define | IQIFC0_CMV1V2_MASK 0x02 |
| Bit Mask for Sub-Register IQIFC0.CMV1V2. More... | |
| #define | IQIFC0_CMV1V2_SHIFT 1 |
| Bit Offset for Sub-Register IQIFC0.CMV1V2. More... | |
| #define | IQIFC0_CMV_MASK 0x0C |
| Bit Mask for Sub-Register IQIFC0.CMV. More... | |
| #define | IQIFC0_CMV_SHIFT 2 |
| Bit Offset for Sub-Register IQIFC0.CMV. More... | |
| #define | IQIFC0_DRV_MASK 0x30 |
| Bit Mask for Sub-Register IQIFC0.DRV. More... | |
| #define | IQIFC0_DRV_SHIFT 4 |
| Bit Offset for Sub-Register IQIFC0.DRV. More... | |
| #define | IQIFC0_EEC_MASK 0x01 |
| Sub-registers of Register IQIFC0. More... | |
| #define | IQIFC0_EEC_SHIFT 0 |
| Bit Offset for Sub-Register IQIFC0.EEC. More... | |
| #define | IQIFC0_EXTLB_MASK 0x80 |
| Bit Mask for Sub-Register IQIFC0.EXTLB. More... | |
| #define | IQIFC0_EXTLB_SHIFT 7 |
| Bit Offset for Sub-Register IQIFC0.EXTLB. More... | |
| #define | IQIFC0_SF_MASK 0x40 |
| Bit Mask for Sub-Register IQIFC0.SF. More... | |
| #define | IQIFC0_SF_SHIFT 6 |
| Bit Offset for Sub-Register IQIFC0.SF. More... | |
| #define | IQIFC1_CHPM_MASK 0x70 |
| Bit Mask for Sub-Register IQIFC1.CHPM. More... | |
| #define | IQIFC1_CHPM_SHIFT 4 |
| Bit Offset for Sub-Register IQIFC1.CHPM. More... | |
| #define | IQIFC1_FAILSF_MASK 0x80 |
| Bit Mask for Sub-Register IQIFC1.FAILSF. More... | |
| #define | IQIFC1_FAILSF_SHIFT 7 |
| Bit Offset for Sub-Register IQIFC1.FAILSF. More... | |
| #define | IQIFC1_SKEWDRV_MASK 0x03 |
| Sub-registers of Register IQIFC1. More... | |
| #define | IQIFC1_SKEWDRV_SHIFT 0 |
| Bit Offset for Sub-Register IQIFC1.SKEWDRV. More... | |
| #define | IQIFC2_SYNC_MASK 0x80 |
| Sub-registers of Register IQIFC2. More... | |
| #define | IQIFC2_SYNC_SHIFT 7 |
| Bit Offset for Sub-Register IQIFC2.SYNC. More... | |
| #define | IRQM_AGCH_MASK 0x20 |
| Bit Mask for Sub-Register IRQM.AGCH. More... | |
| #define | IRQM_AGCH_SHIFT 5 |
| Bit Offset for Sub-Register IRQM.AGCH. More... | |
| #define | IRQM_AGCR_MASK 0x40 |
| Bit Mask for Sub-Register IRQM.AGCR. More... | |
| #define | IRQM_AGCR_SHIFT 6 |
| Bit Offset for Sub-Register IRQM.AGCR. More... | |
| #define | IRQM_BATLOW_MASK 0x08 |
| Bit Mask for Sub-Register IRQM.BATLOW. More... | |
| #define | IRQM_BATLOW_SHIFT 3 |
| Bit Offset for Sub-Register IRQM.BATLOW. More... | |
| #define | IRQM_EDC_MASK 0x04 |
| Bit Mask for Sub-Register IRQM.EDC. More... | |
| #define | IRQM_EDC_SHIFT 2 |
| Bit Offset for Sub-Register IRQM.EDC. More... | |
| #define | IRQM_FBLI_MASK 0x80 |
| Bit Mask for Sub-Register IRQM.FBLI. More... | |
| #define | IRQM_FBLI_SHIFT 7 |
| Bit Offset for Sub-Register IRQM.FBLI. More... | |
| #define | IRQM_IQIFSF_MASK 0x20 |
| Bit Mask for Sub-Register IRQM.IQIFSF. More... | |
| #define | IRQM_IQIFSF_SHIFT 5 |
| Bit Offset for Sub-Register IRQM.IQIFSF. More... | |
| #define | IRQM_RXAM_MASK 0x04 |
| Bit Mask for Sub-Register IRQM.RXAM. More... | |
| #define | IRQM_RXAM_SHIFT 2 |
| Bit Offset for Sub-Register IRQM.RXAM. More... | |
| #define | IRQM_RXEM_MASK 0x08 |
| Bit Mask for Sub-Register IRQM.RXEM. More... | |
| #define | IRQM_RXEM_SHIFT 3 |
| Bit Offset for Sub-Register IRQM.RXEM. More... | |
| #define | IRQM_RXFE_MASK 0x02 |
| Bit Mask for Sub-Register IRQM.RXFE. More... | |
| #define | IRQM_RXFE_SHIFT 1 |
| Bit Offset for Sub-Register IRQM.RXFE. More... | |
| #define | IRQM_RXFS_MASK 0x01 |
| Sub-registers of Register IRQM. More... | |
| #define | IRQM_RXFS_SHIFT 0 |
| Bit Offset for Sub-Register IRQM.RXFS. More... | |
| #define | IRQM_TRXERR_MASK 0x10 |
| Bit Mask for Sub-Register IRQM.TRXERR. More... | |
| #define | IRQM_TRXERR_SHIFT 4 |
| Bit Offset for Sub-Register IRQM.TRXERR. More... | |
| #define | IRQM_TRXRDY_MASK 0x02 |
| Bit Mask for Sub-Register IRQM.TRXRDY. More... | |
| #define | IRQM_TRXRDY_SHIFT 1 |
| Bit Offset for Sub-Register IRQM.TRXRDY. More... | |
| #define | IRQM_TXFE_MASK 0x10 |
| Bit Mask for Sub-Register IRQM.TXFE. More... | |
| #define | IRQM_TXFE_SHIFT 4 |
| Bit Offset for Sub-Register IRQM.TXFE. More... | |
| #define | IRQM_WAKEUP_MASK 0x01 |
| Sub-registers of Register IRQM. More... | |
| #define | IRQM_WAKEUP_SHIFT 0 |
| Bit Offset for Sub-Register IRQM.WAKEUP. More... | |
| #define | IRQS_AGCH_MASK 0x20 |
| Bit Mask for Sub-Register IRQS.AGCH. More... | |
| #define | IRQS_AGCH_SHIFT 5 |
| Bit Offset for Sub-Register IRQS.AGCH. More... | |
| #define | IRQS_AGCR_MASK 0x40 |
| Bit Mask for Sub-Register IRQS.AGCR. More... | |
| #define | IRQS_AGCR_SHIFT 6 |
| Bit Offset for Sub-Register IRQS.AGCR. More... | |
| #define | IRQS_BATLOW_MASK 0x08 |
| Bit Mask for Sub-Register IRQS.BATLOW. More... | |
| #define | IRQS_BATLOW_SHIFT 3 |
| Bit Offset for Sub-Register IRQS.BATLOW. More... | |
| #define | IRQS_EDC_MASK 0x04 |
| Bit Mask for Sub-Register IRQS.EDC. More... | |
| #define | IRQS_EDC_SHIFT 2 |
| Bit Offset for Sub-Register IRQS.EDC. More... | |
| #define | IRQS_FBLI_MASK 0x80 |
| Bit Mask for Sub-Register IRQS.FBLI. More... | |
| #define | IRQS_FBLI_SHIFT 7 |
| Bit Offset for Sub-Register IRQS.FBLI. More... | |
| #define | IRQS_IQIFSF_MASK 0x20 |
| Bit Mask for Sub-Register IRQS.IQIFSF. More... | |
| #define | IRQS_IQIFSF_SHIFT 5 |
| Bit Offset for Sub-Register IRQS.IQIFSF. More... | |
| #define | IRQS_RXAM_MASK 0x04 |
| Bit Mask for Sub-Register IRQS.RXAM. More... | |
| #define | IRQS_RXAM_SHIFT 2 |
| Bit Offset for Sub-Register IRQS.RXAM. More... | |
| #define | IRQS_RXEM_MASK 0x08 |
| Bit Mask for Sub-Register IRQS.RXEM. More... | |
| #define | IRQS_RXEM_SHIFT 3 |
| Bit Offset for Sub-Register IRQS.RXEM. More... | |
| #define | IRQS_RXFE_MASK 0x02 |
| Bit Mask for Sub-Register IRQS.RXFE. More... | |
| #define | IRQS_RXFE_SHIFT 1 |
| Bit Offset for Sub-Register IRQS.RXFE. More... | |
| #define | IRQS_RXFS_MASK 0x01 |
| Sub-registers of Register IRQS. More... | |
| #define | IRQS_RXFS_SHIFT 0 |
| Bit Offset for Sub-Register IRQS.RXFS. More... | |
| #define | IRQS_TRXERR_MASK 0x10 |
| Bit Mask for Sub-Register IRQS.TRXERR. More... | |
| #define | IRQS_TRXERR_SHIFT 4 |
| Bit Offset for Sub-Register IRQS.TRXERR. More... | |
| #define | IRQS_TRXRDY_MASK 0x02 |
| Bit Mask for Sub-Register IRQS.TRXRDY. More... | |
| #define | IRQS_TRXRDY_SHIFT 1 |
| Bit Offset for Sub-Register IRQS.TRXRDY. More... | |
| #define | IRQS_TXFE_MASK 0x10 |
| Bit Mask for Sub-Register IRQS.TXFE. More... | |
| #define | IRQS_TXFE_SHIFT 4 |
| Bit Offset for Sub-Register IRQS.TXFE. More... | |
| #define | IRQS_WAKEUP_MASK 0x01 |
| Subregister Type Definitions (MASK, SHIFT) More... | |
| #define | IRQS_WAKEUP_SHIFT 0 |
| Bit Offset for Sub-Register IRQS.WAKEUP. More... | |
| #define | MACEA0_MACEA0_MASK 0xFF |
| Sub-registers of Register MACEA0. More... | |
| #define | MACEA0_MACEA0_SHIFT 0 |
| Bit Offset for Sub-Register MACEA0.MACEA0. More... | |
| #define | MACEA1_MACEA1_MASK 0xFF |
| Sub-registers of Register MACEA1. More... | |
| #define | MACEA1_MACEA1_SHIFT 0 |
| Bit Offset for Sub-Register MACEA1.MACEA1. More... | |
| #define | MACEA2_MACEA2_MASK 0xFF |
| Sub-registers of Register MACEA2. More... | |
| #define | MACEA2_MACEA2_SHIFT 0 |
| Bit Offset for Sub-Register MACEA2.MACEA2. More... | |
| #define | MACEA3_MACEA3_MASK 0xFF |
| Sub-registers of Register MACEA3. More... | |
| #define | MACEA3_MACEA3_SHIFT 0 |
| Bit Offset for Sub-Register MACEA3.MACEA3. More... | |
| #define | MACEA4_MACEA4_MASK 0xFF |
| Sub-registers of Register MACEA4. More... | |
| #define | MACEA4_MACEA4_SHIFT 0 |
| Bit Offset for Sub-Register MACEA4.MACEA4. More... | |
| #define | MACEA5_MACEA5_MASK 0xFF |
| Sub-registers of Register MACEA5. More... | |
| #define | MACEA5_MACEA5_SHIFT 0 |
| Bit Offset for Sub-Register MACEA5.MACEA5. More... | |
| #define | MACEA6_MACEA6_MASK 0xFF |
| Sub-registers of Register MACEA6. More... | |
| #define | MACEA6_MACEA6_SHIFT 0 |
| Bit Offset for Sub-Register MACEA6.MACEA6. More... | |
| #define | MACEA7_MACEA7_MASK 0xFF |
| Sub-registers of Register MACEA7. More... | |
| #define | MACEA7_MACEA7_SHIFT 0 |
| Bit Offset for Sub-Register MACEA7.MACEA7. More... | |
| #define | MACPID0F0_MACPID0F0_MASK 0xFF |
| Sub-registers of Register MACPID0F0. More... | |
| #define | MACPID0F0_MACPID0F0_SHIFT 0 |
| Bit Offset for Sub-Register MACPID0F0.MACPID0F0. More... | |
| #define | MACPID0F1_MACPID0F1_MASK 0xFF |
| Sub-registers of Register MACPID0F1. More... | |
| #define | MACPID0F1_MACPID0F1_SHIFT 0 |
| Bit Offset for Sub-Register MACPID0F1.MACPID0F1. More... | |
| #define | MACPID0F2_MACPID0F2_MASK 0xFF |
| Sub-registers of Register MACPID0F2. More... | |
| #define | MACPID0F2_MACPID0F2_SHIFT 0 |
| Bit Offset for Sub-Register MACPID0F2.MACPID0F2. More... | |
| #define | MACPID0F3_MACPID0F3_MASK 0xFF |
| Sub-registers of Register MACPID0F3. More... | |
| #define | MACPID0F3_MACPID0F3_SHIFT 0 |
| Bit Offset for Sub-Register MACPID0F3.MACPID0F3. More... | |
| #define | MACPID1F0_MACPID1F0_MASK 0xFF |
| Sub-registers of Register MACPID1F0. More... | |
| #define | MACPID1F0_MACPID1F0_SHIFT 0 |
| Bit Offset for Sub-Register MACPID1F0.MACPID1F0. More... | |
| #define | MACPID1F1_MACPID1F1_MASK 0xFF |
| Sub-registers of Register MACPID1F1. More... | |
| #define | MACPID1F1_MACPID1F1_SHIFT 0 |
| Bit Offset for Sub-Register MACPID1F1.MACPID1F1. More... | |
| #define | MACPID1F2_MACPID1F2_MASK 0xFF |
| Sub-registers of Register MACPID1F2. More... | |
| #define | MACPID1F2_MACPID1F2_SHIFT 0 |
| Bit Offset for Sub-Register MACPID1F2.MACPID1F2. More... | |
| #define | MACPID1F3_MACPID1F3_MASK 0xFF |
| Sub-registers of Register MACPID1F3. More... | |
| #define | MACPID1F3_MACPID1F3_SHIFT 0 |
| Bit Offset for Sub-Register MACPID1F3.MACPID1F3. More... | |
| #define | MACSHA0F0_MACSHA0F0_MASK 0xFF |
| Sub-registers of Register MACSHA0F0. More... | |
| #define | MACSHA0F0_MACSHA0F0_SHIFT 0 |
| Bit Offset for Sub-Register MACSHA0F0.MACSHA0F0. More... | |
| #define | MACSHA0F1_MACSHA0F1_MASK 0xFF |
| Sub-registers of Register MACSHA0F1. More... | |
| #define | MACSHA0F1_MACSHA0F1_SHIFT 0 |
| Bit Offset for Sub-Register MACSHA0F1.MACSHA0F1. More... | |
| #define | MACSHA0F2_MACSHA0F2_MASK 0xFF |
| Sub-registers of Register MACSHA0F2. More... | |
| #define | MACSHA0F2_MACSHA0F2_SHIFT 0 |
| Bit Offset for Sub-Register MACSHA0F2.MACSHA0F2. More... | |
| #define | MACSHA0F3_MACSHA0F3_MASK 0xFF |
| Sub-registers of Register MACSHA0F3. More... | |
| #define | MACSHA0F3_MACSHA0F3_SHIFT 0 |
| Bit Offset for Sub-Register MACSHA0F3.MACSHA0F3. More... | |
| #define | MACSHA1F0_MACSHA1F0_MASK 0xFF |
| Sub-registers of Register MACSHA1F0. More... | |
| #define | MACSHA1F0_MACSHA1F0_SHIFT 0 |
| Bit Offset for Sub-Register MACSHA1F0.MACSHA1F0. More... | |
| #define | MACSHA1F1_MACSHA1F1_MASK 0xFF |
| Sub-registers of Register MACSHA1F1. More... | |
| #define | MACSHA1F1_MACSHA1F1_SHIFT 0 |
| Bit Offset for Sub-Register MACSHA1F1.MACSHA1F1. More... | |
| #define | MACSHA1F2_MACSHA1F2_MASK 0xFF |
| Sub-registers of Register MACSHA1F2. More... | |
| #define | MACSHA1F2_MACSHA1F2_SHIFT 0 |
| Bit Offset for Sub-Register MACSHA1F2.MACSHA1F2. More... | |
| #define | MACSHA1F3_MACSHA1F3_MASK 0xFF |
| Sub-registers of Register MACSHA1F3. More... | |
| #define | MACSHA1F3_MACSHA1F3_SHIFT 0 |
| Bit Offset for Sub-Register MACSHA1F3.MACSHA1F3. More... | |
| #define | OFDMC_LFO_MASK 0x08 |
| Bit Mask for Sub-Register OFDMC.LFO. More... | |
| #define | OFDMC_LFO_SHIFT 3 |
| Bit Offset for Sub-Register OFDMC.LFO. More... | |
| #define | OFDMC_OPT_MASK 0x03 |
| Sub-registers of Register OFDMC. More... | |
| #define | OFDMC_OPT_SHIFT 0 |
| Bit Offset for Sub-Register OFDMC.OPT. More... | |
| #define | OFDMC_POI_MASK 0x04 |
| Bit Mask for Sub-Register OFDMC.POI. More... | |
| #define | OFDMC_POI_SHIFT 2 |
| Bit Offset for Sub-Register OFDMC.POI. More... | |
| #define | OFDMC_SSRX_MASK 0xC0 |
| Bit Mask for Sub-Register OFDMC.SSRX. More... | |
| #define | OFDMC_SSRX_SHIFT 6 |
| Bit Offset for Sub-Register OFDMC.SSRX. More... | |
| #define | OFDMC_SSTX_MASK 0x30 |
| Bit Mask for Sub-Register OFDMC.SSTX. More... | |
| #define | OFDMC_SSTX_SHIFT 4 |
| Bit Offset for Sub-Register OFDMC.SSTX. More... | |
| #define | OFDMPHRRX_MCS_MASK 0x07 |
| Sub-registers of Register OFDMPHRRX. More... | |
| #define | OFDMPHRRX_MCS_SHIFT 0 |
| Bit Offset for Sub-Register OFDMPHRRX.MCS. More... | |
| #define | OFDMPHRRX_RB17_MASK 0x20 |
| Bit Mask for Sub-Register OFDMPHRRX.RB17. More... | |
| #define | OFDMPHRRX_RB17_SHIFT 5 |
| Bit Offset for Sub-Register OFDMPHRRX.RB17. More... | |
| #define | OFDMPHRRX_RB18_MASK 0x40 |
| Bit Mask for Sub-Register OFDMPHRRX.RB18. More... | |
| #define | OFDMPHRRX_RB18_SHIFT 6 |
| Bit Offset for Sub-Register OFDMPHRRX.RB18. More... | |
| #define | OFDMPHRRX_RB21_MASK 0x80 |
| Bit Mask for Sub-Register OFDMPHRRX.RB21. More... | |
| #define | OFDMPHRRX_RB21_SHIFT 7 |
| Bit Offset for Sub-Register OFDMPHRRX.RB21. More... | |
| #define | OFDMPHRRX_RB5_MASK 0x10 |
| Bit Mask for Sub-Register OFDMPHRRX.RB5. More... | |
| #define | OFDMPHRRX_RB5_SHIFT 4 |
| Bit Offset for Sub-Register OFDMPHRRX.RB5. More... | |
| #define | OFDMPHRRX_SPC_MASK 0x08 |
| Bit Mask for Sub-Register OFDMPHRRX.SPC. More... | |
| #define | OFDMPHRRX_SPC_SHIFT 3 |
| Bit Offset for Sub-Register OFDMPHRRX.SPC. More... | |
| #define | OFDMPHRTX_MCS_MASK 0x07 |
| Sub-registers of Register OFDMPHRTX. More... | |
| #define | OFDMPHRTX_MCS_SHIFT 0 |
| Bit Offset for Sub-Register OFDMPHRTX.MCS. More... | |
| #define | OFDMPHRTX_RB17_MASK 0x20 |
| Bit Mask for Sub-Register OFDMPHRTX.RB17. More... | |
| #define | OFDMPHRTX_RB17_SHIFT 5 |
| Bit Offset for Sub-Register OFDMPHRTX.RB17. More... | |
| #define | OFDMPHRTX_RB18_MASK 0x40 |
| Bit Mask for Sub-Register OFDMPHRTX.RB18. More... | |
| #define | OFDMPHRTX_RB18_SHIFT 6 |
| Bit Offset for Sub-Register OFDMPHRTX.RB18. More... | |
| #define | OFDMPHRTX_RB21_MASK 0x80 |
| Bit Mask for Sub-Register OFDMPHRTX.RB21. More... | |
| #define | OFDMPHRTX_RB21_SHIFT 7 |
| Bit Offset for Sub-Register OFDMPHRTX.RB21. More... | |
| #define | OFDMPHRTX_RB5_MASK 0x10 |
| Bit Mask for Sub-Register OFDMPHRTX.RB5. More... | |
| #define | OFDMPHRTX_RB5_SHIFT 4 |
| Bit Offset for Sub-Register OFDMPHRTX.RB5. More... | |
| #define | OFDMSW_PDT_MASK 0xE0 |
| Bit Mask for Sub-Register OFDMSW.PDT. More... | |
| #define | OFDMSW_PDT_SHIFT 5 |
| Bit Offset for Sub-Register OFDMSW.PDT. More... | |
| #define | OFDMSW_RXO_MASK 0x10 |
| Sub-registers of Register OFDMSW. More... | |
| #define | OFDMSW_RXO_SHIFT 4 |
| Bit Offset for Sub-Register OFDMSW.RXO. More... | |
| #define | OQPSKC0_DM_MASK 0x10 |
| Bit Mask for Sub-Register OQPSKC0.DM. More... | |
| #define | OQPSKC0_DM_SHIFT 4 |
| Bit Offset for Sub-Register OQPSKC0.DM. More... | |
| #define | OQPSKC0_FCHIP_MASK 0x03 |
| Sub-registers of Register OQPSKC0. More... | |
| #define | OQPSKC0_FCHIP_SHIFT 0 |
| Bit Offset for Sub-Register OQPSKC0.FCHIP. More... | |
| #define | OQPSKC0_MOD_MASK 0x08 |
| Bit Mask for Sub-Register OQPSKC0.MOD. More... | |
| #define | OQPSKC0_MOD_SHIFT 3 |
| Bit Offset for Sub-Register OQPSKC0.MOD. More... | |
| #define | OQPSKC1_PDT0_MASK 0x07 |
| Sub-registers of Register OQPSKC1. More... | |
| #define | OQPSKC1_PDT0_SHIFT 0 |
| Bit Offset for Sub-Register OQPSKC1.PDT0. More... | |
| #define | OQPSKC1_PDT1_MASK 0x38 |
| Bit Mask for Sub-Register OQPSKC1.PDT1. More... | |
| #define | OQPSKC1_PDT1_SHIFT 3 |
| Bit Offset for Sub-Register OQPSKC1.PDT1. More... | |
| #define | OQPSKC1_RXO_MASK 0x80 |
| Bit Mask for Sub-Register OQPSKC1.RXO. More... | |
| #define | OQPSKC1_RXO_SHIFT 7 |
| Bit Offset for Sub-Register OQPSKC1.RXO. More... | |
| #define | OQPSKC1_RXOLEG_MASK 0x40 |
| Bit Mask for Sub-Register OQPSKC1.RXOLEG. More... | |
| #define | OQPSKC1_RXOLEG_SHIFT 6 |
| Bit Offset for Sub-Register OQPSKC1.RXOLEG. More... | |
| #define | OQPSKC2_ENPROP_MASK 0x08 |
| Bit Mask for Sub-Register OQPSKC2.ENPROP. More... | |
| #define | OQPSKC2_ENPROP_SHIFT 3 |
| Bit Offset for Sub-Register OQPSKC2.ENPROP. More... | |
| #define | OQPSKC2_FCSTLEG_MASK 0x04 |
| Bit Mask for Sub-Register OQPSKC2.FCSTLEG. More... | |
| #define | OQPSKC2_FCSTLEG_SHIFT 2 |
| Bit Offset for Sub-Register OQPSKC2.FCSTLEG. More... | |
| #define | OQPSKC2_RPC_MASK 0x10 |
| Bit Mask for Sub-Register OQPSKC2.RPC. More... | |
| #define | OQPSKC2_RPC_SHIFT 4 |
| Bit Offset for Sub-Register OQPSKC2.RPC. More... | |
| #define | OQPSKC2_RXM_MASK 0x03 |
| Sub-registers of Register OQPSKC2. More... | |
| #define | OQPSKC2_RXM_SHIFT 0 |
| Bit Offset for Sub-Register OQPSKC2.RXM. More... | |
| #define | OQPSKC2_SPC_MASK 0x20 |
| Bit Mask for Sub-Register OQPSKC2.SPC. More... | |
| #define | OQPSKC2_SPC_SHIFT 5 |
| Bit Offset for Sub-Register OQPSKC2.SPC. More... | |
| #define | OQPSKC3_HRLEG_MASK 0x20 |
| Bit Mask for Sub-Register OQPSKC3.HRLEG. More... | |
| #define | OQPSKC3_HRLEG_SHIFT 5 |
| Bit Offset for Sub-Register OQPSKC3.HRLEG. More... | |
| #define | OQPSKC3_NSFD_MASK 0x0C |
| Sub-registers of Register OQPSKC3. More... | |
| #define | OQPSKC3_NSFD_SHIFT 2 |
| Bit Offset for Sub-Register OQPSKC3.NSFD. More... | |
| #define | OQPSKPHRRX_LEG_MASK 0x01 |
| Sub-registers of Register OQPSKPHRRX. More... | |
| #define | OQPSKPHRRX_LEG_SHIFT 0 |
| Bit Offset for Sub-Register OQPSKPHRRX.LEG. More... | |
| #define | OQPSKPHRRX_MOD_MASK 0x0E |
| Bit Mask for Sub-Register OQPSKPHRRX.MOD. More... | |
| #define | OQPSKPHRRX_MOD_SHIFT 1 |
| Bit Offset for Sub-Register OQPSKPHRRX.MOD. More... | |
| #define | OQPSKPHRRX_PPDUT_MASK 0x20 |
| Bit Mask for Sub-Register OQPSKPHRRX.PPDUT. More... | |
| #define | OQPSKPHRRX_PPDUT_SHIFT 5 |
| Bit Offset for Sub-Register OQPSKPHRRX.PPDUT. More... | |
| #define | OQPSKPHRRX_RB0_MASK 0x10 |
| Bit Mask for Sub-Register OQPSKPHRRX.RB0. More... | |
| #define | OQPSKPHRRX_RB0_SHIFT 4 |
| Bit Offset for Sub-Register OQPSKPHRRX.RB0. More... | |
| #define | OQPSKPHRTX_LEG_MASK 0x01 |
| Sub-registers of Register OQPSKPHRTX. More... | |
| #define | OQPSKPHRTX_LEG_SHIFT 0 |
| Bit Offset for Sub-Register OQPSKPHRTX.LEG. More... | |
| #define | OQPSKPHRTX_MOD_MASK 0x0E |
| Bit Mask for Sub-Register OQPSKPHRTX.MOD. More... | |
| #define | OQPSKPHRTX_MOD_SHIFT 1 |
| Bit Offset for Sub-Register OQPSKPHRTX.MOD. More... | |
| #define | OQPSKPHRTX_PPDUT_MASK 0x20 |
| Bit Mask for Sub-Register OQPSKPHRTX.PPDUT. More... | |
| #define | OQPSKPHRTX_PPDUT_SHIFT 5 |
| Bit Offset for Sub-Register OQPSKPHRTX.PPDUT. More... | |
| #define | OQPSKPHRTX_RB0_MASK 0x10 |
| Bit Mask for Sub-Register OQPSKPHRTX.RB0. More... | |
| #define | OQPSKPHRTX_RB0_SHIFT 4 |
| Bit Offset for Sub-Register OQPSKPHRTX.RB0. More... | |
| #define | PAC_PACUR_MASK 0x60 |
| Bit Mask for Sub-Register PAC.PACUR. More... | |
| #define | PAC_PACUR_SHIFT 5 |
| Bit Offset for Sub-Register PAC.PACUR. More... | |
| #define | PAC_TXPWR_MASK 0x1F |
| Sub-registers of Register PAC. More... | |
| #define | PAC_TXPWR_SHIFT 0 |
| Bit Offset for Sub-Register PAC.TXPWR. More... | |
| #define | PADFE_PADFE_MASK 0xC0 |
| Sub-registers of Register PADFE. More... | |
| #define | PADFE_PADFE_SHIFT 6 |
| Bit Offset for Sub-Register PADFE.PADFE. More... | |
| #define | PC_BBEN_MASK 0x04 |
| Bit Mask for Sub-Register PC.BBEN. More... | |
| #define | PC_BBEN_SHIFT 2 |
| Bit Offset for Sub-Register PC.BBEN. More... | |
| #define | PC_CTX_MASK 0x80 |
| Bit Mask for Sub-Register PC.CTX. More... | |
| #define | PC_CTX_SHIFT 7 |
| Bit Offset for Sub-Register PC.CTX. More... | |
| #define | PC_FCSFE_MASK 0x40 |
| Bit Mask for Sub-Register PC.FCSFE. More... | |
| #define | PC_FCSFE_SHIFT 6 |
| Bit Offset for Sub-Register PC.FCSFE. More... | |
| #define | PC_FCSOK_MASK 0x20 |
| Bit Mask for Sub-Register PC.FCSOK. More... | |
| #define | PC_FCSOK_SHIFT 5 |
| Bit Offset for Sub-Register PC.FCSOK. More... | |
| #define | PC_FCST_MASK 0x08 |
| Bit Mask for Sub-Register PC.FCST. More... | |
| #define | PC_FCST_SHIFT 3 |
| Bit Offset for Sub-Register PC.FCST. More... | |
| #define | PC_PT_MASK 0x03 |
| Sub-registers of Register PC. More... | |
| #define | PC_PT_SHIFT 0 |
| Bit Offset for Sub-Register PC.PT. More... | |
| #define | PC_TXAFCS_MASK 0x10 |
| Bit Mask for Sub-Register PC.TXAFCS. More... | |
| #define | PC_TXAFCS_SHIFT 4 |
| Bit Offset for Sub-Register PC.TXAFCS. More... | |
| #define | PLL_LBW_MASK 0x30 |
| Bit Mask for Sub-Register PLL.LBW. More... | |
| #define | PLL_LBW_SHIFT 4 |
| Bit Offset for Sub-Register PLL.LBW. More... | |
| #define | PLL_LS_MASK 0x02 |
| Sub-registers of Register PLL. More... | |
| #define | PLL_LS_SHIFT 1 |
| Bit Offset for Sub-Register PLL.LS. More... | |
| #define | PLLCF_CF_MASK 0x3F |
| Sub-registers of Register PLLCF. More... | |
| #define | PLLCF_CF_SHIFT 0 |
| Bit Offset for Sub-Register PLLCF.CF. More... | |
| #define | PMUC_AVG_MASK 0x02 |
| Bit Mask for Sub-Register PMUC.AVG. More... | |
| #define | PMUC_AVG_SHIFT 1 |
| Bit Offset for Sub-Register PMUC.AVG. More... | |
| #define | PMUC_CCFTS_MASK 0x80 |
| Bit Mask for Sub-Register PMUC.CCFTS. More... | |
| #define | PMUC_CCFTS_SHIFT 7 |
| Bit Offset for Sub-Register PMUC.CCFTS. More... | |
| #define | PMUC_EN_MASK 0x01 |
| Sub-registers of Register PMUC. More... | |
| #define | PMUC_EN_SHIFT 0 |
| Bit Offset for Sub-Register PMUC.EN. More... | |
| #define | PMUC_FED_MASK 0x20 |
| Bit Mask for Sub-Register PMUC.FED. More... | |
| #define | PMUC_FED_SHIFT 5 |
| Bit Offset for Sub-Register PMUC.FED. More... | |
| #define | PMUC_IQSEL_MASK 0x40 |
| Bit Mask for Sub-Register PMUC.IQSEL. More... | |
| #define | PMUC_IQSEL_SHIFT 6 |
| Bit Offset for Sub-Register PMUC.IQSEL. More... | |
| #define | PMUC_SYNC_MASK 0x1C |
| Bit Mask for Sub-Register PMUC.SYNC. More... | |
| #define | PMUC_SYNC_SHIFT 2 |
| Bit Offset for Sub-Register PMUC.SYNC. More... | |
| #define | PMUI_PMUI_MASK 0xFF |
| Sub-registers of Register PMUI. More... | |
| #define | PMUI_PMUI_SHIFT 0 |
| Bit Offset for Sub-Register PMUI.PMUI. More... | |
| #define | PMUQ_PMUQ_MASK 0xFF |
| Sub-registers of Register PMUQ. More... | |
| #define | PMUQ_PMUQ_SHIFT 0 |
| Bit Offset for Sub-Register PMUQ.PMUQ. More... | |
| #define | PMUQF_PMUQF_MASK 0xFF |
| Sub-registers of Register PMUQF. More... | |
| #define | PMUQF_PMUQF_SHIFT 0 |
| Bit Offset for Sub-Register PMUQF.PMUQF. More... | |
| #define | PMUVAL_PMUVAL_MASK 0xFF |
| Sub-registers of Register PMUVAL. More... | |
| #define | PMUVAL_PMUVAL_SHIFT 0 |
| Bit Offset for Sub-Register PMUVAL.PMUVAL. More... | |
| #define | PN_PN_MASK 0xFF |
| Sub-registers of Register PN. More... | |
| #define | PN_PN_SHIFT 0 |
| Bit Offset for Sub-Register PN.PN. More... | |
| #define | PS_TXUR_MASK 0x01 |
| Sub-registers of Register PS. More... | |
| #define | PS_TXUR_SHIFT 0 |
| Bit Offset for Sub-Register PS.TXUR. More... | |
| #define | RF_BW1000KHZ_IF1000KHZ (0x8) |
| Constant BW1000KHZ_IF1000KHZ for sub-register SR_BW in register RF09_RXBWC. More... | |
| #define | RF_BW1250KHZ_IF2000KHZ (0x9) |
| Constant BW1250KHZ_IF2000KHZ for sub-register SR_BW in register RF09_RXBWC. More... | |
| #define | RF_BW1600KHZ_IF2000KHZ (0xA) |
| Constant BW1600KHZ_IF2000KHZ for sub-register SR_BW in register RF09_RXBWC. More... | |
| #define | RF_BW160KHZ_IF250KHZ (0x0) |
| Constant BW160KHZ_IF250KHZ for sub-register SR_BW in register RF09_RXBWC. More... | |
| #define | RF_BW2000KHZ_IF2000KHZ (0xB) |
| Constant BW2000KHZ_IF2000KHZ for sub-register SR_BW in register RF09_RXBWC. More... | |
| #define | RF_BW200KHZ_IF250KHZ (0x1) |
| Constant BW200KHZ_IF250KHZ for sub-register SR_BW in register RF09_RXBWC. More... | |
| #define | RF_BW250KHZ_IF250KHZ (0x2) |
| Constant BW250KHZ_IF250KHZ for sub-register SR_BW in register RF09_RXBWC. More... | |
| #define | RF_BW320KHZ_IF500KHZ (0x3) |
| Constant BW320KHZ_IF500KHZ for sub-register SR_BW in register RF09_RXBWC. More... | |
| #define | RF_BW400KHZ_IF500KHZ (0x4) |
| Constant BW400KHZ_IF500KHZ for sub-register SR_BW in register RF09_RXBWC. More... | |
| #define | RF_BW500KHZ_IF500KHZ (0x5) |
| Constant BW500KHZ_IF500KHZ for sub-register SR_BW in register RF09_RXBWC. More... | |
| #define | RF_BW630KHZ_IF1000KHZ (0x6) |
| Constant BW630KHZ_IF1000KHZ for sub-register SR_BW in register RF09_RXBWC. More... | |
| #define | RF_BW800KHZ_IF1000KHZ (0x7) |
| Constant BW800KHZ_IF1000KHZ for sub-register SR_BW in register RF09_RXBWC. More... | |
| #define | RF_DRV2 (0x0) |
| Constant DRV2 for sub-register SR_DRV in register RF_CFG. More... | |
| #define | RF_DRV4 (0x1) |
| Constant DRV4 for sub-register SR_DRV in register RF_CFG. More... | |
| #define | RF_DRV6 (0x2) |
| Constant DRV6 for sub-register SR_DRV in register RF_CFG. More... | |
| #define | RF_DRV8 (0x3) |
| Constant DRV8 for sub-register SR_DRV in register RF_CFG. More... | |
| #define | RF_DRVCLKO2 (0x0) |
| Constant DRVCLKO2 for sub-register SR_DRV in register RF_CLKO. More... | |
| #define | RF_DRVCLKO4 (0x1) |
| Constant DRVCLKO4 for sub-register SR_DRV in register RF_CLKO. More... | |
| #define | RF_DRVCLKO6 (0x2) |
| Constant DRVCLKO6 for sub-register SR_DRV in register RF_CLKO. More... | |
| #define | RF_DRVCLKO8 (0x3) |
| Constant DRVCLKO8 for sub-register SR_DRV in register RF_CLKO. More... | |
| #define | RF_EDAUTO (0x0) |
| Constant EDAUTO for sub-register SR_EDM in register RF09_EDC. More... | |
| #define | RF_EDCONT (0x2) |
| Constant EDCONT for sub-register SR_EDM in register RF09_EDC. More... | |
| #define | RF_EDOFF (0x3) |
| Constant EDOFF for sub-register SR_EDM in register RF09_EDC. More... | |
| #define | RF_EDSINGLE (0x1) |
| Constant EDSINGLE for sub-register SR_EDM in register RF09_EDC. More... | |
| #define | RF_FEMODE0 (0x0) |
| Constant FEMODE0 for sub-register SR_PADFE in register RF09_PADFE. More... | |
| #define | RF_FEMODE1 (0x1) |
| Constant FEMODE1 for sub-register SR_PADFE in register RF09_PADFE. More... | |
| #define | RF_FEMODE2 (0x2) |
| Constant FEMODE2 for sub-register SR_PADFE in register RF09_PADFE. More... | |
| #define | RF_FEMODE3 (0x3) |
| Constant FEMODE3 for sub-register SR_PADFE in register RF09_PADFE. More... | |
| #define | RF_FLC1000KHZ (0xB) |
| Constant FLC1000KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC. More... | |
| #define | RF_FLC100KHZ (0x1) |
| Constant FLC100KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC. More... | |
| #define | RF_FLC125KHZ (0x2) |
| Constant FLC125KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC. More... | |
| #define | RF_FLC160KHZ (0x3) |
| Constant FLC160KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC. More... | |
| #define | RF_FLC200KHZ (0x4) |
| Constant FLC200KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC. More... | |
| #define | RF_FLC250KHZ (0x5) |
| Constant FLC250KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC. More... | |
| #define | RF_FLC315KHZ (0x6) |
| Constant FLC315KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC. More... | |
| #define | RF_FLC400KHZ (0x7) |
| Constant FLC400KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC. More... | |
| #define | RF_FLC500KHZ (0x8) |
| Constant FLC500KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC. More... | |
| #define | RF_FLC625KHZ (0x9) |
| Constant FLC625KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC. More... | |
| #define | RF_FLC800KHZ (0xA) |
| Constant FLC800KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC. More... | |
| #define | RF_FLC80KHZ (0x0) |
| Constant FLC80KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC. More... | |
| #define | RF_MODE_BBRF (0x0) |
| Constant MODE_BBRF for sub-register SR_CHPM in register RF_IQIFC1. More... | |
| #define | RF_MODE_BBRF09 (0x4) |
| Constant MODE_BBRF09 for sub-register SR_CHPM in register RF_IQIFC1. More... | |
| #define | RF_MODE_BBRF24 (0x5) |
| Constant MODE_BBRF24 for sub-register SR_CHPM in register RF_IQIFC1. More... | |
| #define | RF_MODE_RF (0x1) |
| Constant MODE_RF for sub-register SR_CHPM in register RF_IQIFC1. More... | |
| #define | RF_PARAMP16U (0x2) |
| Constant PARAMP16U for sub-register SR_PARAMP in register RF09_TXCUTC. More... | |
| #define | RF_PARAMP32U (0x3) |
| Constant PARAMP32U for sub-register SR_PARAMP in register RF09_TXCUTC. More... | |
| #define | RF_PARAMP4U (0x0) |
| Constant PARAMP4U for sub-register SR_PARAMP in register RF09_TXCUTC. More... | |
| #define | RF_PARAMP8U (0x1) |
| Constant PARAMP8U for sub-register SR_PARAMP in register RF09_TXCUTC. More... | |
| #define | RF_TRANSITION (0x6) |
| Constant TRANSITION for sub-register SR_STATE in register RF09_STATE. More... | |
| #define | RG_BBC0_AFC0 (0x320) |
| Address for register BBC0_AFC0. More... | |
| #define | RG_BBC0_AFC1 (0x321) |
| Address for register BBC0_AFC1. More... | |
| #define | RG_BBC0_AFFTM (0x322) |
| Address for register BBC0_AFFTM. More... | |
| #define | RG_BBC0_AFFVM (0x323) |
| Address for register BBC0_AFFVM. More... | |
| #define | RG_BBC0_AFS (0x324) |
| Address for register BBC0_AFS. More... | |
| #define | RG_BBC0_AMAACKPD (0x342) |
| Address for register BBC0_AMAACKPD. More... | |
| #define | RG_BBC0_AMAACKTH (0x344) |
| Address for register BBC0_AMAACKTH. More... | |
| #define | RG_BBC0_AMAACKTL (0x343) |
| Address for register BBC0_AMAACKTL. More... | |
| #define | RG_BBC0_AMCS (0x340) |
| Address for register BBC0_AMCS. More... | |
| #define | RG_BBC0_AMEDT (0x341) |
| Address for register BBC0_AMEDT. More... | |
| #define | RG_BBC0_CNT0 (0x391) |
| Address for register BBC0_CNT0. More... | |
| #define | RG_BBC0_CNT1 (0x392) |
| Address for register BBC0_CNT1. More... | |
| #define | RG_BBC0_CNT2 (0x393) |
| Address for register BBC0_CNT2. More... | |
| #define | RG_BBC0_CNT3 (0x394) |
| Address for register BBC0_CNT3. More... | |
| #define | RG_BBC0_CNTC (0x390) |
| Address for register BBC0_CNTC. More... | |
| #define | RG_BBC0_FBLH (0x309) |
| Address for register BBC0_FBLH. More... | |
| #define | RG_BBC0_FBLIH (0x30B) |
| Address for register BBC0_FBLIH. More... | |
| #define | RG_BBC0_FBLIL (0x30A) |
| Address for register BBC0_FBLIL. More... | |
| #define | RG_BBC0_FBLL (0x308) |
| Address for register BBC0_FBLL. More... | |
| #define | RG_BBC0_FBRXE (0x27FE) |
| Address for register BBC0_FBRXE. More... | |
| #define | RG_BBC0_FBRXS (0x2000) |
| Address for register BBC0_FBRXS. More... | |
| #define | RG_BBC0_FBTXE (0x2FFE) |
| Address for register BBC0_FBTXE. More... | |
| #define | RG_BBC0_FBTXS (0x2800) |
| Address for register BBC0_FBTXS. More... | |
| #define | RG_BBC0_FSKC0 (0x360) |
| Address for register BBC0_FSKC0. More... | |
| #define | RG_BBC0_FSKC1 (0x361) |
| Address for register BBC0_FSKC1. More... | |
| #define | RG_BBC0_FSKC2 (0x362) |
| Address for register BBC0_FSKC2. More... | |
| #define | RG_BBC0_FSKC3 (0x363) |
| Address for register BBC0_FSKC3. More... | |
| #define | RG_BBC0_FSKC4 (0x364) |
| Address for register BBC0_FSKC4. More... | |
| #define | RG_BBC0_FSKDM (0x372) |
| Address for register BBC0_FSKDM. More... | |
| #define | RG_BBC0_FSKPE0 (0x373) |
| Address for register BBC0_FSKPE0. More... | |
| #define | RG_BBC0_FSKPE1 (0x374) |
| Address for register BBC0_FSKPE1. More... | |
| #define | RG_BBC0_FSKPE2 (0x375) |
| Address for register BBC0_FSKPE2. More... | |
| #define | RG_BBC0_FSKPHRRX (0x36B) |
| Address for register BBC0_FSKPHRRX. More... | |
| #define | RG_BBC0_FSKPHRTX (0x36A) |
| Address for register BBC0_FSKPHRTX. More... | |
| #define | RG_BBC0_FSKPLL (0x365) |
| Address for register BBC0_FSKPLL. More... | |
| #define | RG_BBC0_FSKRPC (0x36C) |
| Address for register BBC0_FSKRPC. More... | |
| #define | RG_BBC0_FSKRPCOFFT (0x36E) |
| Address for register BBC0_FSKRPCOFFT. More... | |
| #define | RG_BBC0_FSKRPCONT (0x36D) |
| Address for register BBC0_FSKRPCONT. More... | |
| #define | RG_BBC0_FSKRRXFLH (0x371) |
| Address for register BBC0_FSKRRXFLH. More... | |
| #define | RG_BBC0_FSKRRXFLL (0x370) |
| Address for register BBC0_FSKRRXFLL. More... | |
| #define | RG_BBC0_FSKSFD0H (0x367) |
| Address for register BBC0_FSKSFD0H. More... | |
| #define | RG_BBC0_FSKSFD0L (0x366) |
| Address for register BBC0_FSKSFD0L. More... | |
| #define | RG_BBC0_FSKSFD1H (0x369) |
| Address for register BBC0_FSKSFD1H. More... | |
| #define | RG_BBC0_FSKSFD1L (0x368) |
| Address for register BBC0_FSKSFD1L. More... | |
| #define | RG_BBC0_IRQM (0x300) |
| Address for register BBC0_IRQM. More... | |
| #define | RG_BBC0_IRQS (0x02) |
| Address for register BBC0_IRQS. More... | |
| #define | RG_BBC0_MACEA0 (0x325) |
| Address for register BBC0_MACEA0. More... | |
| #define | RG_BBC0_MACEA1 (0x326) |
| Address for register BBC0_MACEA1. More... | |
| #define | RG_BBC0_MACEA2 (0x327) |
| Address for register BBC0_MACEA2. More... | |
| #define | RG_BBC0_MACEA3 (0x328) |
| Address for register BBC0_MACEA3. More... | |
| #define | RG_BBC0_MACEA4 (0x329) |
| Address for register BBC0_MACEA4. More... | |
| #define | RG_BBC0_MACEA5 (0x32A) |
| Address for register BBC0_MACEA5. More... | |
| #define | RG_BBC0_MACEA6 (0x32B) |
| Address for register BBC0_MACEA6. More... | |
| #define | RG_BBC0_MACEA7 (0x32C) |
| Address for register BBC0_MACEA7. More... | |
| #define | RG_BBC0_MACPID0F0 (0x32D) |
| Address for register BBC0_MACPID0F0. More... | |
| #define | RG_BBC0_MACPID0F1 (0x331) |
| Address for register BBC0_MACPID0F1. More... | |
| #define | RG_BBC0_MACPID0F2 (0x335) |
| Address for register BBC0_MACPID0F2. More... | |
| #define | RG_BBC0_MACPID0F3 (0x339) |
| Address for register BBC0_MACPID0F3. More... | |
| #define | RG_BBC0_MACPID1F0 (0x32E) |
| Address for register BBC0_MACPID1F0. More... | |
| #define | RG_BBC0_MACPID1F1 (0x332) |
| Address for register BBC0_MACPID1F1. More... | |
| #define | RG_BBC0_MACPID1F2 (0x336) |
| Address for register BBC0_MACPID1F2. More... | |
| #define | RG_BBC0_MACPID1F3 (0x33A) |
| Address for register BBC0_MACPID1F3. More... | |
| #define | RG_BBC0_MACSHA0F0 (0x32F) |
| Address for register BBC0_MACSHA0F0. More... | |
| #define | RG_BBC0_MACSHA0F1 (0x333) |
| Address for register BBC0_MACSHA0F1. More... | |
| #define | RG_BBC0_MACSHA0F2 (0x337) |
| Address for register BBC0_MACSHA0F2. More... | |
| #define | RG_BBC0_MACSHA0F3 (0x33B) |
| Address for register BBC0_MACSHA0F3. More... | |
| #define | RG_BBC0_MACSHA1F0 (0x330) |
| Address for register BBC0_MACSHA1F0. More... | |
| #define | RG_BBC0_MACSHA1F1 (0x334) |
| Address for register BBC0_MACSHA1F1. More... | |
| #define | RG_BBC0_MACSHA1F2 (0x338) |
| Address for register BBC0_MACSHA1F2. More... | |
| #define | RG_BBC0_MACSHA1F3 (0x33C) |
| Address for register BBC0_MACSHA1F3. More... | |
| #define | RG_BBC0_OFDMC (0x30E) |
| Address for register BBC0_OFDMC. More... | |
| #define | RG_BBC0_OFDMPHRRX (0x30D) |
| Address for register BBC0_OFDMPHRRX. More... | |
| #define | RG_BBC0_OFDMPHRTX (0x30C) |
| Address for register BBC0_OFDMPHRTX. More... | |
| #define | RG_BBC0_OFDMSW (0x30F) |
| Address for register BBC0_OFDMSW. More... | |
| #define | RG_BBC0_OQPSKC0 (0x310) |
| Address for register BBC0_OQPSKC0. More... | |
| #define | RG_BBC0_OQPSKC1 (0x311) |
| Address for register BBC0_OQPSKC1. More... | |
| #define | RG_BBC0_OQPSKC2 (0x312) |
| Address for register BBC0_OQPSKC2. More... | |
| #define | RG_BBC0_OQPSKC3 (0x313) |
| Address for register BBC0_OQPSKC3. More... | |
| #define | RG_BBC0_OQPSKPHRRX (0x315) |
| Address for register BBC0_OQPSKPHRRX. More... | |
| #define | RG_BBC0_OQPSKPHRTX (0x314) |
| Address for register BBC0_OQPSKPHRTX. More... | |
| #define | RG_BBC0_PC (0x301) |
| Address for register BBC0_PC. More... | |
| #define | RG_BBC0_PMUC (0x380) |
| Address for register BBC0_PMUC. More... | |
| #define | RG_BBC0_PMUI (0x383) |
| Address for register BBC0_PMUI. More... | |
| #define | RG_BBC0_PMUQ (0x384) |
| Address for register BBC0_PMUQ. More... | |
| #define | RG_BBC0_PMUQF (0x382) |
| Address for register BBC0_PMUQF. More... | |
| #define | RG_BBC0_PMUVAL (0x381) |
| Address for register BBC0_PMUVAL. More... | |
| #define | RG_BBC0_PS (0x302) |
| Address for register BBC0_PS. More... | |
| #define | RG_BBC0_RXFLH (0x305) |
| Address for register BBC0_RXFLH. More... | |
| #define | RG_BBC0_RXFLL (0x304) |
| Address for register BBC0_RXFLL. More... | |
| #define | RG_BBC0_TXFLH (0x307) |
| Address for register BBC0_TXFLH. More... | |
| #define | RG_BBC0_TXFLL (0x306) |
| Address for register BBC0_TXFLL. More... | |
| #define | RG_BBC1_AFC0 (0x420) |
| Address for register BBC1_AFC0. More... | |
| #define | RG_BBC1_AFC1 (0x421) |
| Address for register BBC1_AFC1. More... | |
| #define | RG_BBC1_AFFTM (0x422) |
| Address for register BBC1_AFFTM. More... | |
| #define | RG_BBC1_AFFVM (0x423) |
| Address for register BBC1_AFFVM. More... | |
| #define | RG_BBC1_AFS (0x424) |
| Address for register BBC1_AFS. More... | |
| #define | RG_BBC1_AMAACKPD (0x442) |
| Address for register BBC1_AMAACKPD. More... | |
| #define | RG_BBC1_AMAACKTH (0x444) |
| Address for register BBC1_AMAACKTH. More... | |
| #define | RG_BBC1_AMAACKTL (0x443) |
| Address for register BBC1_AMAACKTL. More... | |
| #define | RG_BBC1_AMCS (0x440) |
| Address for register BBC1_AMCS. More... | |
| #define | RG_BBC1_AMEDT (0x441) |
| Address for register BBC1_AMEDT. More... | |
| #define | RG_BBC1_CNT0 (0x491) |
| Address for register BBC1_CNT0. More... | |
| #define | RG_BBC1_CNT1 (0x492) |
| Address for register BBC1_CNT1. More... | |
| #define | RG_BBC1_CNT2 (0x493) |
| Address for register BBC1_CNT2. More... | |
| #define | RG_BBC1_CNT3 (0x494) |
| Address for register BBC1_CNT3. More... | |
| #define | RG_BBC1_CNTC (0x490) |
| Address for register BBC1_CNTC. More... | |
| #define | RG_BBC1_FBLH (0x409) |
| Address for register BBC1_FBLH. More... | |
| #define | RG_BBC1_FBLIH (0x40B) |
| Address for register BBC1_FBLIH. More... | |
| #define | RG_BBC1_FBLIL (0x40A) |
| Address for register BBC1_FBLIL. More... | |
| #define | RG_BBC1_FBLL (0x408) |
| Address for register BBC1_FBLL. More... | |
| #define | RG_BBC1_FBRXE (0x37FE) |
| Address for register BBC1_FBRXE. More... | |
| #define | RG_BBC1_FBRXS (0x3000) |
| Address for register BBC1_FBRXS. More... | |
| #define | RG_BBC1_FBTXE (0x3FFE) |
| Address for register BBC1_FBTXE. More... | |
| #define | RG_BBC1_FBTXS (0x3800) |
| Address for register BBC1_FBTXS. More... | |
| #define | RG_BBC1_FSKC0 (0x460) |
| Address for register BBC1_FSKC0. More... | |
| #define | RG_BBC1_FSKC1 (0x461) |
| Address for register BBC1_FSKC1. More... | |
| #define | RG_BBC1_FSKC2 (0x462) |
| Address for register BBC1_FSKC2. More... | |
| #define | RG_BBC1_FSKC3 (0x463) |
| Address for register BBC1_FSKC3. More... | |
| #define | RG_BBC1_FSKC4 (0x464) |
| Address for register BBC1_FSKC4. More... | |
| #define | RG_BBC1_FSKDM (0x472) |
| Address for register BBC1_FSKDM. More... | |
| #define | RG_BBC1_FSKPE0 (0x473) |
| Address for register BBC1_FSKPE0. More... | |
| #define | RG_BBC1_FSKPE1 (0x474) |
| Address for register BBC1_FSKPE1. More... | |
| #define | RG_BBC1_FSKPE2 (0x475) |
| Address for register BBC1_FSKPE2. More... | |
| #define | RG_BBC1_FSKPHRRX (0x46B) |
| Address for register BBC1_FSKPHRRX. More... | |
| #define | RG_BBC1_FSKPHRTX (0x46A) |
| Address for register BBC1_FSKPHRTX. More... | |
| #define | RG_BBC1_FSKPLL (0x465) |
| Address for register BBC1_FSKPLL. More... | |
| #define | RG_BBC1_FSKRPC (0x46C) |
| Address for register BBC1_FSKRPC. More... | |
| #define | RG_BBC1_FSKRPCOFFT (0x46E) |
| Address for register BBC1_FSKRPCOFFT. More... | |
| #define | RG_BBC1_FSKRPCONT (0x46D) |
| Address for register BBC1_FSKRPCONT. More... | |
| #define | RG_BBC1_FSKRRXFLH (0x471) |
| Address for register BBC1_FSKRRXFLH. More... | |
| #define | RG_BBC1_FSKRRXFLL (0x470) |
| Address for register BBC1_FSKRRXFLL. More... | |
| #define | RG_BBC1_FSKSFD0H (0x467) |
| Address for register BBC1_FSKSFD0H. More... | |
| #define | RG_BBC1_FSKSFD0L (0x466) |
| Address for register BBC1_FSKSFD0L. More... | |
| #define | RG_BBC1_FSKSFD1H (0x469) |
| Address for register BBC1_FSKSFD1H. More... | |
| #define | RG_BBC1_FSKSFD1L (0x468) |
| Address for register BBC1_FSKSFD1L. More... | |
| #define | RG_BBC1_IRQM (0x400) |
| Address for register BBC1_IRQM. More... | |
| #define | RG_BBC1_IRQS (0x03) |
| Address for register BBC1_IRQS. More... | |
| #define | RG_BBC1_MACEA0 (0x425) |
| Address for register BBC1_MACEA0. More... | |
| #define | RG_BBC1_MACEA1 (0x426) |
| Address for register BBC1_MACEA1. More... | |
| #define | RG_BBC1_MACEA2 (0x427) |
| Address for register BBC1_MACEA2. More... | |
| #define | RG_BBC1_MACEA3 (0x428) |
| Address for register BBC1_MACEA3. More... | |
| #define | RG_BBC1_MACEA4 (0x429) |
| Address for register BBC1_MACEA4. More... | |
| #define | RG_BBC1_MACEA5 (0x42A) |
| Address for register BBC1_MACEA5. More... | |
| #define | RG_BBC1_MACEA6 (0x42B) |
| Address for register BBC1_MACEA6. More... | |
| #define | RG_BBC1_MACEA7 (0x42C) |
| Address for register BBC1_MACEA7. More... | |
| #define | RG_BBC1_MACPID0F0 (0x42D) |
| Address for register BBC1_MACPID0F0. More... | |
| #define | RG_BBC1_MACPID0F1 (0x431) |
| Address for register BBC1_MACPID0F1. More... | |
| #define | RG_BBC1_MACPID0F2 (0x435) |
| Address for register BBC1_MACPID0F2. More... | |
| #define | RG_BBC1_MACPID0F3 (0x439) |
| Address for register BBC1_MACPID0F3. More... | |
| #define | RG_BBC1_MACPID1F0 (0x42E) |
| Address for register BBC1_MACPID1F0. More... | |
| #define | RG_BBC1_MACPID1F1 (0x432) |
| Address for register BBC1_MACPID1F1. More... | |
| #define | RG_BBC1_MACPID1F2 (0x436) |
| Address for register BBC1_MACPID1F2. More... | |
| #define | RG_BBC1_MACPID1F3 (0x43A) |
| Address for register BBC1_MACPID1F3. More... | |
| #define | RG_BBC1_MACSHA0F0 (0x42F) |
| Address for register BBC1_MACSHA0F0. More... | |
| #define | RG_BBC1_MACSHA0F1 (0x433) |
| Address for register BBC1_MACSHA0F1. More... | |
| #define | RG_BBC1_MACSHA0F2 (0x437) |
| Address for register BBC1_MACSHA0F2. More... | |
| #define | RG_BBC1_MACSHA0F3 (0x43B) |
| Address for register BBC1_MACSHA0F3. More... | |
| #define | RG_BBC1_MACSHA1F0 (0x430) |
| Address for register BBC1_MACSHA1F0. More... | |
| #define | RG_BBC1_MACSHA1F1 (0x434) |
| Address for register BBC1_MACSHA1F1. More... | |
| #define | RG_BBC1_MACSHA1F2 (0x438) |
| Address for register BBC1_MACSHA1F2. More... | |
| #define | RG_BBC1_MACSHA1F3 (0x43C) |
| Address for register BBC1_MACSHA1F3. More... | |
| #define | RG_BBC1_OFDMC (0x40E) |
| Address for register BBC1_OFDMC. More... | |
| #define | RG_BBC1_OFDMPHRRX (0x40D) |
| Address for register BBC1_OFDMPHRRX. More... | |
| #define | RG_BBC1_OFDMPHRTX (0x40C) |
| Address for register BBC1_OFDMPHRTX. More... | |
| #define | RG_BBC1_OFDMSW (0x40F) |
| Address for register BBC1_OFDMSW. More... | |
| #define | RG_BBC1_OQPSKC0 (0x410) |
| Address for register BBC1_OQPSKC0. More... | |
| #define | RG_BBC1_OQPSKC1 (0x411) |
| Address for register BBC1_OQPSKC1. More... | |
| #define | RG_BBC1_OQPSKC2 (0x412) |
| Address for register BBC1_OQPSKC2. More... | |
| #define | RG_BBC1_OQPSKC3 (0x413) |
| Address for register BBC1_OQPSKC3. More... | |
| #define | RG_BBC1_OQPSKPHRRX (0x415) |
| Address for register BBC1_OQPSKPHRRX. More... | |
| #define | RG_BBC1_OQPSKPHRTX (0x414) |
| Address for register BBC1_OQPSKPHRTX. More... | |
| #define | RG_BBC1_PC (0x401) |
| Address for register BBC1_PC. More... | |
| #define | RG_BBC1_PMUC (0x480) |
| Address for register BBC1_PMUC. More... | |
| #define | RG_BBC1_PMUI (0x483) |
| Address for register BBC1_PMUI. More... | |
| #define | RG_BBC1_PMUQ (0x484) |
| Address for register BBC1_PMUQ. More... | |
| #define | RG_BBC1_PMUQF (0x482) |
| Address for register BBC1_PMUQF. More... | |
| #define | RG_BBC1_PMUVAL (0x481) |
| Address for register BBC1_PMUVAL. More... | |
| #define | RG_BBC1_PS (0x402) |
| Address for register BBC1_PS. More... | |
| #define | RG_BBC1_RXFLH (0x405) |
| Address for register BBC1_RXFLH. More... | |
| #define | RG_BBC1_RXFLL (0x404) |
| Address for register BBC1_RXFLL. More... | |
| #define | RG_BBC1_TXFLH (0x407) |
| Address for register BBC1_TXFLH. More... | |
| #define | RG_BBC1_TXFLL (0x406) |
| Address for register BBC1_TXFLL. More... | |
| #define | RG_RF09_AGCC (0x10B) |
| Address for register RF09_AGCC. More... | |
| #define | RG_RF09_AGCS (0x10C) |
| Address for register RF09_AGCS. More... | |
| #define | RG_RF09_AUXS (0x101) |
| Address for register RF09_AUXS. More... | |
| #define | RG_RF09_CCF0H (0x106) |
| Address for register RF09_CCF0H. More... | |
| #define | RG_RF09_CCF0L (0x105) |
| Address for register RF09_CCF0L. More... | |
| #define | RG_RF09_CMD (0x103) |
| Address for register RF09_CMD. More... | |
| #define | RG_RF09_CNL (0x107) |
| Address for register RF09_CNL. More... | |
| #define | RG_RF09_CNM (0x108) |
| Address for register RF09_CNM. More... | |
| #define | RG_RF09_CS (0x104) |
| Address for register RF09_CS. More... | |
| #define | RG_RF09_EDC (0x10E) |
| Address for register RF09_EDC. More... | |
| #define | RG_RF09_EDD (0x10F) |
| Address for register RF09_EDD. More... | |
| #define | RG_RF09_EDV (0x110) |
| Address for register RF09_EDV. More... | |
| #define | RG_RF09_IRQM (0x100) |
| Address for register RF09_IRQM. More... | |
| #define | RG_RF09_IRQS (0x00) |
| Register addresses. More... | |
| #define | RG_RF09_PAC (0x114) |
| Address for register RF09_PAC. More... | |
| #define | RG_RF09_PADFE (0x116) |
| Address for register RF09_PADFE. More... | |
| #define | RG_RF09_PLL (0x121) |
| Address for register RF09_PLL. More... | |
| #define | RG_RF09_PLLCF (0x122) |
| Address for register RF09_PLLCF. More... | |
| #define | RG_RF09_RNDV (0x111) |
| Address for register RF09_RNDV. More... | |
| #define | RG_RF09_RSSI (0x10D) |
| Address for register RF09_RSSI. More... | |
| #define | RG_RF09_RXBWC (0x109) |
| Address for register RF09_RXBWC. More... | |
| #define | RG_RF09_RXDFE (0x10A) |
| Address for register RF09_RXDFE. More... | |
| #define | RG_RF09_STATE (0x102) |
| Address for register RF09_STATE. More... | |
| #define | RG_RF09_TXCI (0x125) |
| Address for register RF09_TXCI. More... | |
| #define | RG_RF09_TXCQ (0x126) |
| Address for register RF09_TXCQ. More... | |
| #define | RG_RF09_TXCUTC (0x112) |
| Address for register RF09_TXCUTC. More... | |
| #define | RG_RF09_TXDACI (0x127) |
| Address for register RF09_TXDACI. More... | |
| #define | RG_RF09_TXDACQ (0x128) |
| Address for register RF09_TXDACQ. More... | |
| #define | RG_RF09_TXDFE (0x113) |
| Address for register RF09_TXDFE. More... | |
| #define | RG_RF24_AGCC (0x20B) |
| Address for register RF24_AGCC. More... | |
| #define | RG_RF24_AGCS (0x20C) |
| Address for register RF24_AGCS. More... | |
| #define | RG_RF24_AUXS (0x201) |
| Address for register RF24_AUXS. More... | |
| #define | RG_RF24_CCF0H (0x206) |
| Address for register RF24_CCF0H. More... | |
| #define | RG_RF24_CCF0L (0x205) |
| Address for register RF24_CCF0L. More... | |
| #define | RG_RF24_CMD (0x203) |
| Address for register RF24_CMD. More... | |
| #define | RG_RF24_CNL (0x207) |
| Address for register RF24_CNL. More... | |
| #define | RG_RF24_CNM (0x208) |
| Address for register RF24_CNM. More... | |
| #define | RG_RF24_CS (0x204) |
| Address for register RF24_CS. More... | |
| #define | RG_RF24_EDC (0x20E) |
| Address for register RF24_EDC. More... | |
| #define | RG_RF24_EDD (0x20F) |
| Address for register RF24_EDD. More... | |
| #define | RG_RF24_EDV (0x210) |
| Address for register RF24_EDV. More... | |
| #define | RG_RF24_IRQM (0x200) |
| Address for register RF24_IRQM. More... | |
| #define | RG_RF24_IRQS (0x01) |
| Address for register RF24_IRQS. More... | |
| #define | RG_RF24_PAC (0x214) |
| Address for register RF24_PAC. More... | |
| #define | RG_RF24_PADFE (0x216) |
| Address for register RF24_PADFE. More... | |
| #define | RG_RF24_PLL (0x221) |
| Address for register RF24_PLL. More... | |
| #define | RG_RF24_PLLCF (0x222) |
| Address for register RF24_PLLCF. More... | |
| #define | RG_RF24_RNDV (0x211) |
| Address for register RF24_RNDV. More... | |
| #define | RG_RF24_RSSI (0x20D) |
| Address for register RF24_RSSI. More... | |
| #define | RG_RF24_RXBWC (0x209) |
| Address for register RF24_RXBWC. More... | |
| #define | RG_RF24_RXDFE (0x20A) |
| Address for register RF24_RXDFE. More... | |
| #define | RG_RF24_STATE (0x202) |
| Address for register RF24_STATE. More... | |
| #define | RG_RF24_TXCI (0x225) |
| Address for register RF24_TXCI. More... | |
| #define | RG_RF24_TXCQ (0x226) |
| Address for register RF24_TXCQ. More... | |
| #define | RG_RF24_TXCUTC (0x212) |
| Address for register RF24_TXCUTC. More... | |
| #define | RG_RF24_TXDACI (0x227) |
| Address for register RF24_TXDACI. More... | |
| #define | RG_RF24_TXDACQ (0x228) |
| Address for register RF24_TXDACQ. More... | |
| #define | RG_RF24_TXDFE (0x213) |
| Address for register RF24_TXDFE. More... | |
| #define | RG_RF_BMDVC (0x08) |
| Address for register RF_BMDVC. More... | |
| #define | RG_RF_CFG (0x06) |
| Address for register RF_CFG. More... | |
| #define | RG_RF_CLKO (0x07) |
| Address for register RF_CLKO. More... | |
| #define | RG_RF_IQIFC0 (0x0A) |
| Address for register RF_IQIFC0. More... | |
| #define | RG_RF_IQIFC1 (0x0B) |
| Address for register RF_IQIFC1. More... | |
| #define | RG_RF_IQIFC2 (0x0C) |
| Address for register RF_IQIFC2. More... | |
| #define | RG_RF_PN (0x0D) |
| Address for register RF_PN. More... | |
| #define | RG_RF_RST (0x05) |
| Address for register RF_RST. More... | |
| #define | RG_RF_VN (0x0E) |
| Address for register RF_VN. More... | |
| #define | RG_RF_XOC (0x09) |
| Address for register RF_XOC. More... | |
| #define | RNDV_RNDV_MASK 0xFF |
| Sub-registers of Register RNDV. More... | |
| #define | RNDV_RNDV_SHIFT 0 |
| Bit Offset for Sub-Register RNDV.RNDV. More... | |
| #define | RSSI_RSSI_MASK 0xFF |
| Sub-registers of Register RSSI. More... | |
| #define | RSSI_RSSI_SHIFT 0 |
| Bit Offset for Sub-Register RSSI.RSSI. More... | |
| #define | RST_CMD_MASK 0x07 |
| Sub-registers of Register RST. More... | |
| #define | RST_CMD_SHIFT 0 |
| Bit Offset for Sub-Register RST.CMD. More... | |
| #define | RST_PULSE_WIDTH_NS (5) |
| Parameter definitions. More... | |
| #define | RXBWC_BW_MASK 0x0F |
| Sub-registers of Register RXBWC. More... | |
| #define | RXBWC_BW_SHIFT 0 |
| Bit Offset for Sub-Register RXBWC.BW. More... | |
| #define | RXBWC_IFI_MASK 0x20 |
| Bit Mask for Sub-Register RXBWC.IFI. More... | |
| #define | RXBWC_IFI_SHIFT 5 |
| Bit Offset for Sub-Register RXBWC.IFI. More... | |
| #define | RXBWC_IFS_MASK 0x10 |
| Bit Mask for Sub-Register RXBWC.IFS. More... | |
| #define | RXBWC_IFS_SHIFT 4 |
| Bit Offset for Sub-Register RXBWC.IFS. More... | |
| #define | RXDFE_RCUT_MASK 0xE0 |
| Bit Mask for Sub-Register RXDFE.RCUT. More... | |
| #define | RXDFE_RCUT_SHIFT 5 |
| Bit Offset for Sub-Register RXDFE.RCUT. More... | |
| #define | RXDFE_SR_MASK 0x0F |
| Sub-registers of Register RXDFE. More... | |
| #define | RXDFE_SR_SHIFT 0 |
| Bit Offset for Sub-Register RXDFE.SR. More... | |
| #define | RXFLH_RXFLH_MASK 0x07 |
| Sub-registers of Register RXFLH. More... | |
| #define | RXFLH_RXFLH_SHIFT 0 |
| Bit Offset for Sub-Register RXFLH.RXFLH. More... | |
| #define | RXFLL_RXFLL_MASK 0xFF |
| Sub-registers of Register RXFLL. More... | |
| #define | RXFLL_RXFLL_SHIFT 0 |
| Bit Offset for Sub-Register RXFLL.RXFLL. More... | |
| #define | SR_BBC0_AFC0_AFEN0 |
| Sub-registers of Register RG_BBC0_AFC0. More... | |
| #define | SR_BBC0_AFC0_AFEN1 |
| Access parameters for sub-register AFEN1 in register RG_BBC0_AFC0. More... | |
| #define | SR_BBC0_AFC0_AFEN2 |
| Access parameters for sub-register AFEN2 in register RG_BBC0_AFC0. More... | |
| #define | SR_BBC0_AFC0_AFEN3 |
| Access parameters for sub-register AFEN3 in register RG_BBC0_AFC0. More... | |
| #define | SR_BBC0_AFC0_PM |
| Access parameters for sub-register PM in register RG_BBC0_AFC0. More... | |
| #define | SR_BBC0_AFC1_MRFT0 |
| Access parameters for sub-register MRFT0 in register RG_BBC0_AFC1. More... | |
| #define | SR_BBC0_AFC1_MRFT1 |
| Access parameters for sub-register MRFT1 in register RG_BBC0_AFC1. More... | |
| #define | SR_BBC0_AFC1_MRFT2 |
| Access parameters for sub-register MRFT2 in register RG_BBC0_AFC1. More... | |
| #define | SR_BBC0_AFC1_MRFT3 |
| Access parameters for sub-register MRFT3 in register RG_BBC0_AFC1. More... | |
| #define | SR_BBC0_AFC1_PANC0 |
| Sub-registers of Register RG_BBC0_AFC1. More... | |
| #define | SR_BBC0_AFC1_PANC1 |
| Access parameters for sub-register PANC1 in register RG_BBC0_AFC1. More... | |
| #define | SR_BBC0_AFC1_PANC2 |
| Access parameters for sub-register PANC2 in register RG_BBC0_AFC1. More... | |
| #define | SR_BBC0_AFC1_PANC3 |
| Access parameters for sub-register PANC3 in register RG_BBC0_AFC1. More... | |
| #define | SR_BBC0_AFFTM_AFFTM |
| Sub-registers of Register RG_BBC0_AFFTM. More... | |
| #define | SR_BBC0_AFFVM_AFFVM |
| Sub-registers of Register RG_BBC0_AFFVM. More... | |
| #define | SR_BBC0_AFS_AM0 RG_BBC0_AFS, AFS_AM0_MASK, AFS_AM0_SHIFT |
| Sub-registers of Register RG_BBC0_AFS. More... | |
| #define | SR_BBC0_AFS_AM1 RG_BBC0_AFS, AFS_AM1_MASK, AFS_AM1_SHIFT |
| Access parameters for sub-register AM1 in register RG_BBC0_AFS. More... | |
| #define | SR_BBC0_AFS_AM2 RG_BBC0_AFS, AFS_AM2_MASK, AFS_AM2_SHIFT |
| Access parameters for sub-register AM2 in register RG_BBC0_AFS. More... | |
| #define | SR_BBC0_AFS_AM3 RG_BBC0_AFS, AFS_AM3_MASK, AFS_AM3_SHIFT |
| Access parameters for sub-register AM3 in register RG_BBC0_AFS. More... | |
| #define | SR_BBC0_AFS_EM RG_BBC0_AFS, AFS_EM_MASK, AFS_EM_SHIFT |
| Access parameters for sub-register EM in register RG_BBC0_AFS. More... | |
| #define | SR_BBC0_AMAACKPD_PD0 |
| Sub-registers of Register RG_BBC0_AMAACKPD. More... | |
| #define | SR_BBC0_AMAACKPD_PD1 |
| Access parameters for sub-register PD1 in register RG_BBC0_AMAACKPD. More... | |
| #define | SR_BBC0_AMAACKPD_PD2 |
| Access parameters for sub-register PD2 in register RG_BBC0_AMAACKPD. More... | |
| #define | SR_BBC0_AMAACKPD_PD3 |
| Access parameters for sub-register PD3 in register RG_BBC0_AMAACKPD. More... | |
| #define | SR_BBC0_AMAACKTH_AMAACKTH |
| Sub-registers of Register RG_BBC0_AMAACKTH. More... | |
| #define | SR_BBC0_AMAACKTL_AMAACKTL |
| Sub-registers of Register RG_BBC0_AMAACKTL. More... | |
| #define | SR_BBC0_AMCS_AACK |
| Access parameters for sub-register AACK in register RG_BBC0_AMCS. More... | |
| #define | SR_BBC0_AMCS_AACKDR |
| Access parameters for sub-register AACKDR in register RG_BBC0_AMCS. More... | |
| #define | SR_BBC0_AMCS_AACKFA |
| Access parameters for sub-register AACKFA in register RG_BBC0_AMCS. More... | |
| #define | SR_BBC0_AMCS_AACKFT |
| Access parameters for sub-register AACKFT in register RG_BBC0_AMCS. More... | |
| #define | SR_BBC0_AMCS_AACKS |
| Access parameters for sub-register AACKS in register RG_BBC0_AMCS. More... | |
| #define | SR_BBC0_AMCS_CCAED |
| Access parameters for sub-register CCAED in register RG_BBC0_AMCS. More... | |
| #define | SR_BBC0_AMCS_CCATX |
| Access parameters for sub-register CCATX in register RG_BBC0_AMCS. More... | |
| #define | SR_BBC0_AMCS_TX2RX |
| Sub-registers of Register RG_BBC0_AMCS. More... | |
| #define | SR_BBC0_AMEDT_AMEDT |
| Sub-registers of Register RG_BBC0_AMEDT. More... | |
| #define | SR_BBC0_CNT0_CNT0 |
| Sub-registers of Register RG_BBC0_CNT0. More... | |
| #define | SR_BBC0_CNT1_CNT1 |
| Sub-registers of Register RG_BBC0_CNT1. More... | |
| #define | SR_BBC0_CNT2_CNT2 |
| Sub-registers of Register RG_BBC0_CNT2. More... | |
| #define | SR_BBC0_CNT3_CNT3 |
| Sub-registers of Register RG_BBC0_CNT3. More... | |
| #define | SR_BBC0_CNTC_CAPRXS |
| Access parameters for sub-register CAPRXS in register RG_BBC0_CNTC. More... | |
| #define | SR_BBC0_CNTC_CAPTXS |
| Access parameters for sub-register CAPTXS in register RG_BBC0_CNTC. More... | |
| #define | SR_BBC0_CNTC_EN |
| Sub-registers of Register RG_BBC0_CNTC. More... | |
| #define | SR_BBC0_CNTC_RSTRXS |
| Access parameters for sub-register RSTRXS in register RG_BBC0_CNTC. More... | |
| #define | SR_BBC0_CNTC_RSTTXS |
| Access parameters for sub-register RSTTXS in register RG_BBC0_CNTC. More... | |
| #define | SR_BBC0_FBLH_FBLH |
| Sub-registers of Register RG_BBC0_FBLH. More... | |
| #define | SR_BBC0_FBLIH_FBLIH |
| Sub-registers of Register RG_BBC0_FBLIH. More... | |
| #define | SR_BBC0_FBLIL_FBLIL |
| Sub-registers of Register RG_BBC0_FBLIL. More... | |
| #define | SR_BBC0_FBLL_FBLL |
| Sub-registers of Register RG_BBC0_FBLL. More... | |
| #define | SR_BBC0_FBRXE_FBRXE |
| Sub-registers of Register RG_BBC0_FBRXE. More... | |
| #define | SR_BBC0_FBRXS_FBRXS |
| Sub-registers of Register RG_BBC0_FBRXS. More... | |
| #define | SR_BBC0_FBTXE_FBTXE |
| Sub-registers of Register RG_BBC0_FBTXE. More... | |
| #define | SR_BBC0_FBTXS_FBTXS |
| Sub-registers of Register RG_BBC0_FBTXS. More... | |
| #define | SR_BBC0_FSKC0_BT |
| Access parameters for sub-register BT in register RG_BBC0_FSKC0. More... | |
| #define | SR_BBC0_FSKC0_MIDX |
| Access parameters for sub-register MIDX in register RG_BBC0_FSKC0. More... | |
| #define | SR_BBC0_FSKC0_MIDXS |
| Access parameters for sub-register MIDXS in register RG_BBC0_FSKC0. More... | |
| #define | SR_BBC0_FSKC0_MORD |
| Sub-registers of Register RG_BBC0_FSKC0. More... | |
| #define | SR_BBC0_FSKC1_FI |
| Access parameters for sub-register FI in register RG_BBC0_FSKC1. More... | |
| #define | SR_BBC0_FSKC1_FSKPLH |
| Access parameters for sub-register FSKPLH in register RG_BBC0_FSKC1. More... | |
| #define | SR_BBC0_FSKC1_SRATE |
| Sub-registers of Register RG_BBC0_FSKC1. More... | |
| #define | SR_BBC0_FSKC2_FECIE |
| Sub-registers of Register RG_BBC0_FSKC2. More... | |
| #define | SR_BBC0_FSKC2_FECS |
| Access parameters for sub-register FECS in register RG_BBC0_FSKC2. More... | |
| #define | SR_BBC0_FSKC2_MSE |
| Access parameters for sub-register MSE in register RG_BBC0_FSKC2. More... | |
| #define | SR_BBC0_FSKC2_PDTM |
| Access parameters for sub-register PDTM in register RG_BBC0_FSKC2. More... | |
| #define | SR_BBC0_FSKC2_PRI |
| Access parameters for sub-register PRI in register RG_BBC0_FSKC2. More... | |
| #define | SR_BBC0_FSKC2_RXO |
| Access parameters for sub-register RXO in register RG_BBC0_FSKC2. More... | |
| #define | SR_BBC0_FSKC2_RXPTO |
| Access parameters for sub-register RXPTO in register RG_BBC0_FSKC2. More... | |
| #define | SR_BBC0_FSKC3_PDT |
| Sub-registers of Register RG_BBC0_FSKC3. More... | |
| #define | SR_BBC0_FSKC3_SFDT |
| Access parameters for sub-register SFDT in register RG_BBC0_FSKC3. More... | |
| #define | SR_BBC0_FSKC4_CSFD0 |
| Sub-registers of Register RG_BBC0_FSKC4. More... | |
| #define | SR_BBC0_FSKC4_CSFD1 |
| Access parameters for sub-register CSFD1 in register RG_BBC0_FSKC4. More... | |
| #define | SR_BBC0_FSKC4_RAWRBIT |
| Access parameters for sub-register RAWRBIT in register RG_BBC0_FSKC4. More... | |
| #define | SR_BBC0_FSKC4_SFD32 |
| Access parameters for sub-register SFD32 in register RG_BBC0_FSKC4. More... | |
| #define | SR_BBC0_FSKC4_SFDQ |
| Access parameters for sub-register SFDQ in register RG_BBC0_FSKC4. More... | |
| #define | SR_BBC0_FSKDM_EN |
| Sub-registers of Register RG_BBC0_FSKDM. More... | |
| #define | SR_BBC0_FSKDM_PE |
| Access parameters for sub-register PE in register RG_BBC0_FSKDM. More... | |
| #define | SR_BBC0_FSKPE0_FSKPE0 |
| Sub-registers of Register RG_BBC0_FSKPE0. More... | |
| #define | SR_BBC0_FSKPE1_FSKPE1 |
| Sub-registers of Register RG_BBC0_FSKPE1. More... | |
| #define | SR_BBC0_FSKPE2_FSKPE2 |
| Sub-registers of Register RG_BBC0_FSKPE2. More... | |
| #define | SR_BBC0_FSKPHRRX_DW |
| Access parameters for sub-register DW in register RG_BBC0_FSKPHRRX. More... | |
| #define | SR_BBC0_FSKPHRRX_FCST |
| Access parameters for sub-register FCST in register RG_BBC0_FSKPHRRX. More... | |
| #define | SR_BBC0_FSKPHRRX_MS |
| Access parameters for sub-register MS in register RG_BBC0_FSKPHRRX. More... | |
| #define | SR_BBC0_FSKPHRRX_RB1 |
| Sub-registers of Register RG_BBC0_FSKPHRRX. More... | |
| #define | SR_BBC0_FSKPHRRX_RB2 |
| Access parameters for sub-register RB2 in register RG_BBC0_FSKPHRRX. More... | |
| #define | SR_BBC0_FSKPHRRX_SFD |
| Access parameters for sub-register SFD in register RG_BBC0_FSKPHRRX. More... | |
| #define | SR_BBC0_FSKPHRTX_DW |
| Access parameters for sub-register DW in register RG_BBC0_FSKPHRTX. More... | |
| #define | SR_BBC0_FSKPHRTX_RB1 |
| Sub-registers of Register RG_BBC0_FSKPHRTX. More... | |
| #define | SR_BBC0_FSKPHRTX_RB2 |
| Access parameters for sub-register RB2 in register RG_BBC0_FSKPHRTX. More... | |
| #define | SR_BBC0_FSKPHRTX_SFD |
| Access parameters for sub-register SFD in register RG_BBC0_FSKPHRTX. More... | |
| #define | SR_BBC0_FSKPLL_FSKPLL |
| Sub-registers of Register RG_BBC0_FSKPLL. More... | |
| #define | SR_BBC0_FSKRPC_BASET |
| Sub-registers of Register RG_BBC0_FSKRPC. More... | |
| #define | SR_BBC0_FSKRPC_EN |
| Access parameters for sub-register EN in register RG_BBC0_FSKRPC. More... | |
| #define | SR_BBC0_FSKRPCOFFT_FSKRPCOFFT |
| Sub-registers of Register RG_BBC0_FSKRPCOFFT. More... | |
| #define | SR_BBC0_FSKRPCONT_FSKRPCONT |
| Sub-registers of Register RG_BBC0_FSKRPCONT. More... | |
| #define | SR_BBC0_FSKRRXFLH_FSKRRXFLH |
| Sub-registers of Register RG_BBC0_FSKRRXFLH. More... | |
| #define | SR_BBC0_FSKRRXFLL_FSKRRXFLL |
| Sub-registers of Register RG_BBC0_FSKRRXFLL. More... | |
| #define | SR_BBC0_FSKSFD0H_FSKSFD0H |
| Sub-registers of Register RG_BBC0_FSKSFD0H. More... | |
| #define | SR_BBC0_FSKSFD0L_FSKSFD0L |
| Sub-registers of Register RG_BBC0_FSKSFD0L. More... | |
| #define | SR_BBC0_FSKSFD1H_FSKSFD1H |
| Sub-registers of Register RG_BBC0_FSKSFD1H. More... | |
| #define | SR_BBC0_FSKSFD1L_FSKSFD1L |
| Sub-registers of Register RG_BBC0_FSKSFD1L. More... | |
| #define | SR_BBC0_IRQM_AGCH |
| Access parameters for sub-register AGCH in register RG_BBC0_IRQM. More... | |
| #define | SR_BBC0_IRQM_AGCR |
| Access parameters for sub-register AGCR in register RG_BBC0_IRQM. More... | |
| #define | SR_BBC0_IRQM_FBLI |
| Access parameters for sub-register FBLI in register RG_BBC0_IRQM. More... | |
| #define | SR_BBC0_IRQM_RXAM |
| Access parameters for sub-register RXAM in register RG_BBC0_IRQM. More... | |
| #define | SR_BBC0_IRQM_RXEM |
| Access parameters for sub-register RXEM in register RG_BBC0_IRQM. More... | |
| #define | SR_BBC0_IRQM_RXFE |
| Access parameters for sub-register RXFE in register RG_BBC0_IRQM. More... | |
| #define | SR_BBC0_IRQM_RXFS |
| Sub-registers of Register RG_BBC0_IRQM. More... | |
| #define | SR_BBC0_IRQM_TXFE |
| Access parameters for sub-register TXFE in register RG_BBC0_IRQM. More... | |
| #define | SR_BBC0_IRQS_AGCH |
| Access parameters for sub-register AGCH in register RG_BBC0_IRQS. More... | |
| #define | SR_BBC0_IRQS_AGCR |
| Access parameters for sub-register AGCR in register RG_BBC0_IRQS. More... | |
| #define | SR_BBC0_IRQS_FBLI |
| Access parameters for sub-register FBLI in register RG_BBC0_IRQS. More... | |
| #define | SR_BBC0_IRQS_RXAM |
| Access parameters for sub-register RXAM in register RG_BBC0_IRQS. More... | |
| #define | SR_BBC0_IRQS_RXEM |
| Access parameters for sub-register RXEM in register RG_BBC0_IRQS. More... | |
| #define | SR_BBC0_IRQS_RXFE |
| Access parameters for sub-register RXFE in register RG_BBC0_IRQS. More... | |
| #define | SR_BBC0_IRQS_RXFS |
| Sub-registers of Register RG_BBC0_IRQS. More... | |
| #define | SR_BBC0_IRQS_TXFE |
| Access parameters for sub-register TXFE in register RG_BBC0_IRQS. More... | |
| #define | SR_BBC0_MACEA0_MACEA0 |
| Sub-registers of Register RG_BBC0_MACEA0. More... | |
| #define | SR_BBC0_MACEA1_MACEA1 |
| Sub-registers of Register RG_BBC0_MACEA1. More... | |
| #define | SR_BBC0_MACEA2_MACEA2 |
| Sub-registers of Register RG_BBC0_MACEA2. More... | |
| #define | SR_BBC0_MACEA3_MACEA3 |
| Sub-registers of Register RG_BBC0_MACEA3. More... | |
| #define | SR_BBC0_MACEA4_MACEA4 |
| Sub-registers of Register RG_BBC0_MACEA4. More... | |
| #define | SR_BBC0_MACEA5_MACEA5 |
| Sub-registers of Register RG_BBC0_MACEA5. More... | |
| #define | SR_BBC0_MACEA6_MACEA6 |
| Sub-registers of Register RG_BBC0_MACEA6. More... | |
| #define | SR_BBC0_MACEA7_MACEA7 |
| Sub-registers of Register RG_BBC0_MACEA7. More... | |
| #define | SR_BBC0_MACPID0F0_MACPID0F0 |
| Sub-registers of Register RG_BBC0_MACPID0F0. More... | |
| #define | SR_BBC0_MACPID0F1_MACPID0F1 |
| Sub-registers of Register RG_BBC0_MACPID0F1. More... | |
| #define | SR_BBC0_MACPID0F2_MACPID0F2 |
| Sub-registers of Register RG_BBC0_MACPID0F2. More... | |
| #define | SR_BBC0_MACPID0F3_MACPID0F3 |
| Sub-registers of Register RG_BBC0_MACPID0F3. More... | |
| #define | SR_BBC0_MACPID1F0_MACPID1F0 |
| Sub-registers of Register RG_BBC0_MACPID1F0. More... | |
| #define | SR_BBC0_MACPID1F1_MACPID1F1 |
| Sub-registers of Register RG_BBC0_MACPID1F1. More... | |
| #define | SR_BBC0_MACPID1F2_MACPID1F2 |
| Sub-registers of Register RG_BBC0_MACPID1F2. More... | |
| #define | SR_BBC0_MACPID1F3_MACPID1F3 |
| Sub-registers of Register RG_BBC0_MACPID1F3. More... | |
| #define | SR_BBC0_MACSHA0F0_MACSHA0F0 |
| Sub-registers of Register RG_BBC0_MACSHA0F0. More... | |
| #define | SR_BBC0_MACSHA0F1_MACSHA0F1 |
| Sub-registers of Register RG_BBC0_MACSHA0F1. More... | |
| #define | SR_BBC0_MACSHA0F2_MACSHA0F2 |
| Sub-registers of Register RG_BBC0_MACSHA0F2. More... | |
| #define | SR_BBC0_MACSHA0F3_MACSHA0F3 |
| Sub-registers of Register RG_BBC0_MACSHA0F3. More... | |
| #define | SR_BBC0_MACSHA1F0_MACSHA1F0 |
| Sub-registers of Register RG_BBC0_MACSHA1F0. More... | |
| #define | SR_BBC0_MACSHA1F1_MACSHA1F1 |
| Sub-registers of Register RG_BBC0_MACSHA1F1. More... | |
| #define | SR_BBC0_MACSHA1F2_MACSHA1F2 |
| Sub-registers of Register RG_BBC0_MACSHA1F2. More... | |
| #define | SR_BBC0_MACSHA1F3_MACSHA1F3 |
| Sub-registers of Register RG_BBC0_MACSHA1F3. More... | |
| #define | SR_BBC0_OFDMC_LFO |
| Access parameters for sub-register LFO in register RG_BBC0_OFDMC. More... | |
| #define | SR_BBC0_OFDMC_OPT |
| Sub-registers of Register RG_BBC0_OFDMC. More... | |
| #define | SR_BBC0_OFDMC_POI |
| Access parameters for sub-register POI in register RG_BBC0_OFDMC. More... | |
| #define | SR_BBC0_OFDMC_SSRX |
| Access parameters for sub-register SSRX in register RG_BBC0_OFDMC. More... | |
| #define | SR_BBC0_OFDMC_SSTX |
| Access parameters for sub-register SSTX in register RG_BBC0_OFDMC. More... | |
| #define | SR_BBC0_OFDMPHRRX_MCS |
| Sub-registers of Register RG_BBC0_OFDMPHRRX. More... | |
| #define | SR_BBC0_OFDMPHRRX_RB17 |
| Access parameters for sub-register RB17 in register RG_BBC0_OFDMPHRRX. More... | |
| #define | SR_BBC0_OFDMPHRRX_RB18 |
| Access parameters for sub-register RB18 in register RG_BBC0_OFDMPHRRX. More... | |
| #define | SR_BBC0_OFDMPHRRX_RB21 |
| Access parameters for sub-register RB21 in register RG_BBC0_OFDMPHRRX. More... | |
| #define | SR_BBC0_OFDMPHRRX_RB5 |
| Access parameters for sub-register RB5 in register RG_BBC0_OFDMPHRRX. More... | |
| #define | SR_BBC0_OFDMPHRRX_SPC |
| Access parameters for sub-register SPC in register RG_BBC0_OFDMPHRRX. More... | |
| #define | SR_BBC0_OFDMPHRTX_MCS |
| Sub-registers of Register RG_BBC0_OFDMPHRTX. More... | |
| #define | SR_BBC0_OFDMPHRTX_RB17 |
| Access parameters for sub-register RB17 in register RG_BBC0_OFDMPHRTX. More... | |
| #define | SR_BBC0_OFDMPHRTX_RB18 |
| Access parameters for sub-register RB18 in register RG_BBC0_OFDMPHRTX. More... | |
| #define | SR_BBC0_OFDMPHRTX_RB21 |
| Access parameters for sub-register RB21 in register RG_BBC0_OFDMPHRTX. More... | |
| #define | SR_BBC0_OFDMPHRTX_RB5 |
| Access parameters for sub-register RB5 in register RG_BBC0_OFDMPHRTX. More... | |
| #define | SR_BBC0_OFDMSW_PDT |
| Access parameters for sub-register PDT in register RG_BBC0_OFDMSW. More... | |
| #define | SR_BBC0_OFDMSW_RXO |
| Sub-registers of Register RG_BBC0_OFDMSW. More... | |
| #define | SR_BBC0_OQPSKC0_DM |
| Access parameters for sub-register DM in register RG_BBC0_OQPSKC0. More... | |
| #define | SR_BBC0_OQPSKC0_FCHIP |
| Sub-registers of Register RG_BBC0_OQPSKC0. More... | |
| #define | SR_BBC0_OQPSKC0_MOD |
| Access parameters for sub-register MOD in register RG_BBC0_OQPSKC0. More... | |
| #define | SR_BBC0_OQPSKC1_PDT0 |
| Sub-registers of Register RG_BBC0_OQPSKC1. More... | |
| #define | SR_BBC0_OQPSKC1_PDT1 |
| Access parameters for sub-register PDT1 in register RG_BBC0_OQPSKC1. More... | |
| #define | SR_BBC0_OQPSKC1_RXO |
| Access parameters for sub-register RXO in register RG_BBC0_OQPSKC1. More... | |
| #define | SR_BBC0_OQPSKC1_RXOLEG |
| Access parameters for sub-register RXOLEG in register RG_BBC0_OQPSKC1. More... | |
| #define | SR_BBC0_OQPSKC2_ENPROP |
| Access parameters for sub-register ENPROP in register RG_BBC0_OQPSKC2. More... | |
| #define | SR_BBC0_OQPSKC2_FCSTLEG |
| Access parameters for sub-register FCSTLEG in register RG_BBC0_OQPSKC2. More... | |
| #define | SR_BBC0_OQPSKC2_RPC |
| Access parameters for sub-register RPC in register RG_BBC0_OQPSKC2. More... | |
| #define | SR_BBC0_OQPSKC2_RXM |
| Sub-registers of Register RG_BBC0_OQPSKC2. More... | |
| #define | SR_BBC0_OQPSKC2_SPC |
| Access parameters for sub-register SPC in register RG_BBC0_OQPSKC2. More... | |
| #define | SR_BBC0_OQPSKC3_HRLEG |
| Access parameters for sub-register HRLEG in register RG_BBC0_OQPSKC3. More... | |
| #define | SR_BBC0_OQPSKC3_NSFD |
| Sub-registers of Register RG_BBC0_OQPSKC3. More... | |
| #define | SR_BBC0_OQPSKPHRRX_LEG |
| Sub-registers of Register RG_BBC0_OQPSKPHRRX. More... | |
| #define | SR_BBC0_OQPSKPHRRX_MOD |
| Access parameters for sub-register MOD in register RG_BBC0_OQPSKPHRRX. More... | |
| #define | SR_BBC0_OQPSKPHRRX_PPDUT |
| Access parameters for sub-register PPDUT in register RG_BBC0_OQPSKPHRRX. More... | |
| #define | SR_BBC0_OQPSKPHRRX_RB0 |
| Access parameters for sub-register RB0 in register RG_BBC0_OQPSKPHRRX. More... | |
| #define | SR_BBC0_OQPSKPHRTX_LEG |
| Sub-registers of Register RG_BBC0_OQPSKPHRTX. More... | |
| #define | SR_BBC0_OQPSKPHRTX_MOD |
| Access parameters for sub-register MOD in register RG_BBC0_OQPSKPHRTX. More... | |
| #define | SR_BBC0_OQPSKPHRTX_PPDUT |
| Access parameters for sub-register PPDUT in register RG_BBC0_OQPSKPHRTX. More... | |
| #define | SR_BBC0_OQPSKPHRTX_RB0 |
| Access parameters for sub-register RB0 in register RG_BBC0_OQPSKPHRTX. More... | |
| #define | SR_BBC0_PC_BBEN RG_BBC0_PC, PC_BBEN_MASK, PC_BBEN_SHIFT |
| Access parameters for sub-register BBEN in register RG_BBC0_PC. More... | |
| #define | SR_BBC0_PC_CTX RG_BBC0_PC, PC_CTX_MASK, PC_CTX_SHIFT |
| Access parameters for sub-register CTX in register RG_BBC0_PC. More... | |
| #define | SR_BBC0_PC_FCSFE |
| Access parameters for sub-register FCSFE in register RG_BBC0_PC. More... | |
| #define | SR_BBC0_PC_FCSOK |
| Access parameters for sub-register FCSOK in register RG_BBC0_PC. More... | |
| #define | SR_BBC0_PC_FCST RG_BBC0_PC, PC_FCST_MASK, PC_FCST_SHIFT |
| Access parameters for sub-register FCST in register RG_BBC0_PC. More... | |
| #define | SR_BBC0_PC_PT RG_BBC0_PC, PC_PT_MASK, PC_PT_SHIFT |
| Sub-registers of Register RG_BBC0_PC. More... | |
| #define | SR_BBC0_PC_TXAFCS |
| Access parameters for sub-register TXAFCS in register RG_BBC0_PC. More... | |
| #define | SR_BBC0_PMUC_AVG |
| Access parameters for sub-register AVG in register RG_BBC0_PMUC. More... | |
| #define | SR_BBC0_PMUC_CCFTS |
| Access parameters for sub-register CCFTS in register RG_BBC0_PMUC. More... | |
| #define | SR_BBC0_PMUC_EN |
| Sub-registers of Register RG_BBC0_PMUC. More... | |
| #define | SR_BBC0_PMUC_FED |
| Access parameters for sub-register FED in register RG_BBC0_PMUC. More... | |
| #define | SR_BBC0_PMUC_IQSEL |
| Access parameters for sub-register IQSEL in register RG_BBC0_PMUC. More... | |
| #define | SR_BBC0_PMUC_SYNC |
| Access parameters for sub-register SYNC in register RG_BBC0_PMUC. More... | |
| #define | SR_BBC0_PMUI_PMUI |
| Sub-registers of Register RG_BBC0_PMUI. More... | |
| #define | SR_BBC0_PMUQ_PMUQ |
| Sub-registers of Register RG_BBC0_PMUQ. More... | |
| #define | SR_BBC0_PMUQF_PMUQF |
| Sub-registers of Register RG_BBC0_PMUQF. More... | |
| #define | SR_BBC0_PMUVAL_PMUVAL |
| Sub-registers of Register RG_BBC0_PMUVAL. More... | |
| #define | SR_BBC0_PS_TXUR RG_BBC0_PS, PS_TXUR_MASK, PS_TXUR_SHIFT |
| Sub-registers of Register RG_BBC0_PS. More... | |
| #define | SR_BBC0_RXFLH_RXFLH |
| Sub-registers of Register RG_BBC0_RXFLH. More... | |
| #define | SR_BBC0_RXFLL_RXFLL |
| Sub-registers of Register RG_BBC0_RXFLL. More... | |
| #define | SR_BBC0_TXFLH_TXFLH |
| Sub-registers of Register RG_BBC0_TXFLH. More... | |
| #define | SR_BBC0_TXFLL_TXFLL |
| Sub-registers of Register RG_BBC0_TXFLL. More... | |
| #define | SR_BBC1_AFC0_AFEN0 |
| Sub-registers of Register RG_BBC1_AFC0. More... | |
| #define | SR_BBC1_AFC0_AFEN1 |
| Access parameters for sub-register AFEN1 in register RG_BBC1_AFC0. More... | |
| #define | SR_BBC1_AFC0_AFEN2 |
| Access parameters for sub-register AFEN2 in register RG_BBC1_AFC0. More... | |
| #define | SR_BBC1_AFC0_AFEN3 |
| Access parameters for sub-register AFEN3 in register RG_BBC1_AFC0. More... | |
| #define | SR_BBC1_AFC0_PM |
| Access parameters for sub-register PM in register RG_BBC1_AFC0. More... | |
| #define | SR_BBC1_AFC1_MRFT0 |
| Access parameters for sub-register MRFT0 in register RG_BBC1_AFC1. More... | |
| #define | SR_BBC1_AFC1_MRFT1 |
| Access parameters for sub-register MRFT1 in register RG_BBC1_AFC1. More... | |
| #define | SR_BBC1_AFC1_MRFT2 |
| Access parameters for sub-register MRFT2 in register RG_BBC1_AFC1. More... | |
| #define | SR_BBC1_AFC1_MRFT3 |
| Access parameters for sub-register MRFT3 in register RG_BBC1_AFC1. More... | |
| #define | SR_BBC1_AFC1_PANC0 |
| Sub-registers of Register RG_BBC1_AFC1. More... | |
| #define | SR_BBC1_AFC1_PANC1 |
| Access parameters for sub-register PANC1 in register RG_BBC1_AFC1. More... | |
| #define | SR_BBC1_AFC1_PANC2 |
| Access parameters for sub-register PANC2 in register RG_BBC1_AFC1. More... | |
| #define | SR_BBC1_AFC1_PANC3 |
| Access parameters for sub-register PANC3 in register RG_BBC1_AFC1. More... | |
| #define | SR_BBC1_AFFTM_AFFTM |
| Sub-registers of Register RG_BBC1_AFFTM. More... | |
| #define | SR_BBC1_AFFVM_AFFVM |
| Sub-registers of Register RG_BBC1_AFFVM. More... | |
| #define | SR_BBC1_AFS_AM0 RG_BBC1_AFS, AFS_AM0_MASK, AFS_AM0_SHIFT |
| Sub-registers of Register RG_BBC1_AFS. More... | |
| #define | SR_BBC1_AFS_AM1 RG_BBC1_AFS, AFS_AM1_MASK, AFS_AM1_SHIFT |
| Access parameters for sub-register AM1 in register RG_BBC1_AFS. More... | |
| #define | SR_BBC1_AFS_AM2 RG_BBC1_AFS, AFS_AM2_MASK, AFS_AM2_SHIFT |
| Access parameters for sub-register AM2 in register RG_BBC1_AFS. More... | |
| #define | SR_BBC1_AFS_AM3 RG_BBC1_AFS, AFS_AM3_MASK, AFS_AM3_SHIFT |
| Access parameters for sub-register AM3 in register RG_BBC1_AFS. More... | |
| #define | SR_BBC1_AFS_EM RG_BBC1_AFS, AFS_EM_MASK, AFS_EM_SHIFT |
| Access parameters for sub-register EM in register RG_BBC1_AFS. More... | |
| #define | SR_BBC1_AMAACKPD_PD0 |
| Sub-registers of Register RG_BBC1_AMAACKPD. More... | |
| #define | SR_BBC1_AMAACKPD_PD1 |
| Access parameters for sub-register PD1 in register RG_BBC1_AMAACKPD. More... | |
| #define | SR_BBC1_AMAACKPD_PD2 |
| Access parameters for sub-register PD2 in register RG_BBC1_AMAACKPD. More... | |
| #define | SR_BBC1_AMAACKPD_PD3 |
| Access parameters for sub-register PD3 in register RG_BBC1_AMAACKPD. More... | |
| #define | SR_BBC1_AMAACKTH_AMAACKTH |
| Sub-registers of Register RG_BBC1_AMAACKTH. More... | |
| #define | SR_BBC1_AMAACKTL_AMAACKTL |
| Sub-registers of Register RG_BBC1_AMAACKTL. More... | |
| #define | SR_BBC1_AMCS_AACK |
| Access parameters for sub-register AACK in register RG_BBC1_AMCS. More... | |
| #define | SR_BBC1_AMCS_AACKDR |
| Access parameters for sub-register AACKDR in register RG_BBC1_AMCS. More... | |
| #define | SR_BBC1_AMCS_AACKFA |
| Access parameters for sub-register AACKFA in register RG_BBC1_AMCS. More... | |
| #define | SR_BBC1_AMCS_AACKFT |
| Access parameters for sub-register AACKFT in register RG_BBC1_AMCS. More... | |
| #define | SR_BBC1_AMCS_AACKS |
| Access parameters for sub-register AACKS in register RG_BBC1_AMCS. More... | |
| #define | SR_BBC1_AMCS_CCAED |
| Access parameters for sub-register CCAED in register RG_BBC1_AMCS. More... | |
| #define | SR_BBC1_AMCS_CCATX |
| Access parameters for sub-register CCATX in register RG_BBC1_AMCS. More... | |
| #define | SR_BBC1_AMCS_TX2RX |
| Sub-registers of Register RG_BBC1_AMCS. More... | |
| #define | SR_BBC1_AMEDT_AMEDT |
| Sub-registers of Register RG_BBC1_AMEDT. More... | |
| #define | SR_BBC1_CNT0_CNT0 |
| Sub-registers of Register RG_BBC1_CNT0. More... | |
| #define | SR_BBC1_CNT1_CNT1 |
| Sub-registers of Register RG_BBC1_CNT1. More... | |
| #define | SR_BBC1_CNT2_CNT2 |
| Sub-registers of Register RG_BBC1_CNT2. More... | |
| #define | SR_BBC1_CNT3_CNT3 |
| Sub-registers of Register RG_BBC1_CNT3. More... | |
| #define | SR_BBC1_CNTC_CAPRXS |
| Access parameters for sub-register CAPRXS in register RG_BBC1_CNTC. More... | |
| #define | SR_BBC1_CNTC_CAPTXS |
| Access parameters for sub-register CAPTXS in register RG_BBC1_CNTC. More... | |
| #define | SR_BBC1_CNTC_EN |
| Sub-registers of Register RG_BBC1_CNTC. More... | |
| #define | SR_BBC1_CNTC_RSTRXS |
| Access parameters for sub-register RSTRXS in register RG_BBC1_CNTC. More... | |
| #define | SR_BBC1_CNTC_RSTTXS |
| Access parameters for sub-register RSTTXS in register RG_BBC1_CNTC. More... | |
| #define | SR_BBC1_FBLH_FBLH |
| Sub-registers of Register RG_BBC1_FBLH. More... | |
| #define | SR_BBC1_FBLIH_FBLIH |
| Sub-registers of Register RG_BBC1_FBLIH. More... | |
| #define | SR_BBC1_FBLIL_FBLIL |
| Sub-registers of Register RG_BBC1_FBLIL. More... | |
| #define | SR_BBC1_FBLL_FBLL |
| Sub-registers of Register RG_BBC1_FBLL. More... | |
| #define | SR_BBC1_FBRXE_FBRXE |
| Sub-registers of Register RG_BBC1_FBRXE. More... | |
| #define | SR_BBC1_FBRXS_FBRXS |
| Sub-registers of Register RG_BBC1_FBRXS. More... | |
| #define | SR_BBC1_FBTXE_FBTXE |
| Sub-registers of Register RG_BBC1_FBTXE. More... | |
| #define | SR_BBC1_FBTXS_FBTXS |
| Sub-registers of Register RG_BBC1_FBTXS. More... | |
| #define | SR_BBC1_FSKC0_BT |
| Access parameters for sub-register BT in register RG_BBC1_FSKC0. More... | |
| #define | SR_BBC1_FSKC0_MIDX |
| Access parameters for sub-register MIDX in register RG_BBC1_FSKC0. More... | |
| #define | SR_BBC1_FSKC0_MIDXS |
| Access parameters for sub-register MIDXS in register RG_BBC1_FSKC0. More... | |
| #define | SR_BBC1_FSKC0_MORD |
| Sub-registers of Register RG_BBC1_FSKC0. More... | |
| #define | SR_BBC1_FSKC1_FI |
| Access parameters for sub-register FI in register RG_BBC1_FSKC1. More... | |
| #define | SR_BBC1_FSKC1_FSKPLH |
| Access parameters for sub-register FSKPLH in register RG_BBC1_FSKC1. More... | |
| #define | SR_BBC1_FSKC1_SRATE |
| Sub-registers of Register RG_BBC1_FSKC1. More... | |
| #define | SR_BBC1_FSKC2_FECIE |
| Sub-registers of Register RG_BBC1_FSKC2. More... | |
| #define | SR_BBC1_FSKC2_FECS |
| Access parameters for sub-register FECS in register RG_BBC1_FSKC2. More... | |
| #define | SR_BBC1_FSKC2_MSE |
| Access parameters for sub-register MSE in register RG_BBC1_FSKC2. More... | |
| #define | SR_BBC1_FSKC2_PDTM |
| Access parameters for sub-register PDTM in register RG_BBC1_FSKC2. More... | |
| #define | SR_BBC1_FSKC2_PRI |
| Access parameters for sub-register PRI in register RG_BBC1_FSKC2. More... | |
| #define | SR_BBC1_FSKC2_RXO |
| Access parameters for sub-register RXO in register RG_BBC1_FSKC2. More... | |
| #define | SR_BBC1_FSKC2_RXPTO |
| Access parameters for sub-register RXPTO in register RG_BBC1_FSKC2. More... | |
| #define | SR_BBC1_FSKC3_PDT |
| Sub-registers of Register RG_BBC1_FSKC3. More... | |
| #define | SR_BBC1_FSKC3_SFDT |
| Access parameters for sub-register SFDT in register RG_BBC1_FSKC3. More... | |
| #define | SR_BBC1_FSKC4_CSFD0 |
| Sub-registers of Register RG_BBC1_FSKC4. More... | |
| #define | SR_BBC1_FSKC4_CSFD1 |
| Access parameters for sub-register CSFD1 in register RG_BBC1_FSKC4. More... | |
| #define | SR_BBC1_FSKC4_RAWRBIT |
| Access parameters for sub-register RAWRBIT in register RG_BBC1_FSKC4. More... | |
| #define | SR_BBC1_FSKC4_SFD32 |
| Access parameters for sub-register SFD32 in register RG_BBC1_FSKC4. More... | |
| #define | SR_BBC1_FSKC4_SFDQ |
| Access parameters for sub-register SFDQ in register RG_BBC1_FSKC4. More... | |
| #define | SR_BBC1_FSKDM_EN |
| Sub-registers of Register RG_BBC1_FSKDM. More... | |
| #define | SR_BBC1_FSKDM_PE |
| Access parameters for sub-register PE in register RG_BBC1_FSKDM. More... | |
| #define | SR_BBC1_FSKPE0_FSKPE0 |
| Sub-registers of Register RG_BBC1_FSKPE0. More... | |
| #define | SR_BBC1_FSKPE1_FSKPE1 |
| Sub-registers of Register RG_BBC1_FSKPE1. More... | |
| #define | SR_BBC1_FSKPE2_FSKPE2 |
| Sub-registers of Register RG_BBC1_FSKPE2. More... | |
| #define | SR_BBC1_FSKPHRRX_DW |
| Access parameters for sub-register DW in register RG_BBC1_FSKPHRRX. More... | |
| #define | SR_BBC1_FSKPHRRX_FCST |
| Access parameters for sub-register FCST in register RG_BBC1_FSKPHRRX. More... | |
| #define | SR_BBC1_FSKPHRRX_MS |
| Access parameters for sub-register MS in register RG_BBC1_FSKPHRRX. More... | |
| #define | SR_BBC1_FSKPHRRX_RB1 |
| Sub-registers of Register RG_BBC1_FSKPHRRX. More... | |
| #define | SR_BBC1_FSKPHRRX_RB2 |
| Access parameters for sub-register RB2 in register RG_BBC1_FSKPHRRX. More... | |
| #define | SR_BBC1_FSKPHRRX_SFD |
| Access parameters for sub-register SFD in register RG_BBC1_FSKPHRRX. More... | |
| #define | SR_BBC1_FSKPHRTX_DW |
| Access parameters for sub-register DW in register RG_BBC1_FSKPHRTX. More... | |
| #define | SR_BBC1_FSKPHRTX_RB1 |
| Sub-registers of Register RG_BBC1_FSKPHRTX. More... | |
| #define | SR_BBC1_FSKPHRTX_RB2 |
| Access parameters for sub-register RB2 in register RG_BBC1_FSKPHRTX. More... | |
| #define | SR_BBC1_FSKPHRTX_SFD |
| Access parameters for sub-register SFD in register RG_BBC1_FSKPHRTX. More... | |
| #define | SR_BBC1_FSKPLL_FSKPLL |
| Sub-registers of Register RG_BBC1_FSKPLL. More... | |
| #define | SR_BBC1_FSKRPC_BASET |
| Sub-registers of Register RG_BBC1_FSKRPC. More... | |
| #define | SR_BBC1_FSKRPC_EN |
| Access parameters for sub-register EN in register RG_BBC1_FSKRPC. More... | |
| #define | SR_BBC1_FSKRPCOFFT_FSKRPCOFFT |
| Sub-registers of Register RG_BBC1_FSKRPCOFFT. More... | |
| #define | SR_BBC1_FSKRPCONT_FSKRPCONT |
| Sub-registers of Register RG_BBC1_FSKRPCONT. More... | |
| #define | SR_BBC1_FSKRRXFLH_FSKRRXFLH |
| Sub-registers of Register RG_BBC1_FSKRRXFLH. More... | |
| #define | SR_BBC1_FSKRRXFLL_FSKRRXFLL |
| Sub-registers of Register RG_BBC1_FSKRRXFLL. More... | |
| #define | SR_BBC1_FSKSFD0H_FSKSFD0H |
| Sub-registers of Register RG_BBC1_FSKSFD0H. More... | |
| #define | SR_BBC1_FSKSFD0L_FSKSFD0L |
| Sub-registers of Register RG_BBC1_FSKSFD0L. More... | |
| #define | SR_BBC1_FSKSFD1H_FSKSFD1H |
| Sub-registers of Register RG_BBC1_FSKSFD1H. More... | |
| #define | SR_BBC1_FSKSFD1L_FSKSFD1L |
| Sub-registers of Register RG_BBC1_FSKSFD1L. More... | |
| #define | SR_BBC1_IRQM_AGCH |
| Access parameters for sub-register AGCH in register RG_BBC1_IRQM. More... | |
| #define | SR_BBC1_IRQM_AGCR |
| Access parameters for sub-register AGCR in register RG_BBC1_IRQM. More... | |
| #define | SR_BBC1_IRQM_FBLI |
| Access parameters for sub-register FBLI in register RG_BBC1_IRQM. More... | |
| #define | SR_BBC1_IRQM_RXAM |
| Access parameters for sub-register RXAM in register RG_BBC1_IRQM. More... | |
| #define | SR_BBC1_IRQM_RXEM |
| Access parameters for sub-register RXEM in register RG_BBC1_IRQM. More... | |
| #define | SR_BBC1_IRQM_RXFE |
| Access parameters for sub-register RXFE in register RG_BBC1_IRQM. More... | |
| #define | SR_BBC1_IRQM_RXFS |
| Sub-registers of Register RG_BBC1_IRQM. More... | |
| #define | SR_BBC1_IRQM_TXFE |
| Access parameters for sub-register TXFE in register RG_BBC1_IRQM. More... | |
| #define | SR_BBC1_IRQS_AGCH |
| Access parameters for sub-register AGCH in register RG_BBC1_IRQS. More... | |
| #define | SR_BBC1_IRQS_AGCR |
| Access parameters for sub-register AGCR in register RG_BBC1_IRQS. More... | |
| #define | SR_BBC1_IRQS_FBLI |
| Access parameters for sub-register FBLI in register RG_BBC1_IRQS. More... | |
| #define | SR_BBC1_IRQS_RXAM |
| Access parameters for sub-register RXAM in register RG_BBC1_IRQS. More... | |
| #define | SR_BBC1_IRQS_RXEM |
| Access parameters for sub-register RXEM in register RG_BBC1_IRQS. More... | |
| #define | SR_BBC1_IRQS_RXFE |
| Access parameters for sub-register RXFE in register RG_BBC1_IRQS. More... | |
| #define | SR_BBC1_IRQS_RXFS |
| Sub-registers of Register RG_BBC1_IRQS. More... | |
| #define | SR_BBC1_IRQS_TXFE |
| Access parameters for sub-register TXFE in register RG_BBC1_IRQS. More... | |
| #define | SR_BBC1_MACEA0_MACEA0 |
| Sub-registers of Register RG_BBC1_MACEA0. More... | |
| #define | SR_BBC1_MACEA1_MACEA1 |
| Sub-registers of Register RG_BBC1_MACEA1. More... | |
| #define | SR_BBC1_MACEA2_MACEA2 |
| Sub-registers of Register RG_BBC1_MACEA2. More... | |
| #define | SR_BBC1_MACEA3_MACEA3 |
| Sub-registers of Register RG_BBC1_MACEA3. More... | |
| #define | SR_BBC1_MACEA4_MACEA4 |
| Sub-registers of Register RG_BBC1_MACEA4. More... | |
| #define | SR_BBC1_MACEA5_MACEA5 |
| Sub-registers of Register RG_BBC1_MACEA5. More... | |
| #define | SR_BBC1_MACEA6_MACEA6 |
| Sub-registers of Register RG_BBC1_MACEA6. More... | |
| #define | SR_BBC1_MACEA7_MACEA7 |
| Sub-registers of Register RG_BBC1_MACEA7. More... | |
| #define | SR_BBC1_MACPID0F0_MACPID0F0 |
| Sub-registers of Register RG_BBC1_MACPID0F0. More... | |
| #define | SR_BBC1_MACPID0F1_MACPID0F1 |
| Sub-registers of Register RG_BBC1_MACPID0F1. More... | |
| #define | SR_BBC1_MACPID0F2_MACPID0F2 |
| Sub-registers of Register RG_BBC1_MACPID0F2. More... | |
| #define | SR_BBC1_MACPID0F3_MACPID0F3 |
| Sub-registers of Register RG_BBC1_MACPID0F3. More... | |
| #define | SR_BBC1_MACPID1F0_MACPID1F0 |
| Sub-registers of Register RG_BBC1_MACPID1F0. More... | |
| #define | SR_BBC1_MACPID1F1_MACPID1F1 |
| Sub-registers of Register RG_BBC1_MACPID1F1. More... | |
| #define | SR_BBC1_MACPID1F2_MACPID1F2 |
| Sub-registers of Register RG_BBC1_MACPID1F2. More... | |
| #define | SR_BBC1_MACPID1F3_MACPID1F3 |
| Sub-registers of Register RG_BBC1_MACPID1F3. More... | |
| #define | SR_BBC1_MACSHA0F0_MACSHA0F0 |
| Sub-registers of Register RG_BBC1_MACSHA0F0. More... | |
| #define | SR_BBC1_MACSHA0F1_MACSHA0F1 |
| Sub-registers of Register RG_BBC1_MACSHA0F1. More... | |
| #define | SR_BBC1_MACSHA0F2_MACSHA0F2 |
| Sub-registers of Register RG_BBC1_MACSHA0F2. More... | |
| #define | SR_BBC1_MACSHA0F3_MACSHA0F3 |
| Sub-registers of Register RG_BBC1_MACSHA0F3. More... | |
| #define | SR_BBC1_MACSHA1F0_MACSHA1F0 |
| Sub-registers of Register RG_BBC1_MACSHA1F0. More... | |
| #define | SR_BBC1_MACSHA1F1_MACSHA1F1 |
| Sub-registers of Register RG_BBC1_MACSHA1F1. More... | |
| #define | SR_BBC1_MACSHA1F2_MACSHA1F2 |
| Sub-registers of Register RG_BBC1_MACSHA1F2. More... | |
| #define | SR_BBC1_MACSHA1F3_MACSHA1F3 |
| Sub-registers of Register RG_BBC1_MACSHA1F3. More... | |
| #define | SR_BBC1_OFDMC_LFO |
| Access parameters for sub-register LFO in register RG_BBC1_OFDMC. More... | |
| #define | SR_BBC1_OFDMC_OPT |
| Sub-registers of Register RG_BBC1_OFDMC. More... | |
| #define | SR_BBC1_OFDMC_POI |
| Access parameters for sub-register POI in register RG_BBC1_OFDMC. More... | |
| #define | SR_BBC1_OFDMC_SSRX |
| Access parameters for sub-register SSRX in register RG_BBC1_OFDMC. More... | |
| #define | SR_BBC1_OFDMC_SSTX |
| Access parameters for sub-register SSTX in register RG_BBC1_OFDMC. More... | |
| #define | SR_BBC1_OFDMPHRRX_MCS |
| Sub-registers of Register RG_BBC1_OFDMPHRRX. More... | |
| #define | SR_BBC1_OFDMPHRRX_RB17 |
| Access parameters for sub-register RB17 in register RG_BBC1_OFDMPHRRX. More... | |
| #define | SR_BBC1_OFDMPHRRX_RB18 |
| Access parameters for sub-register RB18 in register RG_BBC1_OFDMPHRRX. More... | |
| #define | SR_BBC1_OFDMPHRRX_RB21 |
| Access parameters for sub-register RB21 in register RG_BBC1_OFDMPHRRX. More... | |
| #define | SR_BBC1_OFDMPHRRX_RB5 |
| Access parameters for sub-register RB5 in register RG_BBC1_OFDMPHRRX. More... | |
| #define | SR_BBC1_OFDMPHRRX_SPC |
| Access parameters for sub-register SPC in register RG_BBC1_OFDMPHRRX. More... | |
| #define | SR_BBC1_OFDMPHRTX_MCS |
| Sub-registers of Register RG_BBC1_OFDMPHRTX. More... | |
| #define | SR_BBC1_OFDMPHRTX_RB17 |
| Access parameters for sub-register RB17 in register RG_BBC1_OFDMPHRTX. More... | |
| #define | SR_BBC1_OFDMPHRTX_RB18 |
| Access parameters for sub-register RB18 in register RG_BBC1_OFDMPHRTX. More... | |
| #define | SR_BBC1_OFDMPHRTX_RB21 |
| Access parameters for sub-register RB21 in register RG_BBC1_OFDMPHRTX. More... | |
| #define | SR_BBC1_OFDMPHRTX_RB5 |
| Access parameters for sub-register RB5 in register RG_BBC1_OFDMPHRTX. More... | |
| #define | SR_BBC1_OFDMSW_PDT |
| Access parameters for sub-register PDT in register RG_BBC1_OFDMSW. More... | |
| #define | SR_BBC1_OFDMSW_RXO |
| Sub-registers of Register RG_BBC1_OFDMSW. More... | |
| #define | SR_BBC1_OQPSKC0_DM |
| Access parameters for sub-register DM in register RG_BBC1_OQPSKC0. More... | |
| #define | SR_BBC1_OQPSKC0_FCHIP |
| Sub-registers of Register RG_BBC1_OQPSKC0. More... | |
| #define | SR_BBC1_OQPSKC0_MOD |
| Access parameters for sub-register MOD in register RG_BBC1_OQPSKC0. More... | |
| #define | SR_BBC1_OQPSKC1_PDT0 |
| Sub-registers of Register RG_BBC1_OQPSKC1. More... | |
| #define | SR_BBC1_OQPSKC1_PDT1 |
| Access parameters for sub-register PDT1 in register RG_BBC1_OQPSKC1. More... | |
| #define | SR_BBC1_OQPSKC1_RXO |
| Access parameters for sub-register RXO in register RG_BBC1_OQPSKC1. More... | |
| #define | SR_BBC1_OQPSKC1_RXOLEG |
| Access parameters for sub-register RXOLEG in register RG_BBC1_OQPSKC1. More... | |
| #define | SR_BBC1_OQPSKC2_ENPROP |
| Access parameters for sub-register ENPROP in register RG_BBC1_OQPSKC2. More... | |
| #define | SR_BBC1_OQPSKC2_FCSTLEG |
| Access parameters for sub-register FCSTLEG in register RG_BBC1_OQPSKC2. More... | |
| #define | SR_BBC1_OQPSKC2_RPC |
| Access parameters for sub-register RPC in register RG_BBC1_OQPSKC2. More... | |
| #define | SR_BBC1_OQPSKC2_RXM |
| Sub-registers of Register RG_BBC1_OQPSKC2. More... | |
| #define | SR_BBC1_OQPSKC2_SPC |
| Access parameters for sub-register SPC in register RG_BBC1_OQPSKC2. More... | |
| #define | SR_BBC1_OQPSKC3_HRLEG |
| Access parameters for sub-register HRLEG in register RG_BBC1_OQPSKC3. More... | |
| #define | SR_BBC1_OQPSKC3_NSFD |
| Sub-registers of Register RG_BBC1_OQPSKC3. More... | |
| #define | SR_BBC1_OQPSKPHRRX_LEG |
| Sub-registers of Register RG_BBC1_OQPSKPHRRX. More... | |
| #define | SR_BBC1_OQPSKPHRRX_MOD |
| Access parameters for sub-register MOD in register RG_BBC1_OQPSKPHRRX. More... | |
| #define | SR_BBC1_OQPSKPHRRX_PPDUT |
| Access parameters for sub-register PPDUT in register RG_BBC1_OQPSKPHRRX. More... | |
| #define | SR_BBC1_OQPSKPHRRX_RB0 |
| Access parameters for sub-register RB0 in register RG_BBC1_OQPSKPHRRX. More... | |
| #define | SR_BBC1_OQPSKPHRTX_LEG |
| Sub-registers of Register RG_BBC1_OQPSKPHRTX. More... | |
| #define | SR_BBC1_OQPSKPHRTX_MOD |
| Access parameters for sub-register MOD in register RG_BBC1_OQPSKPHRTX. More... | |
| #define | SR_BBC1_OQPSKPHRTX_PPDUT |
| Access parameters for sub-register PPDUT in register RG_BBC1_OQPSKPHRTX. More... | |
| #define | SR_BBC1_OQPSKPHRTX_RB0 |
| Access parameters for sub-register RB0 in register RG_BBC1_OQPSKPHRTX. More... | |
| #define | SR_BBC1_PC_BBEN RG_BBC1_PC, PC_BBEN_MASK, PC_BBEN_SHIFT |
| Access parameters for sub-register BBEN in register RG_BBC1_PC. More... | |
| #define | SR_BBC1_PC_CTX RG_BBC1_PC, PC_CTX_MASK, PC_CTX_SHIFT |
| Access parameters for sub-register CTX in register RG_BBC1_PC. More... | |
| #define | SR_BBC1_PC_FCSFE |
| Access parameters for sub-register FCSFE in register RG_BBC1_PC. More... | |
| #define | SR_BBC1_PC_FCSOK |
| Access parameters for sub-register FCSOK in register RG_BBC1_PC. More... | |
| #define | SR_BBC1_PC_FCST RG_BBC1_PC, PC_FCST_MASK, PC_FCST_SHIFT |
| Access parameters for sub-register FCST in register RG_BBC1_PC. More... | |
| #define | SR_BBC1_PC_PT RG_BBC1_PC, PC_PT_MASK, PC_PT_SHIFT |
| Sub-registers of Register RG_BBC1_PC. More... | |
| #define | SR_BBC1_PC_TXAFCS |
| Access parameters for sub-register TXAFCS in register RG_BBC1_PC. More... | |
| #define | SR_BBC1_PMUC_AVG |
| Access parameters for sub-register AVG in register RG_BBC1_PMUC. More... | |
| #define | SR_BBC1_PMUC_CCFTS |
| Access parameters for sub-register CCFTS in register RG_BBC1_PMUC. More... | |
| #define | SR_BBC1_PMUC_EN |
| Sub-registers of Register RG_BBC1_PMUC. More... | |
| #define | SR_BBC1_PMUC_FED |
| Access parameters for sub-register FED in register RG_BBC1_PMUC. More... | |
| #define | SR_BBC1_PMUC_IQSEL |
| Access parameters for sub-register IQSEL in register RG_BBC1_PMUC. More... | |
| #define | SR_BBC1_PMUC_SYNC |
| Access parameters for sub-register SYNC in register RG_BBC1_PMUC. More... | |
| #define | SR_BBC1_PMUI_PMUI |
| Sub-registers of Register RG_BBC1_PMUI. More... | |
| #define | SR_BBC1_PMUQ_PMUQ |
| Sub-registers of Register RG_BBC1_PMUQ. More... | |
| #define | SR_BBC1_PMUQF_PMUQF |
| Sub-registers of Register RG_BBC1_PMUQF. More... | |
| #define | SR_BBC1_PMUVAL_PMUVAL |
| Sub-registers of Register RG_BBC1_PMUVAL. More... | |
| #define | SR_BBC1_PS_TXUR RG_BBC1_PS, PS_TXUR_MASK, PS_TXUR_SHIFT |
| Sub-registers of Register RG_BBC1_PS. More... | |
| #define | SR_BBC1_RXFLH_RXFLH |
| Sub-registers of Register RG_BBC1_RXFLH. More... | |
| #define | SR_BBC1_RXFLL_RXFLL |
| Sub-registers of Register RG_BBC1_RXFLL. More... | |
| #define | SR_BBC1_TXFLH_TXFLH |
| Sub-registers of Register RG_BBC1_TXFLH. More... | |
| #define | SR_BBC1_TXFLL_TXFLL |
| Sub-registers of Register RG_BBC1_TXFLL. More... | |
| #define | SR_RF09_AGCC_AGCI |
| Access parameters for sub-register AGCI in register RG_RF09_AGCC. More... | |
| #define | SR_RF09_AGCC_AVGS |
| Access parameters for sub-register AVGS in register RG_RF09_AGCC. More... | |
| #define | SR_RF09_AGCC_EN |
| Sub-registers of Register RG_RF09_AGCC. More... | |
| #define | SR_RF09_AGCC_FRZC |
| Access parameters for sub-register FRZC in register RG_RF09_AGCC. More... | |
| #define | SR_RF09_AGCC_FRZS |
| Access parameters for sub-register FRZS in register RG_RF09_AGCC. More... | |
| #define | SR_RF09_AGCC_RST |
| Access parameters for sub-register RST in register RG_RF09_AGCC. More... | |
| #define | SR_RF09_AGCS_GCW |
| Sub-registers of Register RG_RF09_AGCS. More... | |
| #define | SR_RF09_AGCS_TGT |
| Access parameters for sub-register TGT in register RG_RF09_AGCS. More... | |
| #define | SR_RF09_AUXS_AGCMAP |
| Access parameters for sub-register AGCMAP in register RG_RF09_AUXS. More... | |
| #define | SR_RF09_AUXS_AVEN |
| Access parameters for sub-register AVEN in register RG_RF09_AUXS. More... | |
| #define | SR_RF09_AUXS_AVEXT |
| Access parameters for sub-register AVEXT in register RG_RF09_AUXS. More... | |
| #define | SR_RF09_AUXS_AVS |
| Access parameters for sub-register AVS in register RG_RF09_AUXS. More... | |
| #define | SR_RF09_AUXS_EXTLNABYP |
| Access parameters for sub-register EXTLNABYP in register RG_RF09_AUXS. More... | |
| #define | SR_RF09_AUXS_PAVC |
| Sub-registers of Register RG_RF09_AUXS. More... | |
| #define | SR_RF09_CCF0H_CCF0H |
| Sub-registers of Register RG_RF09_CCF0H. More... | |
| #define | SR_RF09_CCF0L_CCF0L |
| Sub-registers of Register RG_RF09_CCF0L. More... | |
| #define | SR_RF09_CMD_CMD RG_RF09_CMD, CMD_CMD_MASK, CMD_CMD_SHIFT |
| Sub-registers of Register RG_RF09_CMD. More... | |
| #define | SR_RF09_CNL_CNL RG_RF09_CNL, CNL_CNL_MASK, CNL_CNL_SHIFT |
| Sub-registers of Register RG_RF09_CNL. More... | |
| #define | SR_RF09_CNM_CM RG_RF09_CNM, CNM_CM_MASK, CNM_CM_SHIFT |
| Access parameters for sub-register CM in register RG_RF09_CNM. More... | |
| #define | SR_RF09_CNM_CNH RG_RF09_CNM, CNM_CNH_MASK, CNM_CNH_SHIFT |
| Sub-registers of Register RG_RF09_CNM. More... | |
| #define | SR_RF09_CS_CS RG_RF09_CS, CS_CS_MASK, CS_CS_SHIFT |
| Sub-registers of Register RG_RF09_CS. More... | |
| #define | SR_RF09_EDC_EDM RG_RF09_EDC, EDC_EDM_MASK, EDC_EDM_SHIFT |
| Sub-registers of Register RG_RF09_EDC. More... | |
| #define | SR_RF09_EDD_DF RG_RF09_EDD, EDD_DF_MASK, EDD_DF_SHIFT |
| Access parameters for sub-register DF in register RG_RF09_EDD. More... | |
| #define | SR_RF09_EDD_DTB RG_RF09_EDD, EDD_DTB_MASK, EDD_DTB_SHIFT |
| Sub-registers of Register RG_RF09_EDD. More... | |
| #define | SR_RF09_EDV_EDV RG_RF09_EDV, EDV_EDV_MASK, EDV_EDV_SHIFT |
| Sub-registers of Register RG_RF09_EDV. More... | |
| #define | SR_RF09_IRQM_BATLOW |
| Access parameters for sub-register BATLOW in register RG_RF09_IRQM. More... | |
| #define | SR_RF09_IRQM_EDC |
| Access parameters for sub-register EDC in register RG_RF09_IRQM. More... | |
| #define | SR_RF09_IRQM_IQIFSF |
| Access parameters for sub-register IQIFSF in register RG_RF09_IRQM. More... | |
| #define | SR_RF09_IRQM_TRXERR |
| Access parameters for sub-register TRXERR in register RG_RF09_IRQM. More... | |
| #define | SR_RF09_IRQM_TRXRDY |
| Access parameters for sub-register TRXRDY in register RG_RF09_IRQM. More... | |
| #define | SR_RF09_IRQM_WAKEUP |
| Sub-registers of Register RG_RF09_IRQM. More... | |
| #define | SR_RF09_IRQS_BATLOW |
| Access parameters for sub-register BATLOW in register RG_RF09_IRQS. More... | |
| #define | SR_RF09_IRQS_EDC |
| Access parameters for sub-register EDC in register RG_RF09_IRQS. More... | |
| #define | SR_RF09_IRQS_IQIFSF |
| Access parameters for sub-register IQIFSF in register RG_RF09_IRQS. More... | |
| #define | SR_RF09_IRQS_TRXERR |
| Access parameters for sub-register TRXERR in register RG_RF09_IRQS. More... | |
| #define | SR_RF09_IRQS_TRXRDY |
| Access parameters for sub-register TRXRDY in register RG_RF09_IRQS. More... | |
| #define | SR_RF09_IRQS_WAKEUP |
| Sub-registers of Register RG_RF09_IRQS. More... | |
| #define | SR_RF09_PAC_PACUR |
| Access parameters for sub-register PACUR in register RG_RF09_PAC. More... | |
| #define | SR_RF09_PAC_TXPWR |
| Sub-registers of Register RG_RF09_PAC. More... | |
| #define | SR_RF09_PADFE_PADFE |
| Sub-registers of Register RG_RF09_PADFE. More... | |
| #define | SR_RF09_PLL_LBW RG_RF09_PLL, PLL_LBW_MASK, PLL_LBW_SHIFT |
| Access parameters for sub-register LBW in register RG_RF09_PLL. More... | |
| #define | SR_RF09_PLL_LS RG_RF09_PLL, PLL_LS_MASK, PLL_LS_SHIFT |
| Sub-registers of Register RG_RF09_PLL. More... | |
| #define | SR_RF09_PLLCF_CF |
| Sub-registers of Register RG_RF09_PLLCF. More... | |
| #define | SR_RF09_RNDV_RNDV |
| Sub-registers of Register RG_RF09_RNDV. More... | |
| #define | SR_RF09_RSSI_RSSI |
| Sub-registers of Register RG_RF09_RSSI. More... | |
| #define | SR_RF09_RXBWC_BW |
| Sub-registers of Register RG_RF09_RXBWC. More... | |
| #define | SR_RF09_RXBWC_IFI |
| Access parameters for sub-register IFI in register RG_RF09_RXBWC. More... | |
| #define | SR_RF09_RXBWC_IFS |
| Access parameters for sub-register IFS in register RG_RF09_RXBWC. More... | |
| #define | SR_RF09_RXDFE_RCUT |
| Access parameters for sub-register RCUT in register RG_RF09_RXDFE. More... | |
| #define | SR_RF09_RXDFE_SR |
| Sub-registers of Register RG_RF09_RXDFE. More... | |
| #define | SR_RF09_STATE_STATE |
| Sub-registers of Register RG_RF09_STATE. More... | |
| #define | SR_RF09_TXCI_DCOI |
| Sub-registers of Register RG_RF09_TXCI. More... | |
| #define | SR_RF09_TXCQ_DCOQ |
| Sub-registers of Register RG_RF09_TXCQ. More... | |
| #define | SR_RF09_TXCUTC_LPFCUT |
| Sub-registers of Register RG_RF09_TXCUTC. More... | |
| #define | SR_RF09_TXCUTC_PARAMP |
| Access parameters for sub-register PARAMP in register RG_RF09_TXCUTC. More... | |
| #define | SR_RF09_TXDACI_ENTXDACID |
| Access parameters for sub-register ENTXDACID in register RG_RF09_TXDACI. More... | |
| #define | SR_RF09_TXDACI_TXDACID |
| Sub-registers of Register RG_RF09_TXDACI. More... | |
| #define | SR_RF09_TXDACQ_ENTXDACQD |
| Access parameters for sub-register ENTXDACQD in register RG_RF09_TXDACQ. More... | |
| #define | SR_RF09_TXDACQ_TXDACQD |
| Sub-registers of Register RG_RF09_TXDACQ. More... | |
| #define | SR_RF09_TXDFE_DM |
| Access parameters for sub-register DM in register RG_RF09_TXDFE. More... | |
| #define | SR_RF09_TXDFE_RCUT |
| Access parameters for sub-register RCUT in register RG_RF09_TXDFE. More... | |
| #define | SR_RF09_TXDFE_SR |
| Sub-registers of Register RG_RF09_TXDFE. More... | |
| #define | SR_RF24_AGCC_AGCI |
| Access parameters for sub-register AGCI in register RG_RF24_AGCC. More... | |
| #define | SR_RF24_AGCC_AVGS |
| Access parameters for sub-register AVGS in register RG_RF24_AGCC. More... | |
| #define | SR_RF24_AGCC_EN |
| Sub-registers of Register RG_RF24_AGCC. More... | |
| #define | SR_RF24_AGCC_FRZC |
| Access parameters for sub-register FRZC in register RG_RF24_AGCC. More... | |
| #define | SR_RF24_AGCC_FRZS |
| Access parameters for sub-register FRZS in register RG_RF24_AGCC. More... | |
| #define | SR_RF24_AGCC_RST |
| Access parameters for sub-register RST in register RG_RF24_AGCC. More... | |
| #define | SR_RF24_AGCS_GCW |
| Sub-registers of Register RG_RF24_AGCS. More... | |
| #define | SR_RF24_AGCS_TGT |
| Access parameters for sub-register TGT in register RG_RF24_AGCS. More... | |
| #define | SR_RF24_AUXS_AGCMAP |
| Access parameters for sub-register AGCMAP in register RG_RF24_AUXS. More... | |
| #define | SR_RF24_AUXS_AVEN |
| Access parameters for sub-register AVEN in register RG_RF24_AUXS. More... | |
| #define | SR_RF24_AUXS_AVEXT |
| Access parameters for sub-register AVEXT in register RG_RF24_AUXS. More... | |
| #define | SR_RF24_AUXS_AVS |
| Access parameters for sub-register AVS in register RG_RF24_AUXS. More... | |
| #define | SR_RF24_AUXS_EXTLNABYP |
| Access parameters for sub-register EXTLNABYP in register RG_RF24_AUXS. More... | |
| #define | SR_RF24_AUXS_PAVC |
| Sub-registers of Register RG_RF24_AUXS. More... | |
| #define | SR_RF24_CCF0H_CCF0H |
| Sub-registers of Register RG_RF24_CCF0H. More... | |
| #define | SR_RF24_CCF0L_CCF0L |
| Sub-registers of Register RG_RF24_CCF0L. More... | |
| #define | SR_RF24_CMD_CMD RG_RF24_CMD, CMD_CMD_MASK, CMD_CMD_SHIFT |
| Sub-registers of Register RG_RF24_CMD. More... | |
| #define | SR_RF24_CNL_CNL RG_RF24_CNL, CNL_CNL_MASK, CNL_CNL_SHIFT |
| Sub-registers of Register RG_RF24_CNL. More... | |
| #define | SR_RF24_CNM_CM RG_RF24_CNM, CNM_CM_MASK, CNM_CM_SHIFT |
| Access parameters for sub-register CM in register RG_RF24_CNM. More... | |
| #define | SR_RF24_CNM_CNH RG_RF24_CNM, CNM_CNH_MASK, CNM_CNH_SHIFT |
| Sub-registers of Register RG_RF24_CNM. More... | |
| #define | SR_RF24_CS_CS RG_RF24_CS, CS_CS_MASK, CS_CS_SHIFT |
| Sub-registers of Register RG_RF24_CS. More... | |
| #define | SR_RF24_EDC_EDM RG_RF24_EDC, EDC_EDM_MASK, EDC_EDM_SHIFT |
| Sub-registers of Register RG_RF24_EDC. More... | |
| #define | SR_RF24_EDD_DF RG_RF24_EDD, EDD_DF_MASK, EDD_DF_SHIFT |
| Access parameters for sub-register DF in register RG_RF24_EDD. More... | |
| #define | SR_RF24_EDD_DTB RG_RF24_EDD, EDD_DTB_MASK, EDD_DTB_SHIFT |
| Sub-registers of Register RG_RF24_EDD. More... | |
| #define | SR_RF24_EDV_EDV RG_RF24_EDV, EDV_EDV_MASK, EDV_EDV_SHIFT |
| Sub-registers of Register RG_RF24_EDV. More... | |
| #define | SR_RF24_IRQM_BATLOW |
| Access parameters for sub-register BATLOW in register RG_RF24_IRQM. More... | |
| #define | SR_RF24_IRQM_EDC |
| Access parameters for sub-register EDC in register RG_RF24_IRQM. More... | |
| #define | SR_RF24_IRQM_IQIFSF |
| Access parameters for sub-register IQIFSF in register RG_RF24_IRQM. More... | |
| #define | SR_RF24_IRQM_TRXERR |
| Access parameters for sub-register TRXERR in register RG_RF24_IRQM. More... | |
| #define | SR_RF24_IRQM_TRXRDY |
| Access parameters for sub-register TRXRDY in register RG_RF24_IRQM. More... | |
| #define | SR_RF24_IRQM_WAKEUP |
| Sub-registers of Register RG_RF24_IRQM. More... | |
| #define | SR_RF24_IRQS_BATLOW |
| Access parameters for sub-register BATLOW in register RG_RF24_IRQS. More... | |
| #define | SR_RF24_IRQS_EDC |
| Access parameters for sub-register EDC in register RG_RF24_IRQS. More... | |
| #define | SR_RF24_IRQS_IQIFSF |
| Access parameters for sub-register IQIFSF in register RG_RF24_IRQS. More... | |
| #define | SR_RF24_IRQS_TRXERR |
| Access parameters for sub-register TRXERR in register RG_RF24_IRQS. More... | |
| #define | SR_RF24_IRQS_TRXRDY |
| Access parameters for sub-register TRXRDY in register RG_RF24_IRQS. More... | |
| #define | SR_RF24_IRQS_WAKEUP |
| Sub-registers of Register RG_RF24_IRQS. More... | |
| #define | SR_RF24_PAC_PACUR |
| Access parameters for sub-register PACUR in register RG_RF24_PAC. More... | |
| #define | SR_RF24_PAC_TXPWR |
| Sub-registers of Register RG_RF24_PAC. More... | |
| #define | SR_RF24_PADFE_PADFE |
| Sub-registers of Register RG_RF24_PADFE. More... | |
| #define | SR_RF24_PLL_LBW RG_RF24_PLL, PLL_LBW_MASK, PLL_LBW_SHIFT |
| Access parameters for sub-register LBW in register RG_RF24_PLL. More... | |
| #define | SR_RF24_PLL_LS RG_RF24_PLL, PLL_LS_MASK, PLL_LS_SHIFT |
| Sub-registers of Register RG_RF24_PLL. More... | |
| #define | SR_RF24_PLLCF_CF |
| Sub-registers of Register RG_RF24_PLLCF. More... | |
| #define | SR_RF24_RNDV_RNDV |
| Sub-registers of Register RG_RF24_RNDV. More... | |
| #define | SR_RF24_RSSI_RSSI |
| Sub-registers of Register RG_RF24_RSSI. More... | |
| #define | SR_RF24_RXBWC_BW |
| Sub-registers of Register RG_RF24_RXBWC. More... | |
| #define | SR_RF24_RXBWC_IFI |
| Access parameters for sub-register IFI in register RG_RF24_RXBWC. More... | |
| #define | SR_RF24_RXBWC_IFS |
| Access parameters for sub-register IFS in register RG_RF24_RXBWC. More... | |
| #define | SR_RF24_RXDFE_RCUT |
| Access parameters for sub-register RCUT in register RG_RF24_RXDFE. More... | |
| #define | SR_RF24_RXDFE_SR |
| Sub-registers of Register RG_RF24_RXDFE. More... | |
| #define | SR_RF24_STATE_STATE |
| Sub-registers of Register RG_RF24_STATE. More... | |
| #define | SR_RF24_TXCI_DCOI |
| Sub-registers of Register RG_RF24_TXCI. More... | |
| #define | SR_RF24_TXCQ_DCOQ |
| Sub-registers of Register RG_RF24_TXCQ. More... | |
| #define | SR_RF24_TXCUTC_LPFCUT |
| Sub-registers of Register RG_RF24_TXCUTC. More... | |
| #define | SR_RF24_TXCUTC_PARAMP |
| Access parameters for sub-register PARAMP in register RG_RF24_TXCUTC. More... | |
| #define | SR_RF24_TXDACI_ENTXDACID |
| Access parameters for sub-register ENTXDACID in register RG_RF24_TXDACI. More... | |
| #define | SR_RF24_TXDACI_TXDACID |
| Sub-registers of Register RG_RF24_TXDACI. More... | |
| #define | SR_RF24_TXDACQ_ENTXDACQD |
| Access parameters for sub-register ENTXDACQD in register RG_RF24_TXDACQ. More... | |
| #define | SR_RF24_TXDACQ_TXDACQD |
| Sub-registers of Register RG_RF24_TXDACQ. More... | |
| #define | SR_RF24_TXDFE_DM |
| Access parameters for sub-register DM in register RG_RF24_TXDFE. More... | |
| #define | SR_RF24_TXDFE_RCUT |
| Access parameters for sub-register RCUT in register RG_RF24_TXDFE. More... | |
| #define | SR_RF24_TXDFE_SR |
| Sub-registers of Register RG_RF24_TXDFE. More... | |
| #define | SR_RF_BMDVC_BMHR |
| Access parameters for sub-register BMHR in register RG_RF_BMDVC. More... | |
| #define | SR_RF_BMDVC_BMS |
| Access parameters for sub-register BMS in register RG_RF_BMDVC. More... | |
| #define | SR_RF_BMDVC_BMVTH |
| Sub-registers of Register RG_RF_BMDVC. More... | |
| #define | SR_RF_CFG_DRV RG_RF_CFG, CFG_DRV_MASK, CFG_DRV_SHIFT |
| Sub-registers of Register RG_RF_CFG. More... | |
| #define | SR_RF_CFG_IRQMM |
| Access parameters for sub-register IRQMM in register RG_RF_CFG. More... | |
| #define | SR_RF_CFG_IRQP RG_RF_CFG, CFG_IRQP_MASK, CFG_IRQP_SHIFT |
| Access parameters for sub-register IRQP in register RG_RF_CFG. More... | |
| #define | SR_RF_CLKO_DRV |
| Access parameters for sub-register DRV in register RG_RF_CLKO. More... | |
| #define | SR_RF_CLKO_OS RG_RF_CLKO, CLKO_OS_MASK, CLKO_OS_SHIFT |
| Sub-registers of Register RG_RF_CLKO. More... | |
| #define | SR_RF_IQIFC0_CMV |
| Access parameters for sub-register CMV in register RG_RF_IQIFC0. More... | |
| #define | SR_RF_IQIFC0_CMV1V2 |
| Access parameters for sub-register CMV1V2 in register RG_RF_IQIFC0. More... | |
| #define | SR_RF_IQIFC0_DRV |
| Access parameters for sub-register DRV in register RG_RF_IQIFC0. More... | |
| #define | SR_RF_IQIFC0_EEC |
| Sub-registers of Register RG_RF_IQIFC0. More... | |
| #define | SR_RF_IQIFC0_EXTLB |
| Access parameters for sub-register EXTLB in register RG_RF_IQIFC0. More... | |
| #define | SR_RF_IQIFC0_SF |
| Access parameters for sub-register SF in register RG_RF_IQIFC0. More... | |
| #define | SR_RF_IQIFC1_CHPM |
| Access parameters for sub-register CHPM in register RG_RF_IQIFC1. More... | |
| #define | SR_RF_IQIFC1_FAILSF |
| Access parameters for sub-register FAILSF in register RG_RF_IQIFC1. More... | |
| #define | SR_RF_IQIFC1_SKEWDRV |
| Sub-registers of Register RG_RF_IQIFC1. More... | |
| #define | SR_RF_IQIFC2_SYNC |
| Sub-registers of Register RG_RF_IQIFC2. More... | |
| #define | SR_RF_PN_PN RG_RF_PN, PN_PN_MASK, PN_PN_SHIFT |
| Sub-registers of Register RG_RF_PN. More... | |
| #define | SR_RF_RST_CMD RG_RF_RST, RST_CMD_MASK, RST_CMD_SHIFT |
| Sub-registers of Register RG_RF_RST. More... | |
| #define | SR_RF_VN_VN RG_RF_VN, VN_VN_MASK, VN_VN_SHIFT |
| Sub-registers of Register RG_RF_VN. More... | |
| #define | SR_RF_XOC_FS RG_RF_XOC, XOC_FS_MASK, XOC_FS_SHIFT |
| Access parameters for sub-register FS in register RG_RF_XOC. More... | |
| #define | SR_RF_XOC_TRIM RG_RF_XOC, XOC_TRIM_MASK, XOC_TRIM_SHIFT |
| Sub-registers of Register RG_RF_XOC. More... | |
| #define | STATE_STATE_MASK 0x07 |
| Sub-registers of Register STATE. More... | |
| #define | STATE_STATE_SHIFT 0 |
| Bit Offset for Sub-Register STATE.STATE. More... | |
| #define | TXCI_DCOI_MASK 0x3F |
| Sub-registers of Register TXCI. More... | |
| #define | TXCI_DCOI_SHIFT 0 |
| Bit Offset for Sub-Register TXCI.DCOI. More... | |
| #define | TXCQ_DCOQ_MASK 0x3F |
| Sub-registers of Register TXCQ. More... | |
| #define | TXCQ_DCOQ_SHIFT 0 |
| Bit Offset for Sub-Register TXCQ.DCOQ. More... | |
| #define | TXCUTC_LPFCUT_MASK 0x0F |
| Sub-registers of Register TXCUTC. More... | |
| #define | TXCUTC_LPFCUT_SHIFT 0 |
| Bit Offset for Sub-Register TXCUTC.LPFCUT. More... | |
| #define | TXCUTC_PARAMP_MASK 0xC0 |
| Bit Mask for Sub-Register TXCUTC.PARAMP. More... | |
| #define | TXCUTC_PARAMP_SHIFT 6 |
| Bit Offset for Sub-Register TXCUTC.PARAMP. More... | |
| #define | TXDACI_ENTXDACID_MASK 0x80 |
| Bit Mask for Sub-Register TXDACI.ENTXDACID. More... | |
| #define | TXDACI_ENTXDACID_SHIFT 7 |
| Bit Offset for Sub-Register TXDACI.ENTXDACID. More... | |
| #define | TXDACI_TXDACID_MASK 0x7F |
| Sub-registers of Register TXDACI. More... | |
| #define | TXDACI_TXDACID_SHIFT 0 |
| Bit Offset for Sub-Register TXDACI.TXDACID. More... | |
| #define | TXDACQ_ENTXDACQD_MASK 0x80 |
| Bit Mask for Sub-Register TXDACQ.ENTXDACQD. More... | |
| #define | TXDACQ_ENTXDACQD_SHIFT 7 |
| Bit Offset for Sub-Register TXDACQ.ENTXDACQD. More... | |
| #define | TXDACQ_TXDACQD_MASK 0x7F |
| Sub-registers of Register TXDACQ. More... | |
| #define | TXDACQ_TXDACQD_SHIFT 0 |
| Bit Offset for Sub-Register TXDACQ.TXDACQD. More... | |
| #define | TXDFE_DM_MASK 0x10 |
| Bit Mask for Sub-Register TXDFE.DM. More... | |
| #define | TXDFE_DM_SHIFT 4 |
| Bit Offset for Sub-Register TXDFE.DM. More... | |
| #define | TXDFE_RCUT_MASK 0xE0 |
| Bit Mask for Sub-Register TXDFE.RCUT. More... | |
| #define | TXDFE_RCUT_SHIFT 5 |
| Bit Offset for Sub-Register TXDFE.RCUT. More... | |
| #define | TXDFE_SR_MASK 0x0F |
| Sub-registers of Register TXDFE. More... | |
| #define | TXDFE_SR_SHIFT 0 |
| Bit Offset for Sub-Register TXDFE.SR. More... | |
| #define | TXFLH_TXFLH_MASK 0x07 |
| Sub-registers of Register TXFLH. More... | |
| #define | TXFLH_TXFLH_SHIFT 0 |
| Bit Offset for Sub-Register TXFLH.TXFLH. More... | |
| #define | TXFLL_TXFLL_MASK 0xFF |
| Sub-registers of Register TXFLL. More... | |
| #define | TXFLL_TXFLL_SHIFT 0 |
| Bit Offset for Sub-Register TXFLL.TXFLL. More... | |
| #define | VN_VN_MASK 0xFF |
| Sub-registers of Register VN. More... | |
| #define | VN_VN_SHIFT 0 |
| Bit Offset for Sub-Register VN.VN. More... | |
| #define | XOC_FS_MASK 0x10 |
| Bit Mask for Sub-Register XOC.FS. More... | |
| #define | XOC_FS_SHIFT 4 |
| Bit Offset for Sub-Register XOC.FS. More... | |
| #define | XOC_TRIM_MASK 0x0F |
| Sub-registers of Register XOC. More... | |
| #define | XOC_TRIM_SHIFT 0 |
| Bit Offset for Sub-Register XOC.TRIM. More... | |
Typedefs | |
| typedef enum bb_irq_tag | bb_irq_t |
| Enumeration for BB IRQs. More... | |
| typedef enum rf_cmd_state_tag | rf_cmd_state_t |
| Enumerations. More... | |
| typedef enum rf_cmd_status_tag | rf_cmd_status_t |
| Enumeration for RF commands and states used for trx command and state registers. More... | |
| typedef enum rf_irq_tag | rf_irq_t |
| Enumeration for RF IRQs used for IRQS and IRQM registers. More... | |
Enumerations | |
| enum | bb_irq_tag { BB_IRQ_FBLI = (0x80), BB_IRQ_AGCR = (0x40), BB_IRQ_AGCH = (0x20), BB_IRQ_TXFE = (0x10), BB_IRQ_RXEM = (0x08), BB_IRQ_RXAM = (0x04), BB_IRQ_RXFE = (0x02), BB_IRQ_RXFS = (0x01), BB_IRQ_NO_IRQ = (0x00), BB_IRQ_ALL_IRQ = (0xFF) } |
| Enumeration for BB IRQs. More... | |
| enum | rf_cmd_state_tag { RF_NOP = (0x0), RF_SLEEP = (0x1), RF_TRXOFF = (0x2), RF_TXPREP = (0x3), RF_TX = (0x4), RF_RX = (0x5), RF_RESET = (0x7) } |
| Enumerations. More... | |
| enum | rf_cmd_status_tag { STATUS_RF_TRXOFF = (0x2), STATUS_RF_TXPREP = (0x3), STATUS_RF_TX = (0x4), STATUS_RF_RX = (0x5), STATUS_RF_TRANSITION = (0x6), STATUS_RF_RESET = (0x7) } |
| Enumeration for RF commands and states used for trx command and state registers. More... | |
| enum | rf_irq_tag { RF_IRQ_IQIFSF = (0x20), RF_IRQ_TRXERR = (0x10), RF_IRQ_BATLOW = (0x08), RF_IRQ_EDC = (0x04), RF_IRQ_TRXRDY = (0x02), RF_IRQ_WAKEUP = (0x01), RF_IRQ_NO_IRQ = (0x00), RF_IRQ_ALL_IRQ = (0x3F) } |
| Enumeration for RF IRQs used for IRQS and IRQM registers. More... | |
| #define AFC0_AFEN0_MASK 0x01 |
Sub-registers of Register AFC0.
Bit Mask for Sub-Register AFC0.AFEN0
| #define AFC0_AFEN0_SHIFT 0 |
Bit Offset for Sub-Register AFC0.AFEN0.
| #define AFC0_AFEN1_MASK 0x02 |
Bit Mask for Sub-Register AFC0.AFEN1.
| #define AFC0_AFEN1_SHIFT 1 |
Bit Offset for Sub-Register AFC0.AFEN1.
| #define AFC0_AFEN2_MASK 0x04 |
Bit Mask for Sub-Register AFC0.AFEN2.
| #define AFC0_AFEN2_SHIFT 2 |
Bit Offset for Sub-Register AFC0.AFEN2.
| #define AFC0_AFEN3_MASK 0x08 |
Bit Mask for Sub-Register AFC0.AFEN3.
| #define AFC0_AFEN3_SHIFT 3 |
Bit Offset for Sub-Register AFC0.AFEN3.
| #define AFC0_PM_MASK 0x10 |
Bit Mask for Sub-Register AFC0.PM.
| #define AFC0_PM_SHIFT 4 |
Bit Offset for Sub-Register AFC0.PM.
| #define AFC1_MRFT0_MASK 0x10 |
Bit Mask for Sub-Register AFC1.MRFT0.
| #define AFC1_MRFT0_SHIFT 4 |
Bit Offset for Sub-Register AFC1.MRFT0.
| #define AFC1_MRFT1_MASK 0x20 |
Bit Mask for Sub-Register AFC1.MRFT1.
| #define AFC1_MRFT1_SHIFT 5 |
Bit Offset for Sub-Register AFC1.MRFT1.
| #define AFC1_MRFT2_MASK 0x40 |
Bit Mask for Sub-Register AFC1.MRFT2.
| #define AFC1_MRFT2_SHIFT 6 |
Bit Offset for Sub-Register AFC1.MRFT2.
| #define AFC1_MRFT3_MASK 0x80 |
Bit Mask for Sub-Register AFC1.MRFT3.
| #define AFC1_MRFT3_SHIFT 7 |
Bit Offset for Sub-Register AFC1.MRFT3.
| #define AFC1_PANC0_MASK 0x01 |
Sub-registers of Register AFC1.
Bit Mask for Sub-Register AFC1.PANC0
| #define AFC1_PANC0_SHIFT 0 |
Bit Offset for Sub-Register AFC1.PANC0.
| #define AFC1_PANC1_MASK 0x02 |
Bit Mask for Sub-Register AFC1.PANC1.
| #define AFC1_PANC1_SHIFT 1 |
Bit Offset for Sub-Register AFC1.PANC1.
| #define AFC1_PANC2_MASK 0x04 |
Bit Mask for Sub-Register AFC1.PANC2.
| #define AFC1_PANC2_SHIFT 2 |
Bit Offset for Sub-Register AFC1.PANC2.
| #define AFC1_PANC3_MASK 0x08 |
Bit Mask for Sub-Register AFC1.PANC3.
| #define AFC1_PANC3_SHIFT 3 |
Bit Offset for Sub-Register AFC1.PANC3.
| #define AFFTM_AFFTM_MASK 0xFF |
Sub-registers of Register AFFTM.
Bit Mask for Sub-Register AFFTM.AFFTM
| #define AFFTM_AFFTM_SHIFT 0 |
Bit Offset for Sub-Register AFFTM.AFFTM.
| #define AFFVM_AFFVM_MASK 0x0F |
Sub-registers of Register AFFVM.
Bit Mask for Sub-Register AFFVM.AFFVM
| #define AFFVM_AFFVM_SHIFT 0 |
Bit Offset for Sub-Register AFFVM.AFFVM.
| #define AFS_AM0_MASK 0x01 |
Sub-registers of Register AFS.
Bit Mask for Sub-Register AFS.AM0
| #define AFS_AM0_SHIFT 0 |
Bit Offset for Sub-Register AFS.AM0.
| #define AFS_AM1_MASK 0x02 |
Bit Mask for Sub-Register AFS.AM1.
| #define AFS_AM1_SHIFT 1 |
Bit Offset for Sub-Register AFS.AM1.
| #define AFS_AM2_MASK 0x04 |
Bit Mask for Sub-Register AFS.AM2.
| #define AFS_AM2_SHIFT 2 |
Bit Offset for Sub-Register AFS.AM2.
| #define AFS_AM3_MASK 0x08 |
Bit Mask for Sub-Register AFS.AM3.
| #define AFS_AM3_SHIFT 3 |
Bit Offset for Sub-Register AFS.AM3.
| #define AFS_EM_MASK 0x10 |
Bit Mask for Sub-Register AFS.EM.
| #define AFS_EM_SHIFT 4 |
Bit Offset for Sub-Register AFS.EM.
| #define AGCC_AGCI_MASK 0x40 |
Bit Mask for Sub-Register AGCC.AGCI.
Referenced by fsk_rfcfg().
| #define AGCC_AGCI_SHIFT 6 |
Bit Offset for Sub-Register AGCC.AGCI.
Referenced by fsk_rfcfg(), ofdm_rfcfg(), and oqpsk_rfcfg().
| #define AGCC_AVGS_MASK 0x30 |
Bit Mask for Sub-Register AGCC.AVGS.
Referenced by fsk_rfcfg().
| #define AGCC_AVGS_SHIFT 4 |
Bit Offset for Sub-Register AGCC.AVGS.
Referenced by fsk_rfcfg(), ofdm_rfcfg(), and oqpsk_rfcfg().
| #define AGCC_EN_MASK 0x01 |
Sub-registers of Register AGCC.
Bit Mask for Sub-Register AGCC.EN
| #define AGCC_EN_SHIFT 0 |
Bit Offset for Sub-Register AGCC.EN.
| #define AGCC_FRZC_MASK 0x02 |
Bit Mask for Sub-Register AGCC.FRZC.
| #define AGCC_FRZC_SHIFT 1 |
Bit Offset for Sub-Register AGCC.FRZC.
| #define AGCC_FRZS_MASK 0x04 |
Bit Mask for Sub-Register AGCC.FRZS.
| #define AGCC_FRZS_SHIFT 2 |
Bit Offset for Sub-Register AGCC.FRZS.
| #define AGCC_RST_MASK 0x08 |
Bit Mask for Sub-Register AGCC.RST.
| #define AGCC_RST_SHIFT 3 |
Bit Offset for Sub-Register AGCC.RST.
| #define AGCS_GCW_MASK 0x1F |
Sub-registers of Register AGCS.
Bit Mask for Sub-Register AGCS.GCW
| #define AGCS_GCW_SHIFT 0 |
Bit Offset for Sub-Register AGCS.GCW.
Referenced by ofdm_rfcfg(), and oqpsk_rfcfg().
| #define AGCS_TGT_MASK 0xE0 |
Bit Mask for Sub-Register AGCS.TGT.
| #define AGCS_TGT_SHIFT 5 |
Bit Offset for Sub-Register AGCS.TGT.
Referenced by ofdm_rfcfg(), and oqpsk_rfcfg().
| #define AMAACKPD_PD0_MASK 0x01 |
Sub-registers of Register AMAACKPD.
Bit Mask for Sub-Register AMAACKPD.PD0
| #define AMAACKPD_PD0_SHIFT 0 |
Bit Offset for Sub-Register AMAACKPD.PD0.
| #define AMAACKPD_PD1_MASK 0x02 |
Bit Mask for Sub-Register AMAACKPD.PD1.
| #define AMAACKPD_PD1_SHIFT 1 |
Bit Offset for Sub-Register AMAACKPD.PD1.
| #define AMAACKPD_PD2_MASK 0x04 |
Bit Mask for Sub-Register AMAACKPD.PD2.
| #define AMAACKPD_PD2_SHIFT 2 |
Bit Offset for Sub-Register AMAACKPD.PD2.
| #define AMAACKPD_PD3_MASK 0x08 |
Bit Mask for Sub-Register AMAACKPD.PD3.
| #define AMAACKPD_PD3_SHIFT 3 |
Bit Offset for Sub-Register AMAACKPD.PD3.
| #define AMAACKTH_AMAACKTH_MASK 0x07 |
Sub-registers of Register AMAACKTH.
Bit Mask for Sub-Register AMAACKTH.AMAACKTH
| #define AMAACKTH_AMAACKTH_SHIFT 0 |
Bit Offset for Sub-Register AMAACKTH.AMAACKTH.
| #define AMAACKTL_AMAACKTL_MASK 0xFF |
Sub-registers of Register AMAACKTL.
Bit Mask for Sub-Register AMAACKTL.AMAACKTL
| #define AMAACKTL_AMAACKTL_SHIFT 0 |
Bit Offset for Sub-Register AMAACKTL.AMAACKTL.
| #define AMCS_AACK_MASK 0x08 |
Bit Mask for Sub-Register AMCS.AACK.
Referenced by trx_config(), and tx_done_handling().
| #define AMCS_AACK_SHIFT 3 |
Bit Offset for Sub-Register AMCS.AACK.
| #define AMCS_AACKDR_MASK 0x20 |
Bit Mask for Sub-Register AMCS.AACKDR.
| #define AMCS_AACKDR_SHIFT 5 |
Bit Offset for Sub-Register AMCS.AACKDR.
| #define AMCS_AACKFA_MASK 0x40 |
Bit Mask for Sub-Register AMCS.AACKFA.
| #define AMCS_AACKFA_SHIFT 6 |
Bit Offset for Sub-Register AMCS.AACKFA.
| #define AMCS_AACKFT_MASK 0x80 |
Bit Mask for Sub-Register AMCS.AACKFT.
| #define AMCS_AACKFT_SHIFT 7 |
Bit Offset for Sub-Register AMCS.AACKFT.
| #define AMCS_AACKS_MASK 0x10 |
Bit Mask for Sub-Register AMCS.AACKS.
| #define AMCS_AACKS_SHIFT 4 |
Bit Offset for Sub-Register AMCS.AACKS.
| #define AMCS_CCAED_MASK 0x04 |
Bit Mask for Sub-Register AMCS.CCAED.
| #define AMCS_CCAED_SHIFT 2 |
Bit Offset for Sub-Register AMCS.CCAED.
| #define AMCS_CCATX_MASK 0x02 |
Bit Mask for Sub-Register AMCS.CCATX.
Referenced by transmit_frame().
| #define AMCS_CCATX_SHIFT 1 |
Bit Offset for Sub-Register AMCS.CCATX.
| #define AMCS_TX2RX_MASK 0x01 |
Sub-registers of Register AMCS.
Bit Mask for Sub-Register AMCS.TX2RX
Referenced by transmit_frame().
| #define AMCS_TX2RX_SHIFT 0 |
Bit Offset for Sub-Register AMCS.TX2RX.
| #define AMEDT_AMEDT_MASK 0xFF |
Sub-registers of Register AMEDT.
Bit Mask for Sub-Register AMEDT.AMEDT
| #define AMEDT_AMEDT_SHIFT 0 |
Bit Offset for Sub-Register AMEDT.AMEDT.
| #define AUXS_AGCMAP_MASK 0x60 |
Bit Mask for Sub-Register AUXS.AGCMAP.
| #define AUXS_AGCMAP_SHIFT 5 |
Bit Offset for Sub-Register AUXS.AGCMAP.
| #define AUXS_AVEN_MASK 0x08 |
Bit Mask for Sub-Register AUXS.AVEN.
| #define AUXS_AVEN_SHIFT 3 |
Bit Offset for Sub-Register AUXS.AVEN.
| #define AUXS_AVEXT_MASK 0x10 |
Bit Mask for Sub-Register AUXS.AVEXT.
| #define AUXS_AVEXT_SHIFT 4 |
Bit Offset for Sub-Register AUXS.AVEXT.
| #define AUXS_AVS_MASK 0x04 |
Bit Mask for Sub-Register AUXS.AVS.
| #define AUXS_AVS_SHIFT 2 |
Bit Offset for Sub-Register AUXS.AVS.
| #define AUXS_EXTLNABYP_MASK 0x80 |
Bit Mask for Sub-Register AUXS.EXTLNABYP.
| #define AUXS_EXTLNABYP_SHIFT 7 |
Bit Offset for Sub-Register AUXS.EXTLNABYP.
| #define AUXS_PAVC_MASK 0x03 |
Sub-registers of Register AUXS.
Bit Mask for Sub-Register AUXS.PAVC
| #define AUXS_PAVC_SHIFT 0 |
Bit Offset for Sub-Register AUXS.PAVC.
| #define BASE_ADDR_BBC0_CORE0 (0x0300) |
Base address for BBC0_CORE0 register set.
| #define BASE_ADDR_BBC0_CORE0_IRQS (0x0002) |
Base address for BBC0_CORE0_IRQS register set.
| #define BASE_ADDR_BBC0_FB0 (0x2000) |
Base address for BBC0_FB0 register set.
| #define BASE_ADDR_BBC1_CORE1 (0x0400) |
Base address for BBC1_CORE1 register set.
| #define BASE_ADDR_BBC1_CORE1_IRQS (0x0003) |
Base address for BBC1_CORE1_IRQS register set.
| #define BASE_ADDR_BBC1_FB1 (0x3000) |
Base address for BBC1_FB1 register set.
| #define BASE_ADDR_RF09_RF09 (0x0100) |
Base address for RF09_RF09 register set.
| #define BASE_ADDR_RF09_RFIRQS09 (0x0000) |
Register group base addresses.
Base address for RF09_RFIRQS09 register set
| #define BASE_ADDR_RF24_RF24 (0x0200) |
Base address for RF24_RF24 register set.
| #define BASE_ADDR_RF24_RFIRQS24 (0x0001) |
Base address for RF24_RFIRQS24 register set.
| #define BASE_ADDR_RF_RFCOMMON (0x0005) |
Base address for RF_RFCOMMON register set.
| #define BASE_ADDR_RFT09_RFT09 (0x0100) |
Base address for RFT09_RFT09 register set.
| #define BASE_ADDR_RFT24_RFT24 (0x0200) |
Base address for RFT24_RFT24 register set.
| #define BASE_ADDR_RFT_RFTESTCOMMON (0x0005) |
Base address for RFT_RFTESTCOMMON register set.
| #define BB_CH_BUSY (0x1) |
Constant CH_BUSY for sub-register SR_CCAED in register BBC0_AMCS.
| #define BB_CH_CLEAR (0x0) |
Constant CH_CLEAR for sub-register SR_CCAED in register BBC0_AMCS.
Referenced by handle_tx_end_irq().
| #define BB_FCHIP100 (0x0) |
Constant FCHIP100 for sub-register SR_FCHIP in register BBC0_OQPSKC0.
| #define BB_FCHIP1000 (0x2) |
Constant FCHIP1000 for sub-register SR_FCHIP in register BBC0_OQPSKC0.
| #define BB_FCHIP200 (0x1) |
Constant FCHIP200 for sub-register SR_FCHIP in register BBC0_OQPSKC0.
| #define BB_FCHIP2000 (0x3) |
Constant FCHIP2000 for sub-register SR_FCHIP in register BBC0_OQPSKC0.
| #define BB_MRFSK (0x1) |
Constant MRFSK for sub-register SR_PT in register BBC0_PC.
Referenced by conf_fsk().
| #define BB_MROFDM (0x2) |
Constant MROFDM for sub-register SR_PT in register BBC0_PC.
Referenced by conf_ofdm().
| #define BB_MROQPSK (0x3) |
Constant MROQPSK for sub-register SR_PT in register BBC0_PC.
Referenced by conf_leg_oqpsk(), and conf_oqpsk().
| #define BB_PHYOFF (0x0) |
Constant PHYOFF for sub-register SR_PT in register BBC0_PC.
| #define BB_RC08 (0x0) |
Constant RC08 for sub-register SR_MOD in register BBC0_OQPSKC0.
| #define BB_RRC08 (0x1) |
Constant RRC08 for sub-register SR_MOD in register BBC0_OQPSKC0.
| #define BMDVC_BMHR_MASK 0x10 |
Bit Mask for Sub-Register BMDVC.BMHR.
| #define BMDVC_BMHR_SHIFT 4 |
Bit Offset for Sub-Register BMDVC.BMHR.
| #define BMDVC_BMS_MASK 0x20 |
Bit Mask for Sub-Register BMDVC.BMS.
| #define BMDVC_BMS_SHIFT 5 |
Bit Offset for Sub-Register BMDVC.BMS.
| #define BMDVC_BMVTH_MASK 0x0F |
Sub-registers of Register BMDVC.
Bit Mask for Sub-Register BMDVC.BMVTH
| #define BMDVC_BMVTH_SHIFT 0 |
Bit Offset for Sub-Register BMDVC.BMVTH.
| #define CCF0H_CCF0H_MASK 0xFF |
Sub-registers of Register CCF0H.
Bit Mask for Sub-Register CCF0H.CCF0H
| #define CCF0H_CCF0H_SHIFT 0 |
Bit Offset for Sub-Register CCF0H.CCF0H.
| #define CCF0L_CCF0L_MASK 0xFF |
Sub-registers of Register CCF0L.
Bit Mask for Sub-Register CCF0L.CCF0L
| #define CCF0L_CCF0L_SHIFT 0 |
Bit Offset for Sub-Register CCF0L.CCF0L.
| #define CFG_DRV_MASK 0x03 |
Sub-registers of Register CFG.
Bit Mask for Sub-Register CFG.DRV
| #define CFG_DRV_SHIFT 0 |
Bit Offset for Sub-Register CFG.DRV.
| #define CFG_IRQMM_MASK 0x08 |
Bit Mask for Sub-Register CFG.IRQMM.
| #define CFG_IRQMM_SHIFT 3 |
Bit Offset for Sub-Register CFG.IRQMM.
| #define CFG_IRQP_MASK 0x04 |
Bit Mask for Sub-Register CFG.IRQP.
| #define CFG_IRQP_SHIFT 2 |
Bit Offset for Sub-Register CFG.IRQP.
| #define CLKO_DRV_MASK 0x18 |
Bit Mask for Sub-Register CLKO.DRV.
| #define CLKO_DRV_SHIFT 3 |
Bit Offset for Sub-Register CLKO.DRV.
| #define CLKO_OS_MASK 0x07 |
Sub-registers of Register CLKO.
Bit Mask for Sub-Register CLKO.OS
| #define CLKO_OS_SHIFT 0 |
Bit Offset for Sub-Register CLKO.OS.
| #define CMD_CMD_MASK 0x07 |
Sub-registers of Register CMD.
Bit Mask for Sub-Register CMD.CMD
| #define CMD_CMD_SHIFT 0 |
Bit Offset for Sub-Register CMD.CMD.
| #define CNL_CNL_MASK 0xFF |
Sub-registers of Register CNL.
Bit Mask for Sub-Register CNL.CNL
| #define CNL_CNL_SHIFT 0 |
Bit Offset for Sub-Register CNL.CNL.
| #define CNM_CM_MASK 0xC0 |
Bit Mask for Sub-Register CNM.CM.
| #define CNM_CM_SHIFT 6 |
Bit Offset for Sub-Register CNM.CM.
| #define CNM_CNH_MASK 0x01 |
Sub-registers of Register CNM.
Bit Mask for Sub-Register CNM.CNH
| #define CNM_CNH_SHIFT 0 |
Bit Offset for Sub-Register CNM.CNH.
| #define CNT0_CNT0_MASK 0xFF |
Sub-registers of Register CNT0.
Bit Mask for Sub-Register CNT0.CNT0
| #define CNT0_CNT0_SHIFT 0 |
Bit Offset for Sub-Register CNT0.CNT0.
| #define CNT1_CNT1_MASK 0xFF |
Sub-registers of Register CNT1.
Bit Mask for Sub-Register CNT1.CNT1
| #define CNT1_CNT1_SHIFT 0 |
Bit Offset for Sub-Register CNT1.CNT1.
| #define CNT2_CNT2_MASK 0xFF |
Sub-registers of Register CNT2.
Bit Mask for Sub-Register CNT2.CNT2
| #define CNT2_CNT2_SHIFT 0 |
Bit Offset for Sub-Register CNT2.CNT2.
| #define CNT3_CNT3_MASK 0xFF |
Sub-registers of Register CNT3.
Bit Mask for Sub-Register CNT3.CNT3
| #define CNT3_CNT3_SHIFT 0 |
Bit Offset for Sub-Register CNT3.CNT3.
| #define CNTC_CAPRXS_MASK 0x08 |
Bit Mask for Sub-Register CNTC.CAPRXS.
Referenced by trx_config().
| #define CNTC_CAPRXS_SHIFT 3 |
Bit Offset for Sub-Register CNTC.CAPRXS.
| #define CNTC_CAPTXS_MASK 0x10 |
Bit Mask for Sub-Register CNTC.CAPTXS.
| #define CNTC_CAPTXS_SHIFT 4 |
Bit Offset for Sub-Register CNTC.CAPTXS.
| #define CNTC_EN_MASK 0x01 |
| #define CNTC_EN_SHIFT 0 |
Bit Offset for Sub-Register CNTC.EN.
| #define CNTC_RSTRXS_MASK 0x02 |
Bit Mask for Sub-Register CNTC.RSTRXS.
Referenced by trx_config().
| #define CNTC_RSTRXS_SHIFT 1 |
Bit Offset for Sub-Register CNTC.RSTRXS.
| #define CNTC_RSTTXS_MASK 0x04 |
Bit Mask for Sub-Register CNTC.RSTTXS.
Referenced by trx_config().
| #define CNTC_RSTTXS_SHIFT 2 |
Bit Offset for Sub-Register CNTC.RSTTXS.
| #define CS_CS_MASK 0xFF |
Sub-registers of Register CS.
Bit Mask for Sub-Register CS.CS
| #define CS_CS_SHIFT 0 |
Bit Offset for Sub-Register CS.CS.
| #define EDC_EDM_MASK 0x03 |
Sub-registers of Register EDC.
Bit Mask for Sub-Register EDC.EDM
| #define EDC_EDM_SHIFT 0 |
Bit Offset for Sub-Register EDC.EDM.
| #define EDD_DF_MASK 0xFC |
Bit Mask for Sub-Register EDD.DF.
| #define EDD_DF_SHIFT 2 |
Bit Offset for Sub-Register EDD.DF.
| #define EDD_DTB_MASK 0x03 |
Sub-registers of Register EDD.
Bit Mask for Sub-Register EDD.DTB
| #define EDD_DTB_SHIFT 0 |
Bit Offset for Sub-Register EDD.DTB.
| #define EDV_EDV_MASK 0xFF |
Sub-registers of Register EDV.
Bit Mask for Sub-Register EDV.EDV
| #define EDV_EDV_SHIFT 0 |
Bit Offset for Sub-Register EDV.EDV.
| #define FBLH_FBLH_MASK 0x07 |
Sub-registers of Register FBLH.
Bit Mask for Sub-Register FBLH.FBLH
| #define FBLH_FBLH_SHIFT 0 |
Bit Offset for Sub-Register FBLH.FBLH.
| #define FBLIH_FBLIH_MASK 0x07 |
Sub-registers of Register FBLIH.
Bit Mask for Sub-Register FBLIH.FBLIH
| #define FBLIH_FBLIH_SHIFT 0 |
Bit Offset for Sub-Register FBLIH.FBLIH.
| #define FBLIL_FBLIL_MASK 0xFF |
Sub-registers of Register FBLIL.
Bit Mask for Sub-Register FBLIL.FBLIL
| #define FBLIL_FBLIL_SHIFT 0 |
Bit Offset for Sub-Register FBLIL.FBLIL.
| #define FBLL_FBLL_MASK 0xFF |
Sub-registers of Register FBLL.
Bit Mask for Sub-Register FBLL.FBLL
| #define FBLL_FBLL_SHIFT 0 |
Bit Offset for Sub-Register FBLL.FBLL.
| #define FBRXE_FBRXE_MASK 0xFF |
Sub-registers of Register FBRXE.
Bit Mask for Sub-Register FBRXE.FBRXE
| #define FBRXE_FBRXE_SHIFT 0 |
Bit Offset for Sub-Register FBRXE.FBRXE.
| #define FBRXS_FBRXS_MASK 0xFF |
Sub-registers of Register FBRXS.
Bit Mask for Sub-Register FBRXS.FBRXS
| #define FBRXS_FBRXS_SHIFT 0 |
Bit Offset for Sub-Register FBRXS.FBRXS.
| #define FBTXE_FBTXE_MASK 0xFF |
Sub-registers of Register FBTXE.
Bit Mask for Sub-Register FBTXE.FBTXE
| #define FBTXE_FBTXE_SHIFT 0 |
Bit Offset for Sub-Register FBTXE.FBTXE.
| #define FBTXS_FBTXS_MASK 0xFF |
Sub-registers of Register FBTXS.
Bit Mask for Sub-Register FBTXS.FBTXS
| #define FBTXS_FBTXS_SHIFT 0 |
Bit Offset for Sub-Register FBTXS.FBTXS.
| #define FSKC0_BT_MASK 0xC0 |
Bit Mask for Sub-Register FSKC0.BT.
| #define FSKC0_BT_SHIFT 6 |
Bit Offset for Sub-Register FSKC0.BT.
| #define FSKC0_MIDX_MASK 0x0E |
Bit Mask for Sub-Register FSKC0.MIDX.
| #define FSKC0_MIDX_SHIFT 1 |
Bit Offset for Sub-Register FSKC0.MIDX.
| #define FSKC0_MIDXS_MASK 0x30 |
Bit Mask for Sub-Register FSKC0.MIDXS.
| #define FSKC0_MIDXS_SHIFT 4 |
Bit Offset for Sub-Register FSKC0.MIDXS.
| #define FSKC0_MORD_MASK 0x01 |
Sub-registers of Register FSKC0.
Bit Mask for Sub-Register FSKC0.MORD
| #define FSKC0_MORD_SHIFT 0 |
Bit Offset for Sub-Register FSKC0.MORD.
| #define FSKC1_FI_MASK 0x20 |
Bit Mask for Sub-Register FSKC1.FI.
| #define FSKC1_FI_SHIFT 5 |
Bit Offset for Sub-Register FSKC1.FI.
| #define FSKC1_FSKPLH_MASK 0xC0 |
Bit Mask for Sub-Register FSKC1.FSKPLH.
| #define FSKC1_FSKPLH_SHIFT 6 |
Bit Offset for Sub-Register FSKC1.FSKPLH.
| #define FSKC1_SRATE_MASK 0x0F |
Sub-registers of Register FSKC1.
Bit Mask for Sub-Register FSKC1.SRATE
| #define FSKC1_SRATE_SHIFT 0 |
Bit Offset for Sub-Register FSKC1.SRATE.
| #define FSKC2_FECIE_MASK 0x01 |
Sub-registers of Register FSKC2.
Bit Mask for Sub-Register FSKC2.FECIE
| #define FSKC2_FECIE_SHIFT 0 |
Bit Offset for Sub-Register FSKC2.FECIE.
| #define FSKC2_FECS_MASK 0x02 |
Bit Mask for Sub-Register FSKC2.FECS.
| #define FSKC2_FECS_SHIFT 1 |
Bit Offset for Sub-Register FSKC2.FECS.
| #define FSKC2_MSE_MASK 0x08 |
Bit Mask for Sub-Register FSKC2.MSE.
| #define FSKC2_MSE_SHIFT 3 |
Bit Offset for Sub-Register FSKC2.MSE.
| #define FSKC2_PDTM_MASK 0x80 |
Bit Mask for Sub-Register FSKC2.PDTM.
| #define FSKC2_PDTM_SHIFT 7 |
Bit Offset for Sub-Register FSKC2.PDTM.
| #define FSKC2_PRI_MASK 0x04 |
Bit Mask for Sub-Register FSKC2.PRI.
| #define FSKC2_PRI_SHIFT 2 |
Bit Offset for Sub-Register FSKC2.PRI.
| #define FSKC2_RXO_MASK 0x60 |
Bit Mask for Sub-Register FSKC2.RXO.
| #define FSKC2_RXO_SHIFT 5 |
Bit Offset for Sub-Register FSKC2.RXO.
| #define FSKC2_RXPTO_MASK 0x10 |
Bit Mask for Sub-Register FSKC2.RXPTO.
| #define FSKC2_RXPTO_SHIFT 4 |
Bit Offset for Sub-Register FSKC2.RXPTO.
| #define FSKC3_PDT_MASK 0x0F |
Sub-registers of Register FSKC3.
Bit Mask for Sub-Register FSKC3.PDT
| #define FSKC3_PDT_SHIFT 0 |
Bit Offset for Sub-Register FSKC3.PDT.
| #define FSKC3_SFDT_MASK 0xF0 |
Bit Mask for Sub-Register FSKC3.SFDT.
| #define FSKC3_SFDT_SHIFT 4 |
Bit Offset for Sub-Register FSKC3.SFDT.
| #define FSKC4_CSFD0_MASK 0x03 |
Sub-registers of Register FSKC4.
Bit Mask for Sub-Register FSKC4.CSFD0
| #define FSKC4_CSFD0_SHIFT 0 |
Bit Offset for Sub-Register FSKC4.CSFD0.
| #define FSKC4_CSFD1_MASK 0x0C |
Bit Mask for Sub-Register FSKC4.CSFD1.
| #define FSKC4_CSFD1_SHIFT 2 |
Bit Offset for Sub-Register FSKC4.CSFD1.
| #define FSKC4_RAWRBIT_MASK 0x10 |
Bit Mask for Sub-Register FSKC4.RAWRBIT.
| #define FSKC4_RAWRBIT_SHIFT 4 |
Bit Offset for Sub-Register FSKC4.RAWRBIT.
| #define FSKC4_SFD32_MASK 0x20 |
Bit Mask for Sub-Register FSKC4.SFD32.
| #define FSKC4_SFD32_SHIFT 5 |
Bit Offset for Sub-Register FSKC4.SFD32.
| #define FSKC4_SFDQ_MASK 0x40 |
Bit Mask for Sub-Register FSKC4.SFDQ.
| #define FSKC4_SFDQ_SHIFT 6 |
Bit Offset for Sub-Register FSKC4.SFDQ.
| #define FSKDM_EN_MASK 0x01 |
Sub-registers of Register FSKDM.
Bit Mask for Sub-Register FSKDM.EN
| #define FSKDM_EN_SHIFT 0 |
Bit Offset for Sub-Register FSKDM.EN.
Referenced by fsk_rfcfg().
| #define FSKDM_PE_MASK 0x02 |
Bit Mask for Sub-Register FSKDM.PE.
| #define FSKDM_PE_SHIFT 1 |
Bit Offset for Sub-Register FSKDM.PE.
Referenced by fsk_rfcfg().
| #define FSKPE0_FSKPE0_MASK 0xFF |
Sub-registers of Register FSKPE0.
Bit Mask for Sub-Register FSKPE0.FSKPE0
| #define FSKPE0_FSKPE0_SHIFT 0 |
Bit Offset for Sub-Register FSKPE0.FSKPE0.
| #define FSKPE1_FSKPE1_MASK 0xFF |
Sub-registers of Register FSKPE1.
Bit Mask for Sub-Register FSKPE1.FSKPE1
| #define FSKPE1_FSKPE1_SHIFT 0 |
Bit Offset for Sub-Register FSKPE1.FSKPE1.
| #define FSKPE2_FSKPE2_MASK 0xFF |
Sub-registers of Register FSKPE2.
Bit Mask for Sub-Register FSKPE2.FSKPE2
| #define FSKPE2_FSKPE2_SHIFT 0 |
Bit Offset for Sub-Register FSKPE2.FSKPE2.
| #define FSKPHRRX_DW_MASK 0x04 |
Bit Mask for Sub-Register FSKPHRRX.DW.
| #define FSKPHRRX_DW_SHIFT 2 |
Bit Offset for Sub-Register FSKPHRRX.DW.
| #define FSKPHRRX_FCST_MASK 0x80 |
Bit Mask for Sub-Register FSKPHRRX.FCST.
| #define FSKPHRRX_FCST_SHIFT 7 |
Bit Offset for Sub-Register FSKPHRRX.FCST.
| #define FSKPHRRX_MS_MASK 0x40 |
Bit Mask for Sub-Register FSKPHRRX.MS.
| #define FSKPHRRX_MS_SHIFT 6 |
Bit Offset for Sub-Register FSKPHRRX.MS.
| #define FSKPHRRX_RB1_MASK 0x01 |
Sub-registers of Register FSKPHRRX.
Bit Mask for Sub-Register FSKPHRRX.RB1
| #define FSKPHRRX_RB1_SHIFT 0 |
Bit Offset for Sub-Register FSKPHRRX.RB1.
| #define FSKPHRRX_RB2_MASK 0x02 |
Bit Mask for Sub-Register FSKPHRRX.RB2.
| #define FSKPHRRX_RB2_SHIFT 1 |
Bit Offset for Sub-Register FSKPHRRX.RB2.
| #define FSKPHRRX_SFD_MASK 0x08 |
Bit Mask for Sub-Register FSKPHRRX.SFD.
| #define FSKPHRRX_SFD_SHIFT 3 |
Bit Offset for Sub-Register FSKPHRRX.SFD.
| #define FSKPHRTX_DW_MASK 0x04 |
Bit Mask for Sub-Register FSKPHRTX.DW.
| #define FSKPHRTX_DW_SHIFT 2 |
Bit Offset for Sub-Register FSKPHRTX.DW.
| #define FSKPHRTX_RB1_MASK 0x01 |
Sub-registers of Register FSKPHRTX.
Bit Mask for Sub-Register FSKPHRTX.RB1
| #define FSKPHRTX_RB1_SHIFT 0 |
Bit Offset for Sub-Register FSKPHRTX.RB1.
| #define FSKPHRTX_RB2_MASK 0x02 |
Bit Mask for Sub-Register FSKPHRTX.RB2.
| #define FSKPHRTX_RB2_SHIFT 1 |
Bit Offset for Sub-Register FSKPHRTX.RB2.
| #define FSKPHRTX_SFD_MASK 0x08 |
Bit Mask for Sub-Register FSKPHRTX.SFD.
| #define FSKPHRTX_SFD_SHIFT 3 |
Bit Offset for Sub-Register FSKPHRTX.SFD.
| #define FSKPLL_FSKPLL_MASK 0xFF |
Sub-registers of Register FSKPLL.
Bit Mask for Sub-Register FSKPLL.FSKPLL
| #define FSKPLL_FSKPLL_SHIFT 0 |
Bit Offset for Sub-Register FSKPLL.FSKPLL.
| #define FSKRPC_BASET_MASK 0x07 |
Sub-registers of Register FSKRPC.
Bit Mask for Sub-Register FSKRPC.BASET
| #define FSKRPC_BASET_SHIFT 0 |
Bit Offset for Sub-Register FSKRPC.BASET.
| #define FSKRPC_EN_MASK 0x08 |
Bit Mask for Sub-Register FSKRPC.EN.
| #define FSKRPC_EN_SHIFT 3 |
Bit Offset for Sub-Register FSKRPC.EN.
| #define FSKRPCOFFT_FSKRPCOFFT_MASK 0xFF |
Sub-registers of Register FSKRPCOFFT.
Bit Mask for Sub-Register FSKRPCOFFT.FSKRPCOFFT
| #define FSKRPCOFFT_FSKRPCOFFT_SHIFT 0 |
Bit Offset for Sub-Register FSKRPCOFFT.FSKRPCOFFT.
| #define FSKRPCONT_FSKRPCONT_MASK 0xFF |
Sub-registers of Register FSKRPCONT.
Bit Mask for Sub-Register FSKRPCONT.FSKRPCONT
| #define FSKRPCONT_FSKRPCONT_SHIFT 0 |
Bit Offset for Sub-Register FSKRPCONT.FSKRPCONT.
| #define FSKRRXFLH_FSKRRXFLH_MASK 0x07 |
Sub-registers of Register FSKRRXFLH.
Bit Mask for Sub-Register FSKRRXFLH.FSKRRXFLH
| #define FSKRRXFLH_FSKRRXFLH_SHIFT 0 |
Bit Offset for Sub-Register FSKRRXFLH.FSKRRXFLH.
| #define FSKRRXFLL_FSKRRXFLL_MASK 0xFF |
Sub-registers of Register FSKRRXFLL.
Bit Mask for Sub-Register FSKRRXFLL.FSKRRXFLL
| #define FSKRRXFLL_FSKRRXFLL_SHIFT 0 |
Bit Offset for Sub-Register FSKRRXFLL.FSKRRXFLL.
| #define FSKSFD0H_FSKSFD0H_MASK 0xFF |
Sub-registers of Register FSKSFD0H.
Bit Mask for Sub-Register FSKSFD0H.FSKSFD0H
| #define FSKSFD0H_FSKSFD0H_SHIFT 0 |
Bit Offset for Sub-Register FSKSFD0H.FSKSFD0H.
| #define FSKSFD0L_FSKSFD0L_MASK 0xFF |
Sub-registers of Register FSKSFD0L.
Bit Mask for Sub-Register FSKSFD0L.FSKSFD0L
| #define FSKSFD0L_FSKSFD0L_SHIFT 0 |
Bit Offset for Sub-Register FSKSFD0L.FSKSFD0L.
| #define FSKSFD1H_FSKSFD1H_MASK 0xFF |
Sub-registers of Register FSKSFD1H.
Bit Mask for Sub-Register FSKSFD1H.FSKSFD1H
| #define FSKSFD1H_FSKSFD1H_SHIFT 0 |
Bit Offset for Sub-Register FSKSFD1H.FSKSFD1H.
| #define FSKSFD1L_FSKSFD1L_MASK 0xFF |
Sub-registers of Register FSKSFD1L.
Bit Mask for Sub-Register FSKSFD1L.FSKSFD1L
| #define FSKSFD1L_FSKSFD1L_SHIFT 0 |
Bit Offset for Sub-Register FSKSFD1L.FSKSFD1L.
| #define IQIFC0_CMV1V2_MASK 0x02 |
Bit Mask for Sub-Register IQIFC0.CMV1V2.
| #define IQIFC0_CMV1V2_SHIFT 1 |
Bit Offset for Sub-Register IQIFC0.CMV1V2.
| #define IQIFC0_CMV_MASK 0x0C |
Bit Mask for Sub-Register IQIFC0.CMV.
| #define IQIFC0_CMV_SHIFT 2 |
Bit Offset for Sub-Register IQIFC0.CMV.
| #define IQIFC0_DRV_MASK 0x30 |
Bit Mask for Sub-Register IQIFC0.DRV.
| #define IQIFC0_DRV_SHIFT 4 |
Bit Offset for Sub-Register IQIFC0.DRV.
| #define IQIFC0_EEC_MASK 0x01 |
Sub-registers of Register IQIFC0.
Bit Mask for Sub-Register IQIFC0.EEC
| #define IQIFC0_EEC_SHIFT 0 |
Bit Offset for Sub-Register IQIFC0.EEC.
| #define IQIFC0_EXTLB_MASK 0x80 |
Bit Mask for Sub-Register IQIFC0.EXTLB.
| #define IQIFC0_EXTLB_SHIFT 7 |
Bit Offset for Sub-Register IQIFC0.EXTLB.
| #define IQIFC0_SF_MASK 0x40 |
Bit Mask for Sub-Register IQIFC0.SF.
| #define IQIFC0_SF_SHIFT 6 |
Bit Offset for Sub-Register IQIFC0.SF.
| #define IQIFC1_CHPM_MASK 0x70 |
Bit Mask for Sub-Register IQIFC1.CHPM.
| #define IQIFC1_CHPM_SHIFT 4 |
Bit Offset for Sub-Register IQIFC1.CHPM.
| #define IQIFC1_FAILSF_MASK 0x80 |
Bit Mask for Sub-Register IQIFC1.FAILSF.
| #define IQIFC1_FAILSF_SHIFT 7 |
Bit Offset for Sub-Register IQIFC1.FAILSF.
| #define IQIFC1_SKEWDRV_MASK 0x03 |
Sub-registers of Register IQIFC1.
Bit Mask for Sub-Register IQIFC1.SKEWDRV
| #define IQIFC1_SKEWDRV_SHIFT 0 |
Bit Offset for Sub-Register IQIFC1.SKEWDRV.
| #define IQIFC2_SYNC_MASK 0x80 |
Sub-registers of Register IQIFC2.
Bit Mask for Sub-Register IQIFC2.SYNC
| #define IQIFC2_SYNC_SHIFT 7 |
Bit Offset for Sub-Register IQIFC2.SYNC.
| #define IRQM_AGCH_MASK 0x20 |
Bit Mask for Sub-Register IRQM.AGCH.
| #define IRQM_AGCH_SHIFT 5 |
Bit Offset for Sub-Register IRQM.AGCH.
| #define IRQM_AGCR_MASK 0x40 |
Bit Mask for Sub-Register IRQM.AGCR.
| #define IRQM_AGCR_SHIFT 6 |
Bit Offset for Sub-Register IRQM.AGCR.
| #define IRQM_BATLOW_MASK 0x08 |
Bit Mask for Sub-Register IRQM.BATLOW.
| #define IRQM_BATLOW_SHIFT 3 |
Bit Offset for Sub-Register IRQM.BATLOW.
| #define IRQM_EDC_MASK 0x04 |
Bit Mask for Sub-Register IRQM.EDC.
| #define IRQM_EDC_SHIFT 2 |
Bit Offset for Sub-Register IRQM.EDC.
| #define IRQM_FBLI_MASK 0x80 |
Bit Mask for Sub-Register IRQM.FBLI.
| #define IRQM_FBLI_SHIFT 7 |
Bit Offset for Sub-Register IRQM.FBLI.
| #define IRQM_IQIFSF_MASK 0x20 |
Bit Mask for Sub-Register IRQM.IQIFSF.
| #define IRQM_IQIFSF_SHIFT 5 |
Bit Offset for Sub-Register IRQM.IQIFSF.
| #define IRQM_RXAM_MASK 0x04 |
Bit Mask for Sub-Register IRQM.RXAM.
| #define IRQM_RXAM_SHIFT 2 |
Bit Offset for Sub-Register IRQM.RXAM.
| #define IRQM_RXEM_MASK 0x08 |
Bit Mask for Sub-Register IRQM.RXEM.
| #define IRQM_RXEM_SHIFT 3 |
Bit Offset for Sub-Register IRQM.RXEM.
| #define IRQM_RXFE_MASK 0x02 |
Bit Mask for Sub-Register IRQM.RXFE.
| #define IRQM_RXFE_SHIFT 1 |
Bit Offset for Sub-Register IRQM.RXFE.
| #define IRQM_RXFS_MASK 0x01 |
Sub-registers of Register IRQM.
Bit Mask for Sub-Register IRQM.RXFS
| #define IRQM_RXFS_SHIFT 0 |
Bit Offset for Sub-Register IRQM.RXFS.
| #define IRQM_TRXERR_MASK 0x10 |
Bit Mask for Sub-Register IRQM.TRXERR.
| #define IRQM_TRXERR_SHIFT 4 |
Bit Offset for Sub-Register IRQM.TRXERR.
| #define IRQM_TRXRDY_MASK 0x02 |
Bit Mask for Sub-Register IRQM.TRXRDY.
| #define IRQM_TRXRDY_SHIFT 1 |
Bit Offset for Sub-Register IRQM.TRXRDY.
| #define IRQM_TXFE_MASK 0x10 |
Bit Mask for Sub-Register IRQM.TXFE.
| #define IRQM_TXFE_SHIFT 4 |
Bit Offset for Sub-Register IRQM.TXFE.
| #define IRQM_WAKEUP_MASK 0x01 |
Sub-registers of Register IRQM.
Bit Mask for Sub-Register IRQM.WAKEUP
| #define IRQM_WAKEUP_SHIFT 0 |
Bit Offset for Sub-Register IRQM.WAKEUP.
| #define IRQS_AGCH_MASK 0x20 |
Bit Mask for Sub-Register IRQS.AGCH.
| #define IRQS_AGCH_SHIFT 5 |
Bit Offset for Sub-Register IRQS.AGCH.
| #define IRQS_AGCR_MASK 0x40 |
Bit Mask for Sub-Register IRQS.AGCR.
| #define IRQS_AGCR_SHIFT 6 |
Bit Offset for Sub-Register IRQS.AGCR.
| #define IRQS_BATLOW_MASK 0x08 |
Bit Mask for Sub-Register IRQS.BATLOW.
| #define IRQS_BATLOW_SHIFT 3 |
Bit Offset for Sub-Register IRQS.BATLOW.
| #define IRQS_EDC_MASK 0x04 |
Bit Mask for Sub-Register IRQS.EDC.
| #define IRQS_EDC_SHIFT 2 |
Bit Offset for Sub-Register IRQS.EDC.
| #define IRQS_FBLI_MASK 0x80 |
Bit Mask for Sub-Register IRQS.FBLI.
| #define IRQS_FBLI_SHIFT 7 |
Bit Offset for Sub-Register IRQS.FBLI.
| #define IRQS_IQIFSF_MASK 0x20 |
Bit Mask for Sub-Register IRQS.IQIFSF.
| #define IRQS_IQIFSF_SHIFT 5 |
Bit Offset for Sub-Register IRQS.IQIFSF.
| #define IRQS_RXAM_MASK 0x04 |
Bit Mask for Sub-Register IRQS.RXAM.
| #define IRQS_RXAM_SHIFT 2 |
Bit Offset for Sub-Register IRQS.RXAM.
| #define IRQS_RXEM_MASK 0x08 |
Bit Mask for Sub-Register IRQS.RXEM.
| #define IRQS_RXEM_SHIFT 3 |
Bit Offset for Sub-Register IRQS.RXEM.
| #define IRQS_RXFE_MASK 0x02 |
Bit Mask for Sub-Register IRQS.RXFE.
| #define IRQS_RXFE_SHIFT 1 |
Bit Offset for Sub-Register IRQS.RXFE.
| #define IRQS_RXFS_MASK 0x01 |
Sub-registers of Register IRQS.
Bit Mask for Sub-Register IRQS.RXFS
| #define IRQS_RXFS_SHIFT 0 |
Bit Offset for Sub-Register IRQS.RXFS.
| #define IRQS_TRXERR_MASK 0x10 |
Bit Mask for Sub-Register IRQS.TRXERR.
| #define IRQS_TRXERR_SHIFT 4 |
Bit Offset for Sub-Register IRQS.TRXERR.
| #define IRQS_TRXRDY_MASK 0x02 |
Bit Mask for Sub-Register IRQS.TRXRDY.
| #define IRQS_TRXRDY_SHIFT 1 |
Bit Offset for Sub-Register IRQS.TRXRDY.
| #define IRQS_TXFE_MASK 0x10 |
Bit Mask for Sub-Register IRQS.TXFE.
| #define IRQS_TXFE_SHIFT 4 |
Bit Offset for Sub-Register IRQS.TXFE.
| #define IRQS_WAKEUP_MASK 0x01 |
Subregister Type Definitions (MASK, SHIFT)
Sub-registers of Register IRQS Bit Mask for Sub-Register IRQS.WAKEUP
| #define IRQS_WAKEUP_SHIFT 0 |
Bit Offset for Sub-Register IRQS.WAKEUP.
| #define MACEA0_MACEA0_MASK 0xFF |
Sub-registers of Register MACEA0.
Bit Mask for Sub-Register MACEA0.MACEA0
| #define MACEA0_MACEA0_SHIFT 0 |
Bit Offset for Sub-Register MACEA0.MACEA0.
| #define MACEA1_MACEA1_MASK 0xFF |
Sub-registers of Register MACEA1.
Bit Mask for Sub-Register MACEA1.MACEA1
| #define MACEA1_MACEA1_SHIFT 0 |
Bit Offset for Sub-Register MACEA1.MACEA1.
| #define MACEA2_MACEA2_MASK 0xFF |
Sub-registers of Register MACEA2.
Bit Mask for Sub-Register MACEA2.MACEA2
| #define MACEA2_MACEA2_SHIFT 0 |
Bit Offset for Sub-Register MACEA2.MACEA2.
| #define MACEA3_MACEA3_MASK 0xFF |
Sub-registers of Register MACEA3.
Bit Mask for Sub-Register MACEA3.MACEA3
| #define MACEA3_MACEA3_SHIFT 0 |
Bit Offset for Sub-Register MACEA3.MACEA3.
| #define MACEA4_MACEA4_MASK 0xFF |
Sub-registers of Register MACEA4.
Bit Mask for Sub-Register MACEA4.MACEA4
| #define MACEA4_MACEA4_SHIFT 0 |
Bit Offset for Sub-Register MACEA4.MACEA4.
| #define MACEA5_MACEA5_MASK 0xFF |
Sub-registers of Register MACEA5.
Bit Mask for Sub-Register MACEA5.MACEA5
| #define MACEA5_MACEA5_SHIFT 0 |
Bit Offset for Sub-Register MACEA5.MACEA5.
| #define MACEA6_MACEA6_MASK 0xFF |
Sub-registers of Register MACEA6.
Bit Mask for Sub-Register MACEA6.MACEA6
| #define MACEA6_MACEA6_SHIFT 0 |
Bit Offset for Sub-Register MACEA6.MACEA6.
| #define MACEA7_MACEA7_MASK 0xFF |
Sub-registers of Register MACEA7.
Bit Mask for Sub-Register MACEA7.MACEA7
| #define MACEA7_MACEA7_SHIFT 0 |
Bit Offset for Sub-Register MACEA7.MACEA7.
| #define MACPID0F0_MACPID0F0_MASK 0xFF |
Sub-registers of Register MACPID0F0.
Bit Mask for Sub-Register MACPID0F0.MACPID0F0
| #define MACPID0F0_MACPID0F0_SHIFT 0 |
Bit Offset for Sub-Register MACPID0F0.MACPID0F0.
| #define MACPID0F1_MACPID0F1_MASK 0xFF |
Sub-registers of Register MACPID0F1.
Bit Mask for Sub-Register MACPID0F1.MACPID0F1
| #define MACPID0F1_MACPID0F1_SHIFT 0 |
Bit Offset for Sub-Register MACPID0F1.MACPID0F1.
| #define MACPID0F2_MACPID0F2_MASK 0xFF |
Sub-registers of Register MACPID0F2.
Bit Mask for Sub-Register MACPID0F2.MACPID0F2
| #define MACPID0F2_MACPID0F2_SHIFT 0 |
Bit Offset for Sub-Register MACPID0F2.MACPID0F2.
| #define MACPID0F3_MACPID0F3_MASK 0xFF |
Sub-registers of Register MACPID0F3.
Bit Mask for Sub-Register MACPID0F3.MACPID0F3
| #define MACPID0F3_MACPID0F3_SHIFT 0 |
Bit Offset for Sub-Register MACPID0F3.MACPID0F3.
| #define MACPID1F0_MACPID1F0_MASK 0xFF |
Sub-registers of Register MACPID1F0.
Bit Mask for Sub-Register MACPID1F0.MACPID1F0
| #define MACPID1F0_MACPID1F0_SHIFT 0 |
Bit Offset for Sub-Register MACPID1F0.MACPID1F0.
| #define MACPID1F1_MACPID1F1_MASK 0xFF |
Sub-registers of Register MACPID1F1.
Bit Mask for Sub-Register MACPID1F1.MACPID1F1
| #define MACPID1F1_MACPID1F1_SHIFT 0 |
Bit Offset for Sub-Register MACPID1F1.MACPID1F1.
| #define MACPID1F2_MACPID1F2_MASK 0xFF |
Sub-registers of Register MACPID1F2.
Bit Mask for Sub-Register MACPID1F2.MACPID1F2
| #define MACPID1F2_MACPID1F2_SHIFT 0 |
Bit Offset for Sub-Register MACPID1F2.MACPID1F2.
| #define MACPID1F3_MACPID1F3_MASK 0xFF |
Sub-registers of Register MACPID1F3.
Bit Mask for Sub-Register MACPID1F3.MACPID1F3
| #define MACPID1F3_MACPID1F3_SHIFT 0 |
Bit Offset for Sub-Register MACPID1F3.MACPID1F3.
| #define MACSHA0F0_MACSHA0F0_MASK 0xFF |
Sub-registers of Register MACSHA0F0.
Bit Mask for Sub-Register MACSHA0F0.MACSHA0F0
| #define MACSHA0F0_MACSHA0F0_SHIFT 0 |
Bit Offset for Sub-Register MACSHA0F0.MACSHA0F0.
| #define MACSHA0F1_MACSHA0F1_MASK 0xFF |
Sub-registers of Register MACSHA0F1.
Bit Mask for Sub-Register MACSHA0F1.MACSHA0F1
| #define MACSHA0F1_MACSHA0F1_SHIFT 0 |
Bit Offset for Sub-Register MACSHA0F1.MACSHA0F1.
| #define MACSHA0F2_MACSHA0F2_MASK 0xFF |
Sub-registers of Register MACSHA0F2.
Bit Mask for Sub-Register MACSHA0F2.MACSHA0F2
| #define MACSHA0F2_MACSHA0F2_SHIFT 0 |
Bit Offset for Sub-Register MACSHA0F2.MACSHA0F2.
| #define MACSHA0F3_MACSHA0F3_MASK 0xFF |
Sub-registers of Register MACSHA0F3.
Bit Mask for Sub-Register MACSHA0F3.MACSHA0F3
| #define MACSHA0F3_MACSHA0F3_SHIFT 0 |
Bit Offset for Sub-Register MACSHA0F3.MACSHA0F3.
| #define MACSHA1F0_MACSHA1F0_MASK 0xFF |
Sub-registers of Register MACSHA1F0.
Bit Mask for Sub-Register MACSHA1F0.MACSHA1F0
| #define MACSHA1F0_MACSHA1F0_SHIFT 0 |
Bit Offset for Sub-Register MACSHA1F0.MACSHA1F0.
| #define MACSHA1F1_MACSHA1F1_MASK 0xFF |
Sub-registers of Register MACSHA1F1.
Bit Mask for Sub-Register MACSHA1F1.MACSHA1F1
| #define MACSHA1F1_MACSHA1F1_SHIFT 0 |
Bit Offset for Sub-Register MACSHA1F1.MACSHA1F1.
| #define MACSHA1F2_MACSHA1F2_MASK 0xFF |
Sub-registers of Register MACSHA1F2.
Bit Mask for Sub-Register MACSHA1F2.MACSHA1F2
| #define MACSHA1F2_MACSHA1F2_SHIFT 0 |
Bit Offset for Sub-Register MACSHA1F2.MACSHA1F2.
| #define MACSHA1F3_MACSHA1F3_MASK 0xFF |
Sub-registers of Register MACSHA1F3.
Bit Mask for Sub-Register MACSHA1F3.MACSHA1F3
| #define MACSHA1F3_MACSHA1F3_SHIFT 0 |
Bit Offset for Sub-Register MACSHA1F3.MACSHA1F3.
| #define OFDMC_LFO_MASK 0x08 |
Bit Mask for Sub-Register OFDMC.LFO.
| #define OFDMC_LFO_SHIFT 3 |
Bit Offset for Sub-Register OFDMC.LFO.
| #define OFDMC_OPT_MASK 0x03 |
Sub-registers of Register OFDMC.
Bit Mask for Sub-Register OFDMC.OPT
| #define OFDMC_OPT_SHIFT 0 |
Bit Offset for Sub-Register OFDMC.OPT.
| #define OFDMC_POI_MASK 0x04 |
Bit Mask for Sub-Register OFDMC.POI.
| #define OFDMC_POI_SHIFT 2 |
Bit Offset for Sub-Register OFDMC.POI.
| #define OFDMC_SSRX_MASK 0xC0 |
Bit Mask for Sub-Register OFDMC.SSRX.
| #define OFDMC_SSRX_SHIFT 6 |
Bit Offset for Sub-Register OFDMC.SSRX.
| #define OFDMC_SSTX_MASK 0x30 |
Bit Mask for Sub-Register OFDMC.SSTX.
| #define OFDMC_SSTX_SHIFT 4 |
Bit Offset for Sub-Register OFDMC.SSTX.
| #define OFDMPHRRX_MCS_MASK 0x07 |
Sub-registers of Register OFDMPHRRX.
Bit Mask for Sub-Register OFDMPHRRX.MCS
| #define OFDMPHRRX_MCS_SHIFT 0 |
Bit Offset for Sub-Register OFDMPHRRX.MCS.
| #define OFDMPHRRX_RB17_MASK 0x20 |
Bit Mask for Sub-Register OFDMPHRRX.RB17.
| #define OFDMPHRRX_RB17_SHIFT 5 |
Bit Offset for Sub-Register OFDMPHRRX.RB17.
| #define OFDMPHRRX_RB18_MASK 0x40 |
Bit Mask for Sub-Register OFDMPHRRX.RB18.
| #define OFDMPHRRX_RB18_SHIFT 6 |
Bit Offset for Sub-Register OFDMPHRRX.RB18.
| #define OFDMPHRRX_RB21_MASK 0x80 |
Bit Mask for Sub-Register OFDMPHRRX.RB21.
| #define OFDMPHRRX_RB21_SHIFT 7 |
Bit Offset for Sub-Register OFDMPHRRX.RB21.
| #define OFDMPHRRX_RB5_MASK 0x10 |
Bit Mask for Sub-Register OFDMPHRRX.RB5.
| #define OFDMPHRRX_RB5_SHIFT 4 |
Bit Offset for Sub-Register OFDMPHRRX.RB5.
| #define OFDMPHRRX_SPC_MASK 0x08 |
Bit Mask for Sub-Register OFDMPHRRX.SPC.
| #define OFDMPHRRX_SPC_SHIFT 3 |
Bit Offset for Sub-Register OFDMPHRRX.SPC.
| #define OFDMPHRTX_MCS_MASK 0x07 |
Sub-registers of Register OFDMPHRTX.
Bit Mask for Sub-Register OFDMPHRTX.MCS
| #define OFDMPHRTX_MCS_SHIFT 0 |
Bit Offset for Sub-Register OFDMPHRTX.MCS.
| #define OFDMPHRTX_RB17_MASK 0x20 |
Bit Mask for Sub-Register OFDMPHRTX.RB17.
| #define OFDMPHRTX_RB17_SHIFT 5 |
Bit Offset for Sub-Register OFDMPHRTX.RB17.
| #define OFDMPHRTX_RB18_MASK 0x40 |
Bit Mask for Sub-Register OFDMPHRTX.RB18.
| #define OFDMPHRTX_RB18_SHIFT 6 |
Bit Offset for Sub-Register OFDMPHRTX.RB18.
| #define OFDMPHRTX_RB21_MASK 0x80 |
Bit Mask for Sub-Register OFDMPHRTX.RB21.
| #define OFDMPHRTX_RB21_SHIFT 7 |
Bit Offset for Sub-Register OFDMPHRTX.RB21.
| #define OFDMPHRTX_RB5_MASK 0x10 |
Bit Mask for Sub-Register OFDMPHRTX.RB5.
| #define OFDMPHRTX_RB5_SHIFT 4 |
Bit Offset for Sub-Register OFDMPHRTX.RB5.
| #define OFDMSW_PDT_MASK 0xE0 |
Bit Mask for Sub-Register OFDMSW.PDT.
| #define OFDMSW_PDT_SHIFT 5 |
Bit Offset for Sub-Register OFDMSW.PDT.
| #define OFDMSW_RXO_MASK 0x10 |
Sub-registers of Register OFDMSW.
Bit Mask for Sub-Register OFDMSW.RXO
| #define OFDMSW_RXO_SHIFT 4 |
Bit Offset for Sub-Register OFDMSW.RXO.
| #define OQPSKC0_DM_MASK 0x10 |
Bit Mask for Sub-Register OQPSKC0.DM.
| #define OQPSKC0_DM_SHIFT 4 |
Bit Offset for Sub-Register OQPSKC0.DM.
| #define OQPSKC0_FCHIP_MASK 0x03 |
Sub-registers of Register OQPSKC0.
Bit Mask for Sub-Register OQPSKC0.FCHIP
| #define OQPSKC0_FCHIP_SHIFT 0 |
Bit Offset for Sub-Register OQPSKC0.FCHIP.
| #define OQPSKC0_MOD_MASK 0x08 |
Bit Mask for Sub-Register OQPSKC0.MOD.
| #define OQPSKC0_MOD_SHIFT 3 |
Bit Offset for Sub-Register OQPSKC0.MOD.
| #define OQPSKC1_PDT0_MASK 0x07 |
Sub-registers of Register OQPSKC1.
Bit Mask for Sub-Register OQPSKC1.PDT0
| #define OQPSKC1_PDT0_SHIFT 0 |
Bit Offset for Sub-Register OQPSKC1.PDT0.
| #define OQPSKC1_PDT1_MASK 0x38 |
Bit Mask for Sub-Register OQPSKC1.PDT1.
| #define OQPSKC1_PDT1_SHIFT 3 |
Bit Offset for Sub-Register OQPSKC1.PDT1.
| #define OQPSKC1_RXO_MASK 0x80 |
Bit Mask for Sub-Register OQPSKC1.RXO.
| #define OQPSKC1_RXO_SHIFT 7 |
Bit Offset for Sub-Register OQPSKC1.RXO.
| #define OQPSKC1_RXOLEG_MASK 0x40 |
Bit Mask for Sub-Register OQPSKC1.RXOLEG.
| #define OQPSKC1_RXOLEG_SHIFT 6 |
Bit Offset for Sub-Register OQPSKC1.RXOLEG.
| #define OQPSKC2_ENPROP_MASK 0x08 |
Bit Mask for Sub-Register OQPSKC2.ENPROP.
| #define OQPSKC2_ENPROP_SHIFT 3 |
Bit Offset for Sub-Register OQPSKC2.ENPROP.
| #define OQPSKC2_FCSTLEG_MASK 0x04 |
Bit Mask for Sub-Register OQPSKC2.FCSTLEG.
| #define OQPSKC2_FCSTLEG_SHIFT 2 |
Bit Offset for Sub-Register OQPSKC2.FCSTLEG.
| #define OQPSKC2_RPC_MASK 0x10 |
Bit Mask for Sub-Register OQPSKC2.RPC.
| #define OQPSKC2_RPC_SHIFT 4 |
Bit Offset for Sub-Register OQPSKC2.RPC.
| #define OQPSKC2_RXM_MASK 0x03 |
Sub-registers of Register OQPSKC2.
Bit Mask for Sub-Register OQPSKC2.RXM
| #define OQPSKC2_RXM_SHIFT 0 |
Bit Offset for Sub-Register OQPSKC2.RXM.
| #define OQPSKC2_SPC_MASK 0x20 |
Bit Mask for Sub-Register OQPSKC2.SPC.
| #define OQPSKC2_SPC_SHIFT 5 |
Bit Offset for Sub-Register OQPSKC2.SPC.
| #define OQPSKC3_HRLEG_MASK 0x20 |
Bit Mask for Sub-Register OQPSKC3.HRLEG.
| #define OQPSKC3_HRLEG_SHIFT 5 |
Bit Offset for Sub-Register OQPSKC3.HRLEG.
| #define OQPSKC3_NSFD_MASK 0x0C |
Sub-registers of Register OQPSKC3.
Bit Mask for Sub-Register OQPSKC3.NSFD
| #define OQPSKC3_NSFD_SHIFT 2 |
Bit Offset for Sub-Register OQPSKC3.NSFD.
| #define OQPSKPHRRX_LEG_MASK 0x01 |
Sub-registers of Register OQPSKPHRRX.
Bit Mask for Sub-Register OQPSKPHRRX.LEG
| #define OQPSKPHRRX_LEG_SHIFT 0 |
Bit Offset for Sub-Register OQPSKPHRRX.LEG.
| #define OQPSKPHRRX_MOD_MASK 0x0E |
Bit Mask for Sub-Register OQPSKPHRRX.MOD.
| #define OQPSKPHRRX_MOD_SHIFT 1 |
Bit Offset for Sub-Register OQPSKPHRRX.MOD.
| #define OQPSKPHRRX_PPDUT_MASK 0x20 |
Bit Mask for Sub-Register OQPSKPHRRX.PPDUT.
| #define OQPSKPHRRX_PPDUT_SHIFT 5 |
Bit Offset for Sub-Register OQPSKPHRRX.PPDUT.
| #define OQPSKPHRRX_RB0_MASK 0x10 |
Bit Mask for Sub-Register OQPSKPHRRX.RB0.
| #define OQPSKPHRRX_RB0_SHIFT 4 |
Bit Offset for Sub-Register OQPSKPHRRX.RB0.
| #define OQPSKPHRTX_LEG_MASK 0x01 |
Sub-registers of Register OQPSKPHRTX.
Bit Mask for Sub-Register OQPSKPHRTX.LEG
| #define OQPSKPHRTX_LEG_SHIFT 0 |
Bit Offset for Sub-Register OQPSKPHRTX.LEG.
| #define OQPSKPHRTX_MOD_MASK 0x0E |
Bit Mask for Sub-Register OQPSKPHRTX.MOD.
| #define OQPSKPHRTX_MOD_SHIFT 1 |
Bit Offset for Sub-Register OQPSKPHRTX.MOD.
| #define OQPSKPHRTX_PPDUT_MASK 0x20 |
Bit Mask for Sub-Register OQPSKPHRTX.PPDUT.
| #define OQPSKPHRTX_PPDUT_SHIFT 5 |
Bit Offset for Sub-Register OQPSKPHRTX.PPDUT.
| #define OQPSKPHRTX_RB0_MASK 0x10 |
Bit Mask for Sub-Register OQPSKPHRTX.RB0.
| #define OQPSKPHRTX_RB0_SHIFT 4 |
Bit Offset for Sub-Register OQPSKPHRTX.RB0.
| #define PAC_PACUR_MASK 0x60 |
Bit Mask for Sub-Register PAC.PACUR.
| #define PAC_PACUR_SHIFT 5 |
Bit Offset for Sub-Register PAC.PACUR.
Referenced by fsk_rfcfg(), ofdm_rfcfg(), and oqpsk_rfcfg().
| #define PAC_TXPWR_MASK 0x1F |
Sub-registers of Register PAC.
Bit Mask for Sub-Register PAC.TXPWR
| #define PAC_TXPWR_SHIFT 0 |
Bit Offset for Sub-Register PAC.TXPWR.
Referenced by fsk_rfcfg(), ofdm_rfcfg(), and oqpsk_rfcfg().
| #define PADFE_PADFE_MASK 0xC0 |
Sub-registers of Register PADFE.
Bit Mask for Sub-Register PADFE.PADFE
| #define PADFE_PADFE_SHIFT 6 |
Bit Offset for Sub-Register PADFE.PADFE.
| #define PC_BBEN_MASK 0x04 |
Bit Mask for Sub-Register PC.BBEN.
Referenced by transmit_frame().
| #define PC_BBEN_SHIFT 2 |
Bit Offset for Sub-Register PC.BBEN.
| #define PC_CTX_MASK 0x80 |
Bit Mask for Sub-Register PC.CTX.
| #define PC_CTX_SHIFT 7 |
Bit Offset for Sub-Register PC.CTX.
| #define PC_FCSFE_MASK 0x40 |
Bit Mask for Sub-Register PC.FCSFE.
| #define PC_FCSFE_SHIFT 6 |
Bit Offset for Sub-Register PC.FCSFE.
| #define PC_FCSOK_MASK 0x20 |
Bit Mask for Sub-Register PC.FCSOK.
| #define PC_FCSOK_SHIFT 5 |
Bit Offset for Sub-Register PC.FCSOK.
| #define PC_FCST_MASK 0x08 |
Bit Mask for Sub-Register PC.FCST.
| #define PC_FCST_SHIFT 3 |
Bit Offset for Sub-Register PC.FCST.
| #define PC_PT_MASK 0x03 |
Sub-registers of Register PC.
Bit Mask for Sub-Register PC.PT
| #define PC_PT_SHIFT 0 |
Bit Offset for Sub-Register PC.PT.
| #define PC_TXAFCS_MASK 0x10 |
Bit Mask for Sub-Register PC.TXAFCS.
Referenced by transmit_frame().
| #define PC_TXAFCS_SHIFT 4 |
Bit Offset for Sub-Register PC.TXAFCS.
| #define PLL_LBW_MASK 0x30 |
Bit Mask for Sub-Register PLL.LBW.
| #define PLL_LBW_SHIFT 4 |
Bit Offset for Sub-Register PLL.LBW.
| #define PLL_LS_MASK 0x02 |
Sub-registers of Register PLL.
Bit Mask for Sub-Register PLL.LS
| #define PLL_LS_SHIFT 1 |
Bit Offset for Sub-Register PLL.LS.
| #define PLLCF_CF_MASK 0x3F |
Sub-registers of Register PLLCF.
Bit Mask for Sub-Register PLLCF.CF
| #define PLLCF_CF_SHIFT 0 |
Bit Offset for Sub-Register PLLCF.CF.
| #define PMUC_AVG_MASK 0x02 |
Bit Mask for Sub-Register PMUC.AVG.
| #define PMUC_AVG_SHIFT 1 |
Bit Offset for Sub-Register PMUC.AVG.
| #define PMUC_CCFTS_MASK 0x80 |
Bit Mask for Sub-Register PMUC.CCFTS.
| #define PMUC_CCFTS_SHIFT 7 |
Bit Offset for Sub-Register PMUC.CCFTS.
| #define PMUC_EN_MASK 0x01 |
Sub-registers of Register PMUC.
Bit Mask for Sub-Register PMUC.EN
| #define PMUC_EN_SHIFT 0 |
Bit Offset for Sub-Register PMUC.EN.
| #define PMUC_FED_MASK 0x20 |
Bit Mask for Sub-Register PMUC.FED.
| #define PMUC_FED_SHIFT 5 |
Bit Offset for Sub-Register PMUC.FED.
| #define PMUC_IQSEL_MASK 0x40 |
Bit Mask for Sub-Register PMUC.IQSEL.
| #define PMUC_IQSEL_SHIFT 6 |
Bit Offset for Sub-Register PMUC.IQSEL.
| #define PMUC_SYNC_MASK 0x1C |
Bit Mask for Sub-Register PMUC.SYNC.
| #define PMUC_SYNC_SHIFT 2 |
Bit Offset for Sub-Register PMUC.SYNC.
| #define PMUI_PMUI_MASK 0xFF |
Sub-registers of Register PMUI.
Bit Mask for Sub-Register PMUI.PMUI
| #define PMUI_PMUI_SHIFT 0 |
Bit Offset for Sub-Register PMUI.PMUI.
| #define PMUQ_PMUQ_MASK 0xFF |
Sub-registers of Register PMUQ.
Bit Mask for Sub-Register PMUQ.PMUQ
| #define PMUQ_PMUQ_SHIFT 0 |
Bit Offset for Sub-Register PMUQ.PMUQ.
| #define PMUQF_PMUQF_MASK 0xFF |
Sub-registers of Register PMUQF.
Bit Mask for Sub-Register PMUQF.PMUQF
| #define PMUQF_PMUQF_SHIFT 0 |
Bit Offset for Sub-Register PMUQF.PMUQF.
| #define PMUVAL_PMUVAL_MASK 0xFF |
Sub-registers of Register PMUVAL.
Bit Mask for Sub-Register PMUVAL.PMUVAL
| #define PMUVAL_PMUVAL_SHIFT 0 |
Bit Offset for Sub-Register PMUVAL.PMUVAL.
| #define PN_PN_MASK 0xFF |
Sub-registers of Register PN.
Bit Mask for Sub-Register PN.PN
| #define PN_PN_SHIFT 0 |
Bit Offset for Sub-Register PN.PN.
| #define PS_TXUR_MASK 0x01 |
Sub-registers of Register PS.
Bit Mask for Sub-Register PS.TXUR
| #define PS_TXUR_SHIFT 0 |
Bit Offset for Sub-Register PS.TXUR.
| #define RF_BW1000KHZ_IF1000KHZ (0x8) |
Constant BW1000KHZ_IF1000KHZ for sub-register SR_BW in register RF09_RXBWC.
Referenced by oqpsk_rfcfg().
| #define RF_BW1250KHZ_IF2000KHZ (0x9) |
Constant BW1250KHZ_IF2000KHZ for sub-register SR_BW in register RF09_RXBWC.
| #define RF_BW1600KHZ_IF2000KHZ (0xA) |
Constant BW1600KHZ_IF2000KHZ for sub-register SR_BW in register RF09_RXBWC.
| #define RF_BW160KHZ_IF250KHZ (0x0) |
Constant BW160KHZ_IF250KHZ for sub-register SR_BW in register RF09_RXBWC.
Referenced by oqpsk_rfcfg().
| #define RF_BW2000KHZ_IF2000KHZ (0xB) |
Constant BW2000KHZ_IF2000KHZ for sub-register SR_BW in register RF09_RXBWC.
Referenced by oqpsk_rfcfg().
| #define RF_BW200KHZ_IF250KHZ (0x1) |
Constant BW200KHZ_IF250KHZ for sub-register SR_BW in register RF09_RXBWC.
| #define RF_BW250KHZ_IF250KHZ (0x2) |
Constant BW250KHZ_IF250KHZ for sub-register SR_BW in register RF09_RXBWC.
Referenced by oqpsk_rfcfg().
| #define RF_BW320KHZ_IF500KHZ (0x3) |
Constant BW320KHZ_IF500KHZ for sub-register SR_BW in register RF09_RXBWC.
| #define RF_BW400KHZ_IF500KHZ (0x4) |
Constant BW400KHZ_IF500KHZ for sub-register SR_BW in register RF09_RXBWC.
| #define RF_BW500KHZ_IF500KHZ (0x5) |
Constant BW500KHZ_IF500KHZ for sub-register SR_BW in register RF09_RXBWC.
| #define RF_BW630KHZ_IF1000KHZ (0x6) |
Constant BW630KHZ_IF1000KHZ for sub-register SR_BW in register RF09_RXBWC.
| #define RF_BW800KHZ_IF1000KHZ (0x7) |
Constant BW800KHZ_IF1000KHZ for sub-register SR_BW in register RF09_RXBWC.
| #define RF_DRV2 (0x0) |
Constant DRV2 for sub-register SR_DRV in register RF_CFG.
| #define RF_DRV4 (0x1) |
Constant DRV4 for sub-register SR_DRV in register RF_CFG.
| #define RF_DRV6 (0x2) |
Constant DRV6 for sub-register SR_DRV in register RF_CFG.
| #define RF_DRV8 (0x3) |
Constant DRV8 for sub-register SR_DRV in register RF_CFG.
| #define RF_DRVCLKO2 (0x0) |
Constant DRVCLKO2 for sub-register SR_DRV in register RF_CLKO.
| #define RF_DRVCLKO4 (0x1) |
Constant DRVCLKO4 for sub-register SR_DRV in register RF_CLKO.
| #define RF_DRVCLKO6 (0x2) |
Constant DRVCLKO6 for sub-register SR_DRV in register RF_CLKO.
| #define RF_DRVCLKO8 (0x3) |
Constant DRVCLKO8 for sub-register SR_DRV in register RF_CLKO.
| #define RF_EDAUTO (0x0) |
Constant EDAUTO for sub-register SR_EDM in register RF09_EDC.
Referenced by handle_ed_end_irq().
| #define RF_EDCONT (0x2) |
Constant EDCONT for sub-register SR_EDM in register RF09_EDC.
| #define RF_EDOFF (0x3) |
Constant EDOFF for sub-register SR_EDM in register RF09_EDC.
| #define RF_EDSINGLE (0x1) |
Constant EDSINGLE for sub-register SR_EDM in register RF09_EDC.
Referenced by transmit_frame().
| #define RF_FEMODE0 (0x0) |
Constant FEMODE0 for sub-register SR_PADFE in register RF09_PADFE.
| #define RF_FEMODE1 (0x1) |
Constant FEMODE1 for sub-register SR_PADFE in register RF09_PADFE.
| #define RF_FEMODE2 (0x2) |
Constant FEMODE2 for sub-register SR_PADFE in register RF09_PADFE.
| #define RF_FEMODE3 (0x3) |
Constant FEMODE3 for sub-register SR_PADFE in register RF09_PADFE.
| #define RF_FLC1000KHZ (0xB) |
Constant FLC1000KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC.
Referenced by oqpsk_rfcfg().
| #define RF_FLC100KHZ (0x1) |
Constant FLC100KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC.
| #define RF_FLC125KHZ (0x2) |
Constant FLC125KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC.
| #define RF_FLC160KHZ (0x3) |
Constant FLC160KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC.
| #define RF_FLC200KHZ (0x4) |
Constant FLC200KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC.
| #define RF_FLC250KHZ (0x5) |
Constant FLC250KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC.
| #define RF_FLC315KHZ (0x6) |
Constant FLC315KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC.
| #define RF_FLC400KHZ (0x7) |
Constant FLC400KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC.
Referenced by oqpsk_rfcfg().
| #define RF_FLC500KHZ (0x8) |
Constant FLC500KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC.
| #define RF_FLC625KHZ (0x9) |
Constant FLC625KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC.
| #define RF_FLC800KHZ (0xA) |
Constant FLC800KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC.
| #define RF_FLC80KHZ (0x0) |
Constant FLC80KHZ for sub-register SR_LPFCUT in register RF09_TXCUTC.
| #define RF_MODE_BBRF (0x0) |
Constant MODE_BBRF for sub-register SR_CHPM in register RF_IQIFC1.
| #define RF_MODE_BBRF09 (0x4) |
Constant MODE_BBRF09 for sub-register SR_CHPM in register RF_IQIFC1.
| #define RF_MODE_BBRF24 (0x5) |
Constant MODE_BBRF24 for sub-register SR_CHPM in register RF_IQIFC1.
| #define RF_MODE_RF (0x1) |
Constant MODE_RF for sub-register SR_CHPM in register RF_IQIFC1.
| #define RF_PARAMP16U (0x2) |
Constant PARAMP16U for sub-register SR_PARAMP in register RF09_TXCUTC.
Referenced by oqpsk_rfcfg().
| #define RF_PARAMP32U (0x3) |
Constant PARAMP32U for sub-register SR_PARAMP in register RF09_TXCUTC.
Referenced by ofdm_rfcfg(), and oqpsk_rfcfg().
| #define RF_PARAMP4U (0x0) |
Constant PARAMP4U for sub-register SR_PARAMP in register RF09_TXCUTC.
Referenced by oqpsk_rfcfg().
| #define RF_PARAMP8U (0x1) |
Constant PARAMP8U for sub-register SR_PARAMP in register RF09_TXCUTC.
| #define RF_TRANSITION (0x6) |
Constant TRANSITION for sub-register SR_STATE in register RF09_STATE.
| #define RG_BBC0_AFC0 (0x320) |
Address for register BBC0_AFC0.
| #define RG_BBC0_AFC1 (0x321) |
Address for register BBC0_AFC1.
| #define RG_BBC0_AFFTM (0x322) |
Address for register BBC0_AFFTM.
Referenced by ack_timout_cb(), handle_incoming_frame(), start_ack_wait_timer(), tal_pib_set(), transmit_frame(), and write_all_tal_pib_to_trx().
| #define RG_BBC0_AFFVM (0x323) |
Address for register BBC0_AFFVM.
| #define RG_BBC0_AFS (0x324) |
Address for register BBC0_AFS.
| #define RG_BBC0_AMAACKPD (0x342) |
Address for register BBC0_AMAACKPD.
Referenced by trx_config().
| #define RG_BBC0_AMAACKTH (0x344) |
Address for register BBC0_AMAACKTH.
| #define RG_BBC0_AMAACKTL (0x343) |
Address for register BBC0_AMAACKTL.
Referenced by config_phy().
| #define RG_BBC0_AMCS (0x340) |
Address for register BBC0_AMCS.
Referenced by transmit_frame(), trx_config(), and tx_done_handling().
| #define RG_BBC0_AMEDT (0x341) |
Address for register BBC0_AMEDT.
Referenced by config_phy(), and tal_pib_set().
| #define RG_BBC0_CNT0 (0x391) |
Address for register BBC0_CNT0.
| #define RG_BBC0_CNT1 (0x392) |
Address for register BBC0_CNT1.
| #define RG_BBC0_CNT2 (0x393) |
Address for register BBC0_CNT2.
| #define RG_BBC0_CNT3 (0x394) |
Address for register BBC0_CNT3.
| #define RG_BBC0_CNTC (0x390) |
Address for register BBC0_CNTC.
Referenced by trx_config().
| #define RG_BBC0_FBLH (0x309) |
Address for register BBC0_FBLH.
| #define RG_BBC0_FBLIH (0x30B) |
Address for register BBC0_FBLIH.
| #define RG_BBC0_FBLIL (0x30A) |
Address for register BBC0_FBLIL.
| #define RG_BBC0_FBLL (0x308) |
Address for register BBC0_FBLL.
| #define RG_BBC0_FBRXE (0x27FE) |
Address for register BBC0_FBRXE.
| #define RG_BBC0_FBRXS (0x2000) |
Address for register BBC0_FBRXS.
Referenced by trx_irq_handler_cb(), and upload_frame().
| #define RG_BBC0_FBTXE (0x2FFE) |
Address for register BBC0_FBTXE.
| #define RG_BBC0_FBTXS (0x2800) |
Address for register BBC0_FBTXS.
Referenced by transmit_frame().
| #define RG_BBC0_FSKC0 (0x360) |
Address for register BBC0_FSKC0.
| #define RG_BBC0_FSKC1 (0x361) |
Address for register BBC0_FSKC1.
| #define RG_BBC0_FSKC2 (0x362) |
Address for register BBC0_FSKC2.
| #define RG_BBC0_FSKC3 (0x363) |
Address for register BBC0_FSKC3.
| #define RG_BBC0_FSKC4 (0x364) |
Address for register BBC0_FSKC4.
| #define RG_BBC0_FSKDM (0x372) |
Address for register BBC0_FSKDM.
Referenced by fsk_rfcfg().
| #define RG_BBC0_FSKPE0 (0x373) |
Address for register BBC0_FSKPE0.
| #define RG_BBC0_FSKPE1 (0x374) |
Address for register BBC0_FSKPE1.
| #define RG_BBC0_FSKPE2 (0x375) |
Address for register BBC0_FSKPE2.
| #define RG_BBC0_FSKPHRRX (0x36B) |
Address for register BBC0_FSKPHRRX.
| #define RG_BBC0_FSKPHRTX (0x36A) |
Address for register BBC0_FSKPHRTX.
| #define RG_BBC0_FSKPLL (0x365) |
Address for register BBC0_FSKPLL.
Referenced by ack_transmission_done(), config_fsk_rpc(), handle_incoming_frame(), set_fsk_pibs(), start_rpc(), and stop_rpc().
| #define RG_BBC0_FSKRPC (0x36C) |
Address for register BBC0_FSKRPC.
Referenced by config_fsk_rpc().
| #define RG_BBC0_FSKRPCOFFT (0x36E) |
Address for register BBC0_FSKRPCOFFT.
| #define RG_BBC0_FSKRPCONT (0x36D) |
Address for register BBC0_FSKRPCONT.
| #define RG_BBC0_FSKRRXFLH (0x371) |
Address for register BBC0_FSKRRXFLH.
| #define RG_BBC0_FSKRRXFLL (0x370) |
Address for register BBC0_FSKRRXFLL.
Referenced by set_fsk_pibs(), and tal_pib_set().
| #define RG_BBC0_FSKSFD0H (0x367) |
Address for register BBC0_FSKSFD0H.
| #define RG_BBC0_FSKSFD0L (0x366) |
Address for register BBC0_FSKSFD0L.
Referenced by set_sfd().
| #define RG_BBC0_FSKSFD1H (0x369) |
Address for register BBC0_FSKSFD1H.
| #define RG_BBC0_FSKSFD1L (0x368) |
Address for register BBC0_FSKSFD1L.
| #define RG_BBC0_IRQM (0x300) |
Address for register BBC0_IRQM.
Referenced by conf_trx_modulation(), and trx_config().
| #define RG_BBC0_IRQS (0x02) |
Address for register BBC0_IRQS.
Referenced by cancel_any_reception().
| #define RG_BBC0_MACEA0 (0x325) |
Address for register BBC0_MACEA0.
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define RG_BBC0_MACEA1 (0x326) |
Address for register BBC0_MACEA1.
| #define RG_BBC0_MACEA2 (0x327) |
Address for register BBC0_MACEA2.
| #define RG_BBC0_MACEA3 (0x328) |
Address for register BBC0_MACEA3.
| #define RG_BBC0_MACEA4 (0x329) |
Address for register BBC0_MACEA4.
| #define RG_BBC0_MACEA5 (0x32A) |
Address for register BBC0_MACEA5.
| #define RG_BBC0_MACEA6 (0x32B) |
Address for register BBC0_MACEA6.
| #define RG_BBC0_MACEA7 (0x32C) |
Address for register BBC0_MACEA7.
| #define RG_BBC0_MACPID0F0 (0x32D) |
Address for register BBC0_MACPID0F0.
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define RG_BBC0_MACPID0F1 (0x331) |
Address for register BBC0_MACPID0F1.
| #define RG_BBC0_MACPID0F2 (0x335) |
Address for register BBC0_MACPID0F2.
| #define RG_BBC0_MACPID0F3 (0x339) |
Address for register BBC0_MACPID0F3.
| #define RG_BBC0_MACPID1F0 (0x32E) |
Address for register BBC0_MACPID1F0.
| #define RG_BBC0_MACPID1F1 (0x332) |
Address for register BBC0_MACPID1F1.
| #define RG_BBC0_MACPID1F2 (0x336) |
Address for register BBC0_MACPID1F2.
| #define RG_BBC0_MACPID1F3 (0x33A) |
Address for register BBC0_MACPID1F3.
| #define RG_BBC0_MACSHA0F0 (0x32F) |
Address for register BBC0_MACSHA0F0.
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define RG_BBC0_MACSHA0F1 (0x333) |
Address for register BBC0_MACSHA0F1.
| #define RG_BBC0_MACSHA0F2 (0x337) |
Address for register BBC0_MACSHA0F2.
| #define RG_BBC0_MACSHA0F3 (0x33B) |
Address for register BBC0_MACSHA0F3.
| #define RG_BBC0_MACSHA1F0 (0x330) |
Address for register BBC0_MACSHA1F0.
| #define RG_BBC0_MACSHA1F1 (0x334) |
Address for register BBC0_MACSHA1F1.
| #define RG_BBC0_MACSHA1F2 (0x338) |
Address for register BBC0_MACSHA1F2.
| #define RG_BBC0_MACSHA1F3 (0x33C) |
Address for register BBC0_MACSHA1F3.
| #define RG_BBC0_OFDMC (0x30E) |
Address for register BBC0_OFDMC.
| #define RG_BBC0_OFDMPHRRX (0x30D) |
Address for register BBC0_OFDMPHRRX.
| #define RG_BBC0_OFDMPHRTX (0x30C) |
Address for register BBC0_OFDMPHRTX.
| #define RG_BBC0_OFDMSW (0x30F) |
Address for register BBC0_OFDMSW.
| #define RG_BBC0_OQPSKC0 (0x310) |
Address for register BBC0_OQPSKC0.
| #define RG_BBC0_OQPSKC1 (0x311) |
Address for register BBC0_OQPSKC1.
| #define RG_BBC0_OQPSKC2 (0x312) |
Address for register BBC0_OQPSKC2.
| #define RG_BBC0_OQPSKC3 (0x313) |
Address for register BBC0_OQPSKC3.
| #define RG_BBC0_OQPSKPHRRX (0x315) |
Address for register BBC0_OQPSKPHRRX.
| #define RG_BBC0_OQPSKPHRTX (0x314) |
Address for register BBC0_OQPSKPHRTX.
| #define RG_BBC0_PC (0x301) |
Address for register BBC0_PC.
Referenced by transmit_frame().
| #define RG_BBC0_PMUC (0x380) |
Address for register BBC0_PMUC.
| #define RG_BBC0_PMUI (0x383) |
Address for register BBC0_PMUI.
| #define RG_BBC0_PMUQ (0x384) |
Address for register BBC0_PMUQ.
| #define RG_BBC0_PMUQF (0x382) |
Address for register BBC0_PMUQF.
| #define RG_BBC0_PMUVAL (0x381) |
Address for register BBC0_PMUVAL.
| #define RG_BBC0_PS (0x302) |
Address for register BBC0_PS.
| #define RG_BBC0_RXFLH (0x305) |
Address for register BBC0_RXFLH.
| #define RG_BBC0_RXFLL (0x304) |
Address for register BBC0_RXFLL.
Referenced by upload_frame().
| #define RG_BBC0_TXFLH (0x307) |
Address for register BBC0_TXFLH.
| #define RG_BBC0_TXFLL (0x306) |
Address for register BBC0_TXFLL.
Referenced by transmit_frame().
| #define RG_BBC1_AFC0 (0x420) |
Address for register BBC1_AFC0.
| #define RG_BBC1_AFC1 (0x421) |
Address for register BBC1_AFC1.
| #define RG_BBC1_AFFTM (0x422) |
Address for register BBC1_AFFTM.
| #define RG_BBC1_AFFVM (0x423) |
Address for register BBC1_AFFVM.
| #define RG_BBC1_AFS (0x424) |
Address for register BBC1_AFS.
| #define RG_BBC1_AMAACKPD (0x442) |
Address for register BBC1_AMAACKPD.
| #define RG_BBC1_AMAACKTH (0x444) |
Address for register BBC1_AMAACKTH.
| #define RG_BBC1_AMAACKTL (0x443) |
Address for register BBC1_AMAACKTL.
| #define RG_BBC1_AMCS (0x440) |
Address for register BBC1_AMCS.
| #define RG_BBC1_AMEDT (0x441) |
Address for register BBC1_AMEDT.
| #define RG_BBC1_CNT0 (0x491) |
Address for register BBC1_CNT0.
| #define RG_BBC1_CNT1 (0x492) |
Address for register BBC1_CNT1.
| #define RG_BBC1_CNT2 (0x493) |
Address for register BBC1_CNT2.
| #define RG_BBC1_CNT3 (0x494) |
Address for register BBC1_CNT3.
| #define RG_BBC1_CNTC (0x490) |
Address for register BBC1_CNTC.
| #define RG_BBC1_FBLH (0x409) |
Address for register BBC1_FBLH.
| #define RG_BBC1_FBLIH (0x40B) |
Address for register BBC1_FBLIH.
| #define RG_BBC1_FBLIL (0x40A) |
Address for register BBC1_FBLIL.
| #define RG_BBC1_FBLL (0x408) |
Address for register BBC1_FBLL.
| #define RG_BBC1_FBRXE (0x37FE) |
Address for register BBC1_FBRXE.
| #define RG_BBC1_FBRXS (0x3000) |
Address for register BBC1_FBRXS.
| #define RG_BBC1_FBTXE (0x3FFE) |
Address for register BBC1_FBTXE.
| #define RG_BBC1_FBTXS (0x3800) |
Address for register BBC1_FBTXS.
| #define RG_BBC1_FSKC0 (0x460) |
Address for register BBC1_FSKC0.
| #define RG_BBC1_FSKC1 (0x461) |
Address for register BBC1_FSKC1.
| #define RG_BBC1_FSKC2 (0x462) |
Address for register BBC1_FSKC2.
| #define RG_BBC1_FSKC3 (0x463) |
Address for register BBC1_FSKC3.
| #define RG_BBC1_FSKC4 (0x464) |
Address for register BBC1_FSKC4.
| #define RG_BBC1_FSKDM (0x472) |
Address for register BBC1_FSKDM.
| #define RG_BBC1_FSKPE0 (0x473) |
Address for register BBC1_FSKPE0.
| #define RG_BBC1_FSKPE1 (0x474) |
Address for register BBC1_FSKPE1.
| #define RG_BBC1_FSKPE2 (0x475) |
Address for register BBC1_FSKPE2.
| #define RG_BBC1_FSKPHRRX (0x46B) |
Address for register BBC1_FSKPHRRX.
| #define RG_BBC1_FSKPHRTX (0x46A) |
Address for register BBC1_FSKPHRTX.
| #define RG_BBC1_FSKPLL (0x465) |
Address for register BBC1_FSKPLL.
| #define RG_BBC1_FSKRPC (0x46C) |
Address for register BBC1_FSKRPC.
| #define RG_BBC1_FSKRPCOFFT (0x46E) |
Address for register BBC1_FSKRPCOFFT.
| #define RG_BBC1_FSKRPCONT (0x46D) |
Address for register BBC1_FSKRPCONT.
| #define RG_BBC1_FSKRRXFLH (0x471) |
Address for register BBC1_FSKRRXFLH.
| #define RG_BBC1_FSKRRXFLL (0x470) |
Address for register BBC1_FSKRRXFLL.
| #define RG_BBC1_FSKSFD0H (0x467) |
Address for register BBC1_FSKSFD0H.
| #define RG_BBC1_FSKSFD0L (0x466) |
Address for register BBC1_FSKSFD0L.
| #define RG_BBC1_FSKSFD1H (0x469) |
Address for register BBC1_FSKSFD1H.
| #define RG_BBC1_FSKSFD1L (0x468) |
Address for register BBC1_FSKSFD1L.
| #define RG_BBC1_IRQM (0x400) |
Address for register BBC1_IRQM.
| #define RG_BBC1_IRQS (0x03) |
Address for register BBC1_IRQS.
Referenced by cancel_any_reception().
| #define RG_BBC1_MACEA0 (0x425) |
Address for register BBC1_MACEA0.
| #define RG_BBC1_MACEA1 (0x426) |
Address for register BBC1_MACEA1.
| #define RG_BBC1_MACEA2 (0x427) |
Address for register BBC1_MACEA2.
| #define RG_BBC1_MACEA3 (0x428) |
Address for register BBC1_MACEA3.
| #define RG_BBC1_MACEA4 (0x429) |
Address for register BBC1_MACEA4.
| #define RG_BBC1_MACEA5 (0x42A) |
Address for register BBC1_MACEA5.
| #define RG_BBC1_MACEA6 (0x42B) |
Address for register BBC1_MACEA6.
| #define RG_BBC1_MACEA7 (0x42C) |
Address for register BBC1_MACEA7.
| #define RG_BBC1_MACPID0F0 (0x42D) |
Address for register BBC1_MACPID0F0.
| #define RG_BBC1_MACPID0F1 (0x431) |
Address for register BBC1_MACPID0F1.
| #define RG_BBC1_MACPID0F2 (0x435) |
Address for register BBC1_MACPID0F2.
| #define RG_BBC1_MACPID0F3 (0x439) |
Address for register BBC1_MACPID0F3.
| #define RG_BBC1_MACPID1F0 (0x42E) |
Address for register BBC1_MACPID1F0.
| #define RG_BBC1_MACPID1F1 (0x432) |
Address for register BBC1_MACPID1F1.
| #define RG_BBC1_MACPID1F2 (0x436) |
Address for register BBC1_MACPID1F2.
| #define RG_BBC1_MACPID1F3 (0x43A) |
Address for register BBC1_MACPID1F3.
| #define RG_BBC1_MACSHA0F0 (0x42F) |
Address for register BBC1_MACSHA0F0.
| #define RG_BBC1_MACSHA0F1 (0x433) |
Address for register BBC1_MACSHA0F1.
| #define RG_BBC1_MACSHA0F2 (0x437) |
Address for register BBC1_MACSHA0F2.
| #define RG_BBC1_MACSHA0F3 (0x43B) |
Address for register BBC1_MACSHA0F3.
| #define RG_BBC1_MACSHA1F0 (0x430) |
Address for register BBC1_MACSHA1F0.
| #define RG_BBC1_MACSHA1F1 (0x434) |
Address for register BBC1_MACSHA1F1.
| #define RG_BBC1_MACSHA1F2 (0x438) |
Address for register BBC1_MACSHA1F2.
| #define RG_BBC1_MACSHA1F3 (0x43C) |
Address for register BBC1_MACSHA1F3.
| #define RG_BBC1_OFDMC (0x40E) |
Address for register BBC1_OFDMC.
| #define RG_BBC1_OFDMPHRRX (0x40D) |
Address for register BBC1_OFDMPHRRX.
| #define RG_BBC1_OFDMPHRTX (0x40C) |
Address for register BBC1_OFDMPHRTX.
| #define RG_BBC1_OFDMSW (0x40F) |
Address for register BBC1_OFDMSW.
| #define RG_BBC1_OQPSKC0 (0x410) |
Address for register BBC1_OQPSKC0.
| #define RG_BBC1_OQPSKC1 (0x411) |
Address for register BBC1_OQPSKC1.
| #define RG_BBC1_OQPSKC2 (0x412) |
Address for register BBC1_OQPSKC2.
| #define RG_BBC1_OQPSKC3 (0x413) |
Address for register BBC1_OQPSKC3.
| #define RG_BBC1_OQPSKPHRRX (0x415) |
Address for register BBC1_OQPSKPHRRX.
| #define RG_BBC1_OQPSKPHRTX (0x414) |
Address for register BBC1_OQPSKPHRTX.
| #define RG_BBC1_PC (0x401) |
Address for register BBC1_PC.
| #define RG_BBC1_PMUC (0x480) |
Address for register BBC1_PMUC.
| #define RG_BBC1_PMUI (0x483) |
Address for register BBC1_PMUI.
| #define RG_BBC1_PMUQ (0x484) |
Address for register BBC1_PMUQ.
| #define RG_BBC1_PMUQF (0x482) |
Address for register BBC1_PMUQF.
| #define RG_BBC1_PMUVAL (0x481) |
Address for register BBC1_PMUVAL.
| #define RG_BBC1_PS (0x402) |
Address for register BBC1_PS.
| #define RG_BBC1_RXFLH (0x405) |
Address for register BBC1_RXFLH.
| #define RG_BBC1_RXFLL (0x404) |
Address for register BBC1_RXFLL.
| #define RG_BBC1_TXFLH (0x407) |
Address for register BBC1_TXFLH.
| #define RG_BBC1_TXFLL (0x406) |
Address for register BBC1_TXFLL.
| #define RG_RF09_AGCC (0x10B) |
Address for register RF09_AGCC.
Referenced by fsk_rfcfg(), and trx_config().
| #define RG_RF09_AGCS (0x10C) |
Address for register RF09_AGCS.
| #define RG_RF09_AUXS (0x101) |
Address for register RF09_AUXS.
| #define RG_RF09_CCF0H (0x106) |
Address for register RF09_CCF0H.
| #define RG_RF09_CCF0L (0x105) |
Address for register RF09_CCF0L.
Referenced by apply_channel_settings().
| #define RG_RF09_CMD (0x103) |
Address for register RF09_CMD.
Referenced by conf_trx_modulation(), handle_ed_end_irq(), handle_rx_end_irq(), handle_trxerr(), start_ack_wait_timer(), switch_to_rx(), switch_to_txprep(), tal_rx_enable(), tal_trx_sleep(), tal_trx_wakeup(), transmit_frame(), trx_reset(), and tx_done_handling().
| #define RG_RF09_CNL (0x107) |
Address for register RF09_CNL.
Referenced by apply_channel_settings(), and set_channel().
| #define RG_RF09_CNM (0x108) |
Address for register RF09_CNM.
| #define RG_RF09_CS (0x104) |
Address for register RF09_CS.
Referenced by apply_channel_settings().
| #define RG_RF09_EDC (0x10E) |
Address for register RF09_EDC.
Referenced by transmit_frame().
| #define RG_RF09_EDD (0x10F) |
Address for register RF09_EDD.
Referenced by set_ed_sample_duration().
| #define RG_RF09_EDV (0x110) |
Address for register RF09_EDV.
Referenced by complete_rx_transaction(), and handle_ed_end_irq().
| #define RG_RF09_IRQM (0x100) |
Address for register RF09_IRQM.
Referenced by trx_config().
| #define RG_RF09_IRQS (0x00) |
Register addresses.
Address for register RF09_IRQS
Referenced by cancel_any_reception(), and trx_irq_handler_cb().
| #define RG_RF09_PAC (0x114) |
Address for register RF09_PAC.
Referenced by fsk_rfcfg().
| #define RG_RF09_PADFE (0x116) |
Address for register RF09_PADFE.
| #define RG_RF09_PLL (0x121) |
Address for register RF09_PLL.
Referenced by start_rpc(), stop_rpc(), wait_for_freq_settling(), and wait_for_txprep().
| #define RG_RF09_PLLCF (0x122) |
Address for register RF09_PLLCF.
| #define RG_RF09_RNDV (0x111) |
Address for register RF09_RNDV.
Referenced by tal_generate_rand_seed().
| #define RG_RF09_RSSI (0x10D) |
Address for register RF09_RSSI.
| #define RG_RF09_RXBWC (0x109) |
Address for register RF09_RXBWC.
Referenced by fsk_rfcfg(), ofdm_rfcfg(), oqpsk_rfcfg(), and tal_generate_rand_seed().
| #define RG_RF09_RXDFE (0x10A) |
Address for register RF09_RXDFE.
| #define RG_RF09_STATE (0x102) |
Address for register RF09_STATE.
Referenced by conf_trx_modulation(), transmit_frame(), trx_reset(), and wait_for_txprep().
| #define RG_RF09_TXCI (0x125) |
Address for register RF09_TXCI.
| #define RG_RF09_TXCQ (0x126) |
Address for register RF09_TXCQ.
| #define RG_RF09_TXCUTC (0x112) |
Address for register RF09_TXCUTC.
Referenced by fsk_rfcfg(), ofdm_rfcfg(), and oqpsk_rfcfg().
| #define RG_RF09_TXDACI (0x127) |
Address for register RF09_TXDACI.
| #define RG_RF09_TXDACQ (0x128) |
Address for register RF09_TXDACQ.
| #define RG_RF09_TXDFE (0x113) |
Address for register RF09_TXDFE.
| #define RG_RF24_AGCC (0x20B) |
Address for register RF24_AGCC.
| #define RG_RF24_AGCS (0x20C) |
Address for register RF24_AGCS.
| #define RG_RF24_AUXS (0x201) |
Address for register RF24_AUXS.
| #define RG_RF24_CCF0H (0x206) |
Address for register RF24_CCF0H.
| #define RG_RF24_CCF0L (0x205) |
Address for register RF24_CCF0L.
| #define RG_RF24_CMD (0x203) |
Address for register RF24_CMD.
| #define RG_RF24_CNL (0x207) |
Address for register RF24_CNL.
| #define RG_RF24_CNM (0x208) |
Address for register RF24_CNM.
| #define RG_RF24_CS (0x204) |
Address for register RF24_CS.
| #define RG_RF24_EDC (0x20E) |
Address for register RF24_EDC.
| #define RG_RF24_EDD (0x20F) |
Address for register RF24_EDD.
| #define RG_RF24_EDV (0x210) |
Address for register RF24_EDV.
| #define RG_RF24_IRQM (0x200) |
Address for register RF24_IRQM.
| #define RG_RF24_IRQS (0x01) |
Address for register RF24_IRQS.
Referenced by cancel_any_reception().
| #define RG_RF24_PAC (0x214) |
Address for register RF24_PAC.
| #define RG_RF24_PADFE (0x216) |
Address for register RF24_PADFE.
| #define RG_RF24_PLL (0x221) |
Address for register RF24_PLL.
| #define RG_RF24_PLLCF (0x222) |
Address for register RF24_PLLCF.
| #define RG_RF24_RNDV (0x211) |
Address for register RF24_RNDV.
| #define RG_RF24_RSSI (0x20D) |
Address for register RF24_RSSI.
| #define RG_RF24_RXBWC (0x209) |
Address for register RF24_RXBWC.
| #define RG_RF24_RXDFE (0x20A) |
Address for register RF24_RXDFE.
| #define RG_RF24_STATE (0x202) |
Address for register RF24_STATE.
| #define RG_RF24_TXCI (0x225) |
Address for register RF24_TXCI.
| #define RG_RF24_TXCQ (0x226) |
Address for register RF24_TXCQ.
| #define RG_RF24_TXCUTC (0x212) |
Address for register RF24_TXCUTC.
| #define RG_RF24_TXDACI (0x227) |
Address for register RF24_TXDACI.
| #define RG_RF24_TXDACQ (0x228) |
Address for register RF24_TXDACQ.
| #define RG_RF24_TXDFE (0x213) |
Address for register RF24_TXDFE.
| #define RG_RF_BMDVC (0x08) |
Address for register RF_BMDVC.
| #define RG_RF_CFG (0x06) |
Address for register RF_CFG.
| #define RG_RF_CLKO (0x07) |
Address for register RF_CLKO.
| #define RG_RF_IQIFC0 (0x0A) |
Address for register RF_IQIFC0.
| #define RG_RF_IQIFC1 (0x0B) |
Address for register RF_IQIFC1.
| #define RG_RF_IQIFC2 (0x0C) |
Address for register RF_IQIFC2.
| #define RG_RF_PN (0x0D) |
Address for register RF_PN.
Referenced by tal_init().
| #define RG_RF_RST (0x05) |
Address for register RF_RST.
| #define RG_RF_VN (0x0E) |
Address for register RF_VN.
Referenced by tal_init().
| #define RG_RF_XOC (0x09) |
Address for register RF_XOC.
| #define RNDV_RNDV_MASK 0xFF |
Sub-registers of Register RNDV.
Bit Mask for Sub-Register RNDV.RNDV
| #define RNDV_RNDV_SHIFT 0 |
Bit Offset for Sub-Register RNDV.RNDV.
| #define RSSI_RSSI_MASK 0xFF |
Sub-registers of Register RSSI.
Bit Mask for Sub-Register RSSI.RSSI
| #define RSSI_RSSI_SHIFT 0 |
Bit Offset for Sub-Register RSSI.RSSI.
| #define RST_CMD_MASK 0x07 |
Sub-registers of Register RST.
Bit Mask for Sub-Register RST.CMD
| #define RST_CMD_SHIFT 0 |
Bit Offset for Sub-Register RST.CMD.
| #define RST_PULSE_WIDTH_NS (5) |
Parameter definitions.
Typical timing values.
| #define RXBWC_BW_MASK 0x0F |
Sub-registers of Register RXBWC.
Bit Mask for Sub-Register RXBWC.BW
| #define RXBWC_BW_SHIFT 0 |
Bit Offset for Sub-Register RXBWC.BW.
Referenced by ofdm_rfcfg(), and oqpsk_rfcfg().
| #define RXBWC_IFI_MASK 0x20 |
Bit Mask for Sub-Register RXBWC.IFI.
| #define RXBWC_IFI_SHIFT 5 |
Bit Offset for Sub-Register RXBWC.IFI.
| #define RXBWC_IFS_MASK 0x10 |
Bit Mask for Sub-Register RXBWC.IFS.
| #define RXBWC_IFS_SHIFT 4 |
Bit Offset for Sub-Register RXBWC.IFS.
Referenced by ofdm_rfcfg(), and oqpsk_rfcfg().
| #define RXDFE_RCUT_MASK 0xE0 |
Bit Mask for Sub-Register RXDFE.RCUT.
| #define RXDFE_RCUT_SHIFT 5 |
Bit Offset for Sub-Register RXDFE.RCUT.
Referenced by ofdm_rfcfg(), and oqpsk_rfcfg().
| #define RXDFE_SR_MASK 0x0F |
| #define RXDFE_SR_SHIFT 0 |
Bit Offset for Sub-Register RXDFE.SR.
Referenced by ofdm_rfcfg(), and oqpsk_rfcfg().
| #define RXFLH_RXFLH_MASK 0x07 |
Sub-registers of Register RXFLH.
Bit Mask for Sub-Register RXFLH.RXFLH
| #define RXFLH_RXFLH_SHIFT 0 |
Bit Offset for Sub-Register RXFLH.RXFLH.
| #define RXFLL_RXFLL_MASK 0xFF |
Sub-registers of Register RXFLL.
Bit Mask for Sub-Register RXFLL.RXFLL
| #define RXFLL_RXFLL_SHIFT 0 |
Bit Offset for Sub-Register RXFLL.RXFLL.
| #define SR_BBC0_AFC0_AFEN0 |
Sub-registers of Register RG_BBC0_AFC0.
Access parameters for sub-register AFEN0 in register RG_BBC0_AFC0
Referenced by trx_config().
| #define SR_BBC0_AFC0_AFEN1 |
Access parameters for sub-register AFEN1 in register RG_BBC0_AFC0.
| #define SR_BBC0_AFC0_AFEN2 |
Access parameters for sub-register AFEN2 in register RG_BBC0_AFC0.
| #define SR_BBC0_AFC0_AFEN3 |
Access parameters for sub-register AFEN3 in register RG_BBC0_AFC0.
| #define SR_BBC0_AFC0_PM |
Access parameters for sub-register PM in register RG_BBC0_AFC0.
Referenced by tal_get_curr_trx_config(), tal_pib_set(), tal_rxaack_prom_mode_ctrl(), and write_all_tal_pib_to_trx().
| #define SR_BBC0_AFC1_MRFT0 |
Access parameters for sub-register MRFT0 in register RG_BBC0_AFC1.
| #define SR_BBC0_AFC1_MRFT1 |
Access parameters for sub-register MRFT1 in register RG_BBC0_AFC1.
| #define SR_BBC0_AFC1_MRFT2 |
Access parameters for sub-register MRFT2 in register RG_BBC0_AFC1.
| #define SR_BBC0_AFC1_MRFT3 |
Access parameters for sub-register MRFT3 in register RG_BBC0_AFC1.
| #define SR_BBC0_AFC1_PANC0 |
Sub-registers of Register RG_BBC0_AFC1.
Access parameters for sub-register PANC0 in register RG_BBC0_AFC1
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define SR_BBC0_AFC1_PANC1 |
Access parameters for sub-register PANC1 in register RG_BBC0_AFC1.
| #define SR_BBC0_AFC1_PANC2 |
Access parameters for sub-register PANC2 in register RG_BBC0_AFC1.
| #define SR_BBC0_AFC1_PANC3 |
Access parameters for sub-register PANC3 in register RG_BBC0_AFC1.
| #define SR_BBC0_AFFTM_AFFTM |
Sub-registers of Register RG_BBC0_AFFTM.
Access parameters for sub-register AFFTM in register RG_BBC0_AFFTM
| #define SR_BBC0_AFFVM_AFFVM |
Sub-registers of Register RG_BBC0_AFFVM.
Access parameters for sub-register AFFVM in register RG_BBC0_AFFVM
Referenced by tal_pib_set().
| #define SR_BBC0_AFS_AM0 RG_BBC0_AFS, AFS_AM0_MASK, AFS_AM0_SHIFT |
Sub-registers of Register RG_BBC0_AFS.
Access parameters for sub-register AM0 in register RG_BBC0_AFS
| #define SR_BBC0_AFS_AM1 RG_BBC0_AFS, AFS_AM1_MASK, AFS_AM1_SHIFT |
Access parameters for sub-register AM1 in register RG_BBC0_AFS.
| #define SR_BBC0_AFS_AM2 RG_BBC0_AFS, AFS_AM2_MASK, AFS_AM2_SHIFT |
Access parameters for sub-register AM2 in register RG_BBC0_AFS.
| #define SR_BBC0_AFS_AM3 RG_BBC0_AFS, AFS_AM3_MASK, AFS_AM3_SHIFT |
Access parameters for sub-register AM3 in register RG_BBC0_AFS.
| #define SR_BBC0_AFS_EM RG_BBC0_AFS, AFS_EM_MASK, AFS_EM_SHIFT |
Access parameters for sub-register EM in register RG_BBC0_AFS.
| #define SR_BBC0_AMAACKPD_PD0 |
Sub-registers of Register RG_BBC0_AMAACKPD.
Access parameters for sub-register PD0 in register RG_BBC0_AMAACKPD
| #define SR_BBC0_AMAACKPD_PD1 |
Access parameters for sub-register PD1 in register RG_BBC0_AMAACKPD.
| #define SR_BBC0_AMAACKPD_PD2 |
Access parameters for sub-register PD2 in register RG_BBC0_AMAACKPD.
| #define SR_BBC0_AMAACKPD_PD3 |
Access parameters for sub-register PD3 in register RG_BBC0_AMAACKPD.
| #define SR_BBC0_AMAACKTH_AMAACKTH |
Sub-registers of Register RG_BBC0_AMAACKTH.
Access parameters for sub-register AMAACKTH in register RG_BBC0_AMAACKTH
| #define SR_BBC0_AMAACKTL_AMAACKTL |
Sub-registers of Register RG_BBC0_AMAACKTL.
Access parameters for sub-register AMAACKTL in register RG_BBC0_AMAACKTL
| #define SR_BBC0_AMCS_AACK |
Access parameters for sub-register AACK in register RG_BBC0_AMCS.
Referenced by handle_rx_end_irq(), tal_pib_set(), and trx_irq_handler_cb().
| #define SR_BBC0_AMCS_AACKDR |
Access parameters for sub-register AACKDR in register RG_BBC0_AMCS.
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define SR_BBC0_AMCS_AACKFA |
Access parameters for sub-register AACKFA in register RG_BBC0_AMCS.
| #define SR_BBC0_AMCS_AACKFT |
Access parameters for sub-register AACKFT in register RG_BBC0_AMCS.
Referenced by handle_incoming_frame(), and handle_rx_end_irq().
| #define SR_BBC0_AMCS_AACKS |
Access parameters for sub-register AACKS in register RG_BBC0_AMCS.
| #define SR_BBC0_AMCS_CCAED |
Access parameters for sub-register CCAED in register RG_BBC0_AMCS.
Referenced by handle_tx_end_irq().
| #define SR_BBC0_AMCS_CCATX |
Access parameters for sub-register CCATX in register RG_BBC0_AMCS.
| #define SR_BBC0_AMCS_TX2RX |
Sub-registers of Register RG_BBC0_AMCS.
Access parameters for sub-register TX2RX in register RG_BBC0_AMCS
| #define SR_BBC0_AMEDT_AMEDT |
Sub-registers of Register RG_BBC0_AMEDT.
Access parameters for sub-register AMEDT in register RG_BBC0_AMEDT
| #define SR_BBC0_CNT0_CNT0 |
Sub-registers of Register RG_BBC0_CNT0.
Access parameters for sub-register CNT0 in register RG_BBC0_CNT0
| #define SR_BBC0_CNT1_CNT1 |
Sub-registers of Register RG_BBC0_CNT1.
Access parameters for sub-register CNT1 in register RG_BBC0_CNT1
| #define SR_BBC0_CNT2_CNT2 |
Sub-registers of Register RG_BBC0_CNT2.
Access parameters for sub-register CNT2 in register RG_BBC0_CNT2
| #define SR_BBC0_CNT3_CNT3 |
Sub-registers of Register RG_BBC0_CNT3.
Access parameters for sub-register CNT3 in register RG_BBC0_CNT3
| #define SR_BBC0_CNTC_CAPRXS |
Access parameters for sub-register CAPRXS in register RG_BBC0_CNTC.
| #define SR_BBC0_CNTC_CAPTXS |
Access parameters for sub-register CAPTXS in register RG_BBC0_CNTC.
| #define SR_BBC0_CNTC_EN |
Sub-registers of Register RG_BBC0_CNTC.
Access parameters for sub-register EN in register RG_BBC0_CNTC
| #define SR_BBC0_CNTC_RSTRXS |
Access parameters for sub-register RSTRXS in register RG_BBC0_CNTC.
| #define SR_BBC0_CNTC_RSTTXS |
Access parameters for sub-register RSTTXS in register RG_BBC0_CNTC.
| #define SR_BBC0_FBLH_FBLH |
Sub-registers of Register RG_BBC0_FBLH.
Access parameters for sub-register FBLH in register RG_BBC0_FBLH
| #define SR_BBC0_FBLIH_FBLIH |
Sub-registers of Register RG_BBC0_FBLIH.
Access parameters for sub-register FBLIH in register RG_BBC0_FBLIH
| #define SR_BBC0_FBLIL_FBLIL |
Sub-registers of Register RG_BBC0_FBLIL.
Access parameters for sub-register FBLIL in register RG_BBC0_FBLIL
| #define SR_BBC0_FBLL_FBLL |
Sub-registers of Register RG_BBC0_FBLL.
Access parameters for sub-register FBLL in register RG_BBC0_FBLL
| #define SR_BBC0_FBRXE_FBRXE |
Sub-registers of Register RG_BBC0_FBRXE.
Access parameters for sub-register FBRXE in register RG_BBC0_FBRXE
| #define SR_BBC0_FBRXS_FBRXS |
Sub-registers of Register RG_BBC0_FBRXS.
Access parameters for sub-register FBRXS in register RG_BBC0_FBRXS
| #define SR_BBC0_FBTXE_FBTXE |
Sub-registers of Register RG_BBC0_FBTXE.
Access parameters for sub-register FBTXE in register RG_BBC0_FBTXE
| #define SR_BBC0_FBTXS_FBTXS |
Sub-registers of Register RG_BBC0_FBTXS.
Access parameters for sub-register FBTXS in register RG_BBC0_FBTXS
| #define SR_BBC0_FSKC0_BT |
Access parameters for sub-register BT in register RG_BBC0_FSKC0.
Referenced by conf_fsk().
| #define SR_BBC0_FSKC0_MIDX |
Access parameters for sub-register MIDX in register RG_BBC0_FSKC0.
Referenced by conf_fsk().
| #define SR_BBC0_FSKC0_MIDXS |
Access parameters for sub-register MIDXS in register RG_BBC0_FSKC0.
| #define SR_BBC0_FSKC0_MORD |
Sub-registers of Register RG_BBC0_FSKC0.
Access parameters for sub-register MORD in register RG_BBC0_FSKC0
Referenced by conf_fsk().
| #define SR_BBC0_FSKC1_FI |
Access parameters for sub-register FI in register RG_BBC0_FSKC1.
| #define SR_BBC0_FSKC1_FSKPLH |
Access parameters for sub-register FSKPLH in register RG_BBC0_FSKC1.
Referenced by ack_transmission_done(), config_fsk_rpc(), handle_incoming_frame(), set_fsk_pibs(), start_rpc(), and stop_rpc().
| #define SR_BBC0_FSKC1_SRATE |
Sub-registers of Register RG_BBC0_FSKC1.
Access parameters for sub-register SRATE in register RG_BBC0_FSKC1
Referenced by conf_fsk().
| #define SR_BBC0_FSKC2_FECIE |
Sub-registers of Register RG_BBC0_FSKC2.
Access parameters for sub-register FECIE in register RG_BBC0_FSKC2
Referenced by set_fsk_pibs(), and tal_pib_set().
| #define SR_BBC0_FSKC2_FECS |
Access parameters for sub-register FECS in register RG_BBC0_FSKC2.
Referenced by set_fsk_pibs(), and tal_pib_set().
| #define SR_BBC0_FSKC2_MSE |
Access parameters for sub-register MSE in register RG_BBC0_FSKC2.
Referenced by set_fsk_pibs(), and tal_pib_set().
| #define SR_BBC0_FSKC2_PDTM |
Access parameters for sub-register PDTM in register RG_BBC0_FSKC2.
Referenced by config_fsk_rpc().
| #define SR_BBC0_FSKC2_PRI |
Access parameters for sub-register PRI in register RG_BBC0_FSKC2.
| #define SR_BBC0_FSKC2_RXO |
Access parameters for sub-register RXO in register RG_BBC0_FSKC2.
| #define SR_BBC0_FSKC2_RXPTO |
Access parameters for sub-register RXPTO in register RG_BBC0_FSKC2.
| #define SR_BBC0_FSKC3_PDT |
Sub-registers of Register RG_BBC0_FSKC3.
Access parameters for sub-register PDT in register RG_BBC0_FSKC3
| #define SR_BBC0_FSKC3_SFDT |
Access parameters for sub-register SFDT in register RG_BBC0_FSKC3.
| #define SR_BBC0_FSKC4_CSFD0 |
Sub-registers of Register RG_BBC0_FSKC4.
Access parameters for sub-register CSFD0 in register RG_BBC0_FSKC4
| #define SR_BBC0_FSKC4_CSFD1 |
Access parameters for sub-register CSFD1 in register RG_BBC0_FSKC4.
| #define SR_BBC0_FSKC4_RAWRBIT |
Access parameters for sub-register RAWRBIT in register RG_BBC0_FSKC4.
Referenced by trx_config().
| #define SR_BBC0_FSKC4_SFD32 |
Access parameters for sub-register SFD32 in register RG_BBC0_FSKC4.
| #define SR_BBC0_FSKC4_SFDQ |
Access parameters for sub-register SFDQ in register RG_BBC0_FSKC4.
| #define SR_BBC0_FSKDM_EN |
Sub-registers of Register RG_BBC0_FSKDM.
Access parameters for sub-register EN in register RG_BBC0_FSKDM
| #define SR_BBC0_FSKDM_PE |
Access parameters for sub-register PE in register RG_BBC0_FSKDM.
| #define SR_BBC0_FSKPE0_FSKPE0 |
Sub-registers of Register RG_BBC0_FSKPE0.
Access parameters for sub-register FSKPE0 in register RG_BBC0_FSKPE0
| #define SR_BBC0_FSKPE1_FSKPE1 |
Sub-registers of Register RG_BBC0_FSKPE1.
Access parameters for sub-register FSKPE1 in register RG_BBC0_FSKPE1
| #define SR_BBC0_FSKPE2_FSKPE2 |
Sub-registers of Register RG_BBC0_FSKPE2.
Access parameters for sub-register FSKPE2 in register RG_BBC0_FSKPE2
| #define SR_BBC0_FSKPHRRX_DW |
Access parameters for sub-register DW in register RG_BBC0_FSKPHRRX.
| #define SR_BBC0_FSKPHRRX_FCST |
Access parameters for sub-register FCST in register RG_BBC0_FSKPHRRX.
Referenced by handle_rx_end_irq().
| #define SR_BBC0_FSKPHRRX_MS |
Access parameters for sub-register MS in register RG_BBC0_FSKPHRRX.
Referenced by handle_rx_end_irq().
| #define SR_BBC0_FSKPHRRX_RB1 |
Sub-registers of Register RG_BBC0_FSKPHRRX.
Access parameters for sub-register RB1 in register RG_BBC0_FSKPHRRX
| #define SR_BBC0_FSKPHRRX_RB2 |
Access parameters for sub-register RB2 in register RG_BBC0_FSKPHRRX.
| #define SR_BBC0_FSKPHRRX_SFD |
Access parameters for sub-register SFD in register RG_BBC0_FSKPHRRX.
| #define SR_BBC0_FSKPHRTX_DW |
Access parameters for sub-register DW in register RG_BBC0_FSKPHRTX.
Referenced by set_fsk_pibs(), and tal_pib_set().
| #define SR_BBC0_FSKPHRTX_RB1 |
Sub-registers of Register RG_BBC0_FSKPHRTX.
Access parameters for sub-register RB1 in register RG_BBC0_FSKPHRTX
| #define SR_BBC0_FSKPHRTX_RB2 |
Access parameters for sub-register RB2 in register RG_BBC0_FSKPHRTX.
| #define SR_BBC0_FSKPHRTX_SFD |
Access parameters for sub-register SFD in register RG_BBC0_FSKPHRTX.
Referenced by set_fsk_pibs(), and tal_pib_set().
| #define SR_BBC0_FSKPLL_FSKPLL |
Sub-registers of Register RG_BBC0_FSKPLL.
Access parameters for sub-register FSKPLL in register RG_BBC0_FSKPLL
| #define SR_BBC0_FSKRPC_BASET |
Sub-registers of Register RG_BBC0_FSKRPC.
Access parameters for sub-register BASET in register RG_BBC0_FSKRPC
| #define SR_BBC0_FSKRPC_EN |
Access parameters for sub-register EN in register RG_BBC0_FSKRPC.
Referenced by config_fsk_rpc(), start_rpc(), and stop_rpc().
| #define SR_BBC0_FSKRPCOFFT_FSKRPCOFFT |
Sub-registers of Register RG_BBC0_FSKRPCOFFT.
Access parameters for sub-register FSKRPCOFFT in register RG_BBC0_FSKRPCOFFT
| #define SR_BBC0_FSKRPCONT_FSKRPCONT |
Sub-registers of Register RG_BBC0_FSKRPCONT.
Access parameters for sub-register FSKRPCONT in register RG_BBC0_FSKRPCONT
| #define SR_BBC0_FSKRRXFLH_FSKRRXFLH |
Sub-registers of Register RG_BBC0_FSKRRXFLH.
Access parameters for sub-register FSKRRXFLH in register RG_BBC0_FSKRRXFLH
| #define SR_BBC0_FSKRRXFLL_FSKRRXFLL |
Sub-registers of Register RG_BBC0_FSKRRXFLL.
Access parameters for sub-register FSKRRXFLL in register RG_BBC0_FSKRRXFLL
| #define SR_BBC0_FSKSFD0H_FSKSFD0H |
Sub-registers of Register RG_BBC0_FSKSFD0H.
Access parameters for sub-register FSKSFD0H in register RG_BBC0_FSKSFD0H
| #define SR_BBC0_FSKSFD0L_FSKSFD0L |
Sub-registers of Register RG_BBC0_FSKSFD0L.
Access parameters for sub-register FSKSFD0L in register RG_BBC0_FSKSFD0L
| #define SR_BBC0_FSKSFD1H_FSKSFD1H |
Sub-registers of Register RG_BBC0_FSKSFD1H.
Access parameters for sub-register FSKSFD1H in register RG_BBC0_FSKSFD1H
| #define SR_BBC0_FSKSFD1L_FSKSFD1L |
Sub-registers of Register RG_BBC0_FSKSFD1L.
Access parameters for sub-register FSKSFD1L in register RG_BBC0_FSKSFD1L
| #define SR_BBC0_IRQM_AGCH |
Access parameters for sub-register AGCH in register RG_BBC0_IRQM.
| #define SR_BBC0_IRQM_AGCR |
Access parameters for sub-register AGCR in register RG_BBC0_IRQM.
| #define SR_BBC0_IRQM_FBLI |
Access parameters for sub-register FBLI in register RG_BBC0_IRQM.
| #define SR_BBC0_IRQM_RXAM |
Access parameters for sub-register RXAM in register RG_BBC0_IRQM.
| #define SR_BBC0_IRQM_RXEM |
Access parameters for sub-register RXEM in register RG_BBC0_IRQM.
| #define SR_BBC0_IRQM_RXFE |
Access parameters for sub-register RXFE in register RG_BBC0_IRQM.
| #define SR_BBC0_IRQM_RXFS |
Sub-registers of Register RG_BBC0_IRQM.
Access parameters for sub-register RXFS in register RG_BBC0_IRQM
| #define SR_BBC0_IRQM_TXFE |
Access parameters for sub-register TXFE in register RG_BBC0_IRQM.
| #define SR_BBC0_IRQS_AGCH |
Access parameters for sub-register AGCH in register RG_BBC0_IRQS.
| #define SR_BBC0_IRQS_AGCR |
Access parameters for sub-register AGCR in register RG_BBC0_IRQS.
| #define SR_BBC0_IRQS_FBLI |
Access parameters for sub-register FBLI in register RG_BBC0_IRQS.
| #define SR_BBC0_IRQS_RXAM |
Access parameters for sub-register RXAM in register RG_BBC0_IRQS.
| #define SR_BBC0_IRQS_RXEM |
Access parameters for sub-register RXEM in register RG_BBC0_IRQS.
| #define SR_BBC0_IRQS_RXFE |
Access parameters for sub-register RXFE in register RG_BBC0_IRQS.
| #define SR_BBC0_IRQS_RXFS |
Sub-registers of Register RG_BBC0_IRQS.
Access parameters for sub-register RXFS in register RG_BBC0_IRQS
| #define SR_BBC0_IRQS_TXFE |
Access parameters for sub-register TXFE in register RG_BBC0_IRQS.
| #define SR_BBC0_MACEA0_MACEA0 |
Sub-registers of Register RG_BBC0_MACEA0.
Access parameters for sub-register MACEA0 in register RG_BBC0_MACEA0
| #define SR_BBC0_MACEA1_MACEA1 |
Sub-registers of Register RG_BBC0_MACEA1.
Access parameters for sub-register MACEA1 in register RG_BBC0_MACEA1
| #define SR_BBC0_MACEA2_MACEA2 |
Sub-registers of Register RG_BBC0_MACEA2.
Access parameters for sub-register MACEA2 in register RG_BBC0_MACEA2
| #define SR_BBC0_MACEA3_MACEA3 |
Sub-registers of Register RG_BBC0_MACEA3.
Access parameters for sub-register MACEA3 in register RG_BBC0_MACEA3
| #define SR_BBC0_MACEA4_MACEA4 |
Sub-registers of Register RG_BBC0_MACEA4.
Access parameters for sub-register MACEA4 in register RG_BBC0_MACEA4
| #define SR_BBC0_MACEA5_MACEA5 |
Sub-registers of Register RG_BBC0_MACEA5.
Access parameters for sub-register MACEA5 in register RG_BBC0_MACEA5
| #define SR_BBC0_MACEA6_MACEA6 |
Sub-registers of Register RG_BBC0_MACEA6.
Access parameters for sub-register MACEA6 in register RG_BBC0_MACEA6
| #define SR_BBC0_MACEA7_MACEA7 |
Sub-registers of Register RG_BBC0_MACEA7.
Access parameters for sub-register MACEA7 in register RG_BBC0_MACEA7
| #define SR_BBC0_MACPID0F0_MACPID0F0 |
Sub-registers of Register RG_BBC0_MACPID0F0.
Access parameters for sub-register MACPID0F0 in register RG_BBC0_MACPID0F0
| #define SR_BBC0_MACPID0F1_MACPID0F1 |
Sub-registers of Register RG_BBC0_MACPID0F1.
Access parameters for sub-register MACPID0F1 in register RG_BBC0_MACPID0F1
| #define SR_BBC0_MACPID0F2_MACPID0F2 |
Sub-registers of Register RG_BBC0_MACPID0F2.
Access parameters for sub-register MACPID0F2 in register RG_BBC0_MACPID0F2
| #define SR_BBC0_MACPID0F3_MACPID0F3 |
Sub-registers of Register RG_BBC0_MACPID0F3.
Access parameters for sub-register MACPID0F3 in register RG_BBC0_MACPID0F3
| #define SR_BBC0_MACPID1F0_MACPID1F0 |
Sub-registers of Register RG_BBC0_MACPID1F0.
Access parameters for sub-register MACPID1F0 in register RG_BBC0_MACPID1F0
| #define SR_BBC0_MACPID1F1_MACPID1F1 |
Sub-registers of Register RG_BBC0_MACPID1F1.
Access parameters for sub-register MACPID1F1 in register RG_BBC0_MACPID1F1
| #define SR_BBC0_MACPID1F2_MACPID1F2 |
Sub-registers of Register RG_BBC0_MACPID1F2.
Access parameters for sub-register MACPID1F2 in register RG_BBC0_MACPID1F2
| #define SR_BBC0_MACPID1F3_MACPID1F3 |
Sub-registers of Register RG_BBC0_MACPID1F3.
Access parameters for sub-register MACPID1F3 in register RG_BBC0_MACPID1F3
| #define SR_BBC0_MACSHA0F0_MACSHA0F0 |
Sub-registers of Register RG_BBC0_MACSHA0F0.
Access parameters for sub-register MACSHA0F0 in register RG_BBC0_MACSHA0F0
| #define SR_BBC0_MACSHA0F1_MACSHA0F1 |
Sub-registers of Register RG_BBC0_MACSHA0F1.
Access parameters for sub-register MACSHA0F1 in register RG_BBC0_MACSHA0F1
| #define SR_BBC0_MACSHA0F2_MACSHA0F2 |
Sub-registers of Register RG_BBC0_MACSHA0F2.
Access parameters for sub-register MACSHA0F2 in register RG_BBC0_MACSHA0F2
| #define SR_BBC0_MACSHA0F3_MACSHA0F3 |
Sub-registers of Register RG_BBC0_MACSHA0F3.
Access parameters for sub-register MACSHA0F3 in register RG_BBC0_MACSHA0F3
| #define SR_BBC0_MACSHA1F0_MACSHA1F0 |
Sub-registers of Register RG_BBC0_MACSHA1F0.
Access parameters for sub-register MACSHA1F0 in register RG_BBC0_MACSHA1F0
| #define SR_BBC0_MACSHA1F1_MACSHA1F1 |
Sub-registers of Register RG_BBC0_MACSHA1F1.
Access parameters for sub-register MACSHA1F1 in register RG_BBC0_MACSHA1F1
| #define SR_BBC0_MACSHA1F2_MACSHA1F2 |
Sub-registers of Register RG_BBC0_MACSHA1F2.
Access parameters for sub-register MACSHA1F2 in register RG_BBC0_MACSHA1F2
| #define SR_BBC0_MACSHA1F3_MACSHA1F3 |
Sub-registers of Register RG_BBC0_MACSHA1F3.
Access parameters for sub-register MACSHA1F3 in register RG_BBC0_MACSHA1F3
| #define SR_BBC0_OFDMC_LFO |
Access parameters for sub-register LFO in register RG_BBC0_OFDMC.
Referenced by ofdm_rfcfg().
| #define SR_BBC0_OFDMC_OPT |
Sub-registers of Register RG_BBC0_OFDMC.
Access parameters for sub-register OPT in register RG_BBC0_OFDMC
Referenced by conf_ofdm().
| #define SR_BBC0_OFDMC_POI |
Access parameters for sub-register POI in register RG_BBC0_OFDMC.
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define SR_BBC0_OFDMC_SSRX |
Access parameters for sub-register SSRX in register RG_BBC0_OFDMC.
| #define SR_BBC0_OFDMC_SSTX |
Access parameters for sub-register SSTX in register RG_BBC0_OFDMC.
| #define SR_BBC0_OFDMPHRRX_MCS |
Sub-registers of Register RG_BBC0_OFDMPHRRX.
Access parameters for sub-register MCS in register RG_BBC0_OFDMPHRRX
| #define SR_BBC0_OFDMPHRRX_RB17 |
Access parameters for sub-register RB17 in register RG_BBC0_OFDMPHRRX.
| #define SR_BBC0_OFDMPHRRX_RB18 |
Access parameters for sub-register RB18 in register RG_BBC0_OFDMPHRRX.
| #define SR_BBC0_OFDMPHRRX_RB21 |
Access parameters for sub-register RB21 in register RG_BBC0_OFDMPHRRX.
| #define SR_BBC0_OFDMPHRRX_RB5 |
Access parameters for sub-register RB5 in register RG_BBC0_OFDMPHRRX.
| #define SR_BBC0_OFDMPHRRX_SPC |
Access parameters for sub-register SPC in register RG_BBC0_OFDMPHRRX.
Referenced by ofdm_rfcfg().
| #define SR_BBC0_OFDMPHRTX_MCS |
Sub-registers of Register RG_BBC0_OFDMPHRTX.
Access parameters for sub-register MCS in register RG_BBC0_OFDMPHRTX
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define SR_BBC0_OFDMPHRTX_RB17 |
Access parameters for sub-register RB17 in register RG_BBC0_OFDMPHRTX.
| #define SR_BBC0_OFDMPHRTX_RB18 |
Access parameters for sub-register RB18 in register RG_BBC0_OFDMPHRTX.
| #define SR_BBC0_OFDMPHRTX_RB21 |
Access parameters for sub-register RB21 in register RG_BBC0_OFDMPHRTX.
| #define SR_BBC0_OFDMPHRTX_RB5 |
Access parameters for sub-register RB5 in register RG_BBC0_OFDMPHRTX.
| #define SR_BBC0_OFDMSW_PDT |
Access parameters for sub-register PDT in register RG_BBC0_OFDMSW.
Referenced by ofdm_rfcfg().
| #define SR_BBC0_OFDMSW_RXO |
Sub-registers of Register RG_BBC0_OFDMSW.
Access parameters for sub-register RXO in register RG_BBC0_OFDMSW
| #define SR_BBC0_OQPSKC0_DM |
Access parameters for sub-register DM in register RG_BBC0_OQPSKC0.
Referenced by oqpsk_rfcfg().
| #define SR_BBC0_OQPSKC0_FCHIP |
Sub-registers of Register RG_BBC0_OQPSKC0.
Access parameters for sub-register FCHIP in register RG_BBC0_OQPSKC0
Referenced by conf_leg_oqpsk(), and conf_oqpsk().
| #define SR_BBC0_OQPSKC0_MOD |
Access parameters for sub-register MOD in register RG_BBC0_OQPSKC0.
| #define SR_BBC0_OQPSKC1_PDT0 |
Sub-registers of Register RG_BBC0_OQPSKC1.
Access parameters for sub-register PDT0 in register RG_BBC0_OQPSKC1
| #define SR_BBC0_OQPSKC1_PDT1 |
Access parameters for sub-register PDT1 in register RG_BBC0_OQPSKC1.
| #define SR_BBC0_OQPSKC1_RXO |
Access parameters for sub-register RXO in register RG_BBC0_OQPSKC1.
| #define SR_BBC0_OQPSKC1_RXOLEG |
Access parameters for sub-register RXOLEG in register RG_BBC0_OQPSKC1.
| #define SR_BBC0_OQPSKC2_ENPROP |
Access parameters for sub-register ENPROP in register RG_BBC0_OQPSKC2.
| #define SR_BBC0_OQPSKC2_FCSTLEG |
Access parameters for sub-register FCSTLEG in register RG_BBC0_OQPSKC2.
| #define SR_BBC0_OQPSKC2_RPC |
Access parameters for sub-register RPC in register RG_BBC0_OQPSKC2.
Referenced by conf_oqpsk(), start_rpc(), stop_rpc(), and tal_pib_set().
| #define SR_BBC0_OQPSKC2_RXM |
Sub-registers of Register RG_BBC0_OQPSKC2.
Access parameters for sub-register RXM in register RG_BBC0_OQPSKC2
Referenced by conf_leg_oqpsk(), and conf_oqpsk().
| #define SR_BBC0_OQPSKC2_SPC |
Access parameters for sub-register SPC in register RG_BBC0_OQPSKC2.
| #define SR_BBC0_OQPSKC3_HRLEG |
Access parameters for sub-register HRLEG in register RG_BBC0_OQPSKC3.
Referenced by tal_pib_set().
| #define SR_BBC0_OQPSKC3_NSFD |
Sub-registers of Register RG_BBC0_OQPSKC3.
Access parameters for sub-register NSFD in register RG_BBC0_OQPSKC3
| #define SR_BBC0_OQPSKPHRRX_LEG |
Sub-registers of Register RG_BBC0_OQPSKPHRRX.
Access parameters for sub-register LEG in register RG_BBC0_OQPSKPHRRX
| #define SR_BBC0_OQPSKPHRRX_MOD |
Access parameters for sub-register MOD in register RG_BBC0_OQPSKPHRRX.
| #define SR_BBC0_OQPSKPHRRX_PPDUT |
Access parameters for sub-register PPDUT in register RG_BBC0_OQPSKPHRRX.
| #define SR_BBC0_OQPSKPHRRX_RB0 |
Access parameters for sub-register RB0 in register RG_BBC0_OQPSKPHRRX.
| #define SR_BBC0_OQPSKPHRTX_LEG |
Sub-registers of Register RG_BBC0_OQPSKPHRTX.
Access parameters for sub-register LEG in register RG_BBC0_OQPSKPHRTX
Referenced by conf_leg_oqpsk(), and conf_oqpsk().
| #define SR_BBC0_OQPSKPHRTX_MOD |
Access parameters for sub-register MOD in register RG_BBC0_OQPSKPHRTX.
Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().
| #define SR_BBC0_OQPSKPHRTX_PPDUT |
Access parameters for sub-register PPDUT in register RG_BBC0_OQPSKPHRTX.
| #define SR_BBC0_OQPSKPHRTX_RB0 |
Access parameters for sub-register RB0 in register RG_BBC0_OQPSKPHRTX.
| #define SR_BBC0_PC_BBEN RG_BBC0_PC, PC_BBEN_MASK, PC_BBEN_SHIFT |
Access parameters for sub-register BBEN in register RG_BBC0_PC.
Referenced by handle_ed_end_irq(), handle_tx_end_irq(), tal_generate_rand_seed(), and transmit_frame().
| #define SR_BBC0_PC_CTX RG_BBC0_PC, PC_CTX_MASK, PC_CTX_SHIFT |
Access parameters for sub-register CTX in register RG_BBC0_PC.
| #define SR_BBC0_PC_FCSFE |
Access parameters for sub-register FCSFE in register RG_BBC0_PC.
Referenced by tal_rxaack_prom_mode_ctrl().
| #define SR_BBC0_PC_FCSOK |
Access parameters for sub-register FCSOK in register RG_BBC0_PC.
Referenced by crc_check_ok().
| #define SR_BBC0_PC_FCST RG_BBC0_PC, PC_FCST_MASK, PC_FCST_SHIFT |
Access parameters for sub-register FCST in register RG_BBC0_PC.
Referenced by config_phy(), tal_pib_set(), and write_all_tal_pib_to_trx().
| #define SR_BBC0_PC_PT RG_BBC0_PC, PC_PT_MASK, PC_PT_SHIFT |
Sub-registers of Register RG_BBC0_PC.
Access parameters for sub-register PT in register RG_BBC0_PC
Referenced by conf_fsk(), conf_leg_oqpsk(), conf_ofdm(), and conf_oqpsk().
| #define SR_BBC0_PC_TXAFCS |
Access parameters for sub-register TXAFCS in register RG_BBC0_PC.
Referenced by transmit_frame().
| #define SR_BBC0_PMUC_AVG |
Access parameters for sub-register AVG in register RG_BBC0_PMUC.
| #define SR_BBC0_PMUC_CCFTS |
Access parameters for sub-register CCFTS in register RG_BBC0_PMUC.
| #define SR_BBC0_PMUC_EN |
Sub-registers of Register RG_BBC0_PMUC.
Access parameters for sub-register EN in register RG_BBC0_PMUC
| #define SR_BBC0_PMUC_FED |
Access parameters for sub-register FED in register RG_BBC0_PMUC.
| #define SR_BBC0_PMUC_IQSEL |
Access parameters for sub-register IQSEL in register RG_BBC0_PMUC.
| #define SR_BBC0_PMUC_SYNC |
Access parameters for sub-register SYNC in register RG_BBC0_PMUC.
| #define SR_BBC0_PMUI_PMUI |
Sub-registers of Register RG_BBC0_PMUI.
Access parameters for sub-register PMUI in register RG_BBC0_PMUI
| #define SR_BBC0_PMUQ_PMUQ |
Sub-registers of Register RG_BBC0_PMUQ.
Access parameters for sub-register PMUQ in register RG_BBC0_PMUQ
| #define SR_BBC0_PMUQF_PMUQF |
Sub-registers of Register RG_BBC0_PMUQF.
Access parameters for sub-register PMUQF in register RG_BBC0_PMUQF
| #define SR_BBC0_PMUVAL_PMUVAL |
Sub-registers of Register RG_BBC0_PMUVAL.
Access parameters for sub-register PMUVAL in register RG_BBC0_PMUVAL
| #define SR_BBC0_PS_TXUR RG_BBC0_PS, PS_TXUR_MASK, PS_TXUR_SHIFT |
Sub-registers of Register RG_BBC0_PS.
Access parameters for sub-register TXUR in register RG_BBC0_PS
Referenced by transmit_frame().
| #define SR_BBC0_RXFLH_RXFLH |
Sub-registers of Register RG_BBC0_RXFLH.
Access parameters for sub-register RXFLH in register RG_BBC0_RXFLH
| #define SR_BBC0_RXFLL_RXFLL |
Sub-registers of Register RG_BBC0_RXFLL.
Access parameters for sub-register RXFLL in register RG_BBC0_RXFLL
| #define SR_BBC0_TXFLH_TXFLH |
Sub-registers of Register RG_BBC0_TXFLH.
Access parameters for sub-register TXFLH in register RG_BBC0_TXFLH
| #define SR_BBC0_TXFLL_TXFLL |
Sub-registers of Register RG_BBC0_TXFLL.
Access parameters for sub-register TXFLL in register RG_BBC0_TXFLL
| #define SR_BBC1_AFC0_AFEN0 |
Sub-registers of Register RG_BBC1_AFC0.
Access parameters for sub-register AFEN0 in register RG_BBC1_AFC0
| #define SR_BBC1_AFC0_AFEN1 |
Access parameters for sub-register AFEN1 in register RG_BBC1_AFC0.
| #define SR_BBC1_AFC0_AFEN2 |
Access parameters for sub-register AFEN2 in register RG_BBC1_AFC0.
| #define SR_BBC1_AFC0_AFEN3 |
Access parameters for sub-register AFEN3 in register RG_BBC1_AFC0.
| #define SR_BBC1_AFC0_PM |
Access parameters for sub-register PM in register RG_BBC1_AFC0.
| #define SR_BBC1_AFC1_MRFT0 |
Access parameters for sub-register MRFT0 in register RG_BBC1_AFC1.
| #define SR_BBC1_AFC1_MRFT1 |
Access parameters for sub-register MRFT1 in register RG_BBC1_AFC1.
| #define SR_BBC1_AFC1_MRFT2 |
Access parameters for sub-register MRFT2 in register RG_BBC1_AFC1.
| #define SR_BBC1_AFC1_MRFT3 |
Access parameters for sub-register MRFT3 in register RG_BBC1_AFC1.
| #define SR_BBC1_AFC1_PANC0 |
Sub-registers of Register RG_BBC1_AFC1.
Access parameters for sub-register PANC0 in register RG_BBC1_AFC1
| #define SR_BBC1_AFC1_PANC1 |
Access parameters for sub-register PANC1 in register RG_BBC1_AFC1.
| #define SR_BBC1_AFC1_PANC2 |
Access parameters for sub-register PANC2 in register RG_BBC1_AFC1.
| #define SR_BBC1_AFC1_PANC3 |
Access parameters for sub-register PANC3 in register RG_BBC1_AFC1.
| #define SR_BBC1_AFFTM_AFFTM |
Sub-registers of Register RG_BBC1_AFFTM.
Access parameters for sub-register AFFTM in register RG_BBC1_AFFTM
| #define SR_BBC1_AFFVM_AFFVM |
Sub-registers of Register RG_BBC1_AFFVM.
Access parameters for sub-register AFFVM in register RG_BBC1_AFFVM
| #define SR_BBC1_AFS_AM0 RG_BBC1_AFS, AFS_AM0_MASK, AFS_AM0_SHIFT |
Sub-registers of Register RG_BBC1_AFS.
Access parameters for sub-register AM0 in register RG_BBC1_AFS
| #define SR_BBC1_AFS_AM1 RG_BBC1_AFS, AFS_AM1_MASK, AFS_AM1_SHIFT |
Access parameters for sub-register AM1 in register RG_BBC1_AFS.
| #define SR_BBC1_AFS_AM2 RG_BBC1_AFS, AFS_AM2_MASK, AFS_AM2_SHIFT |
Access parameters for sub-register AM2 in register RG_BBC1_AFS.
| #define SR_BBC1_AFS_AM3 RG_BBC1_AFS, AFS_AM3_MASK, AFS_AM3_SHIFT |
Access parameters for sub-register AM3 in register RG_BBC1_AFS.
| #define SR_BBC1_AFS_EM RG_BBC1_AFS, AFS_EM_MASK, AFS_EM_SHIFT |
Access parameters for sub-register EM in register RG_BBC1_AFS.
| #define SR_BBC1_AMAACKPD_PD0 |
Sub-registers of Register RG_BBC1_AMAACKPD.
Access parameters for sub-register PD0 in register RG_BBC1_AMAACKPD
| #define SR_BBC1_AMAACKPD_PD1 |
Access parameters for sub-register PD1 in register RG_BBC1_AMAACKPD.
| #define SR_BBC1_AMAACKPD_PD2 |
Access parameters for sub-register PD2 in register RG_BBC1_AMAACKPD.
| #define SR_BBC1_AMAACKPD_PD3 |
Access parameters for sub-register PD3 in register RG_BBC1_AMAACKPD.
| #define SR_BBC1_AMAACKTH_AMAACKTH |
Sub-registers of Register RG_BBC1_AMAACKTH.
Access parameters for sub-register AMAACKTH in register RG_BBC1_AMAACKTH
| #define SR_BBC1_AMAACKTL_AMAACKTL |
Sub-registers of Register RG_BBC1_AMAACKTL.
Access parameters for sub-register AMAACKTL in register RG_BBC1_AMAACKTL
| #define SR_BBC1_AMCS_AACK |
Access parameters for sub-register AACK in register RG_BBC1_AMCS.
| #define SR_BBC1_AMCS_AACKDR |
Access parameters for sub-register AACKDR in register RG_BBC1_AMCS.
| #define SR_BBC1_AMCS_AACKFA |
Access parameters for sub-register AACKFA in register RG_BBC1_AMCS.
| #define SR_BBC1_AMCS_AACKFT |
Access parameters for sub-register AACKFT in register RG_BBC1_AMCS.
| #define SR_BBC1_AMCS_AACKS |
Access parameters for sub-register AACKS in register RG_BBC1_AMCS.
| #define SR_BBC1_AMCS_CCAED |
Access parameters for sub-register CCAED in register RG_BBC1_AMCS.
| #define SR_BBC1_AMCS_CCATX |
Access parameters for sub-register CCATX in register RG_BBC1_AMCS.
| #define SR_BBC1_AMCS_TX2RX |
Sub-registers of Register RG_BBC1_AMCS.
Access parameters for sub-register TX2RX in register RG_BBC1_AMCS
| #define SR_BBC1_AMEDT_AMEDT |
Sub-registers of Register RG_BBC1_AMEDT.
Access parameters for sub-register AMEDT in register RG_BBC1_AMEDT
| #define SR_BBC1_CNT0_CNT0 |
Sub-registers of Register RG_BBC1_CNT0.
Access parameters for sub-register CNT0 in register RG_BBC1_CNT0
| #define SR_BBC1_CNT1_CNT1 |
Sub-registers of Register RG_BBC1_CNT1.
Access parameters for sub-register CNT1 in register RG_BBC1_CNT1
| #define SR_BBC1_CNT2_CNT2 |
Sub-registers of Register RG_BBC1_CNT2.
Access parameters for sub-register CNT2 in register RG_BBC1_CNT2
| #define SR_BBC1_CNT3_CNT3 |
Sub-registers of Register RG_BBC1_CNT3.
Access parameters for sub-register CNT3 in register RG_BBC1_CNT3
| #define SR_BBC1_CNTC_CAPRXS |
Access parameters for sub-register CAPRXS in register RG_BBC1_CNTC.
| #define SR_BBC1_CNTC_CAPTXS |
Access parameters for sub-register CAPTXS in register RG_BBC1_CNTC.
| #define SR_BBC1_CNTC_EN |
Sub-registers of Register RG_BBC1_CNTC.
Access parameters for sub-register EN in register RG_BBC1_CNTC
| #define SR_BBC1_CNTC_RSTRXS |
Access parameters for sub-register RSTRXS in register RG_BBC1_CNTC.
| #define SR_BBC1_CNTC_RSTTXS |
Access parameters for sub-register RSTTXS in register RG_BBC1_CNTC.
| #define SR_BBC1_FBLH_FBLH |
Sub-registers of Register RG_BBC1_FBLH.
Access parameters for sub-register FBLH in register RG_BBC1_FBLH
| #define SR_BBC1_FBLIH_FBLIH |
Sub-registers of Register RG_BBC1_FBLIH.
Access parameters for sub-register FBLIH in register RG_BBC1_FBLIH
| #define SR_BBC1_FBLIL_FBLIL |
Sub-registers of Register RG_BBC1_FBLIL.
Access parameters for sub-register FBLIL in register RG_BBC1_FBLIL
| #define SR_BBC1_FBLL_FBLL |
Sub-registers of Register RG_BBC1_FBLL.
Access parameters for sub-register FBLL in register RG_BBC1_FBLL
| #define SR_BBC1_FBRXE_FBRXE |
Sub-registers of Register RG_BBC1_FBRXE.
Access parameters for sub-register FBRXE in register RG_BBC1_FBRXE
| #define SR_BBC1_FBRXS_FBRXS |
Sub-registers of Register RG_BBC1_FBRXS.
Access parameters for sub-register FBRXS in register RG_BBC1_FBRXS
| #define SR_BBC1_FBTXE_FBTXE |
Sub-registers of Register RG_BBC1_FBTXE.
Access parameters for sub-register FBTXE in register RG_BBC1_FBTXE
| #define SR_BBC1_FBTXS_FBTXS |
Sub-registers of Register RG_BBC1_FBTXS.
Access parameters for sub-register FBTXS in register RG_BBC1_FBTXS
| #define SR_BBC1_FSKC0_BT |
Access parameters for sub-register BT in register RG_BBC1_FSKC0.
| #define SR_BBC1_FSKC0_MIDX |
Access parameters for sub-register MIDX in register RG_BBC1_FSKC0.
| #define SR_BBC1_FSKC0_MIDXS |
Access parameters for sub-register MIDXS in register RG_BBC1_FSKC0.
| #define SR_BBC1_FSKC0_MORD |
Sub-registers of Register RG_BBC1_FSKC0.
Access parameters for sub-register MORD in register RG_BBC1_FSKC0
| #define SR_BBC1_FSKC1_FI |
Access parameters for sub-register FI in register RG_BBC1_FSKC1.
| #define SR_BBC1_FSKC1_FSKPLH |
Access parameters for sub-register FSKPLH in register RG_BBC1_FSKC1.
| #define SR_BBC1_FSKC1_SRATE |
Sub-registers of Register RG_BBC1_FSKC1.
Access parameters for sub-register SRATE in register RG_BBC1_FSKC1
| #define SR_BBC1_FSKC2_FECIE |
Sub-registers of Register RG_BBC1_FSKC2.
Access parameters for sub-register FECIE in register RG_BBC1_FSKC2
| #define SR_BBC1_FSKC2_FECS |
Access parameters for sub-register FECS in register RG_BBC1_FSKC2.
| #define SR_BBC1_FSKC2_MSE |
Access parameters for sub-register MSE in register RG_BBC1_FSKC2.
| #define SR_BBC1_FSKC2_PDTM |
Access parameters for sub-register PDTM in register RG_BBC1_FSKC2.
| #define SR_BBC1_FSKC2_PRI |
Access parameters for sub-register PRI in register RG_BBC1_FSKC2.
| #define SR_BBC1_FSKC2_RXO |
Access parameters for sub-register RXO in register RG_BBC1_FSKC2.
| #define SR_BBC1_FSKC2_RXPTO |
Access parameters for sub-register RXPTO in register RG_BBC1_FSKC2.
| #define SR_BBC1_FSKC3_PDT |
Sub-registers of Register RG_BBC1_FSKC3.
Access parameters for sub-register PDT in register RG_BBC1_FSKC3
| #define SR_BBC1_FSKC3_SFDT |
Access parameters for sub-register SFDT in register RG_BBC1_FSKC3.
| #define SR_BBC1_FSKC4_CSFD0 |
Sub-registers of Register RG_BBC1_FSKC4.
Access parameters for sub-register CSFD0 in register RG_BBC1_FSKC4
| #define SR_BBC1_FSKC4_CSFD1 |
Access parameters for sub-register CSFD1 in register RG_BBC1_FSKC4.
| #define SR_BBC1_FSKC4_RAWRBIT |
Access parameters for sub-register RAWRBIT in register RG_BBC1_FSKC4.
| #define SR_BBC1_FSKC4_SFD32 |
Access parameters for sub-register SFD32 in register RG_BBC1_FSKC4.
| #define SR_BBC1_FSKC4_SFDQ |
Access parameters for sub-register SFDQ in register RG_BBC1_FSKC4.
| #define SR_BBC1_FSKDM_EN |
Sub-registers of Register RG_BBC1_FSKDM.
Access parameters for sub-register EN in register RG_BBC1_FSKDM
| #define SR_BBC1_FSKDM_PE |
Access parameters for sub-register PE in register RG_BBC1_FSKDM.
| #define SR_BBC1_FSKPE0_FSKPE0 |
Sub-registers of Register RG_BBC1_FSKPE0.
Access parameters for sub-register FSKPE0 in register RG_BBC1_FSKPE0
| #define SR_BBC1_FSKPE1_FSKPE1 |
Sub-registers of Register RG_BBC1_FSKPE1.
Access parameters for sub-register FSKPE1 in register RG_BBC1_FSKPE1
| #define SR_BBC1_FSKPE2_FSKPE2 |
Sub-registers of Register RG_BBC1_FSKPE2.
Access parameters for sub-register FSKPE2 in register RG_BBC1_FSKPE2
| #define SR_BBC1_FSKPHRRX_DW |
Access parameters for sub-register DW in register RG_BBC1_FSKPHRRX.
| #define SR_BBC1_FSKPHRRX_FCST |
Access parameters for sub-register FCST in register RG_BBC1_FSKPHRRX.
| #define SR_BBC1_FSKPHRRX_MS |
Access parameters for sub-register MS in register RG_BBC1_FSKPHRRX.
| #define SR_BBC1_FSKPHRRX_RB1 |
Sub-registers of Register RG_BBC1_FSKPHRRX.
Access parameters for sub-register RB1 in register RG_BBC1_FSKPHRRX
| #define SR_BBC1_FSKPHRRX_RB2 |
Access parameters for sub-register RB2 in register RG_BBC1_FSKPHRRX.
| #define SR_BBC1_FSKPHRRX_SFD |
Access parameters for sub-register SFD in register RG_BBC1_FSKPHRRX.
| #define SR_BBC1_FSKPHRTX_DW |
Access parameters for sub-register DW in register RG_BBC1_FSKPHRTX.
| #define SR_BBC1_FSKPHRTX_RB1 |
Sub-registers of Register RG_BBC1_FSKPHRTX.
Access parameters for sub-register RB1 in register RG_BBC1_FSKPHRTX
| #define SR_BBC1_FSKPHRTX_RB2 |
Access parameters for sub-register RB2 in register RG_BBC1_FSKPHRTX.
| #define SR_BBC1_FSKPHRTX_SFD |
Access parameters for sub-register SFD in register RG_BBC1_FSKPHRTX.
| #define SR_BBC1_FSKPLL_FSKPLL |
Sub-registers of Register RG_BBC1_FSKPLL.
Access parameters for sub-register FSKPLL in register RG_BBC1_FSKPLL
| #define SR_BBC1_FSKRPC_BASET |
Sub-registers of Register RG_BBC1_FSKRPC.
Access parameters for sub-register BASET in register RG_BBC1_FSKRPC
| #define SR_BBC1_FSKRPC_EN |
Access parameters for sub-register EN in register RG_BBC1_FSKRPC.
| #define SR_BBC1_FSKRPCOFFT_FSKRPCOFFT |
Sub-registers of Register RG_BBC1_FSKRPCOFFT.
Access parameters for sub-register FSKRPCOFFT in register RG_BBC1_FSKRPCOFFT
| #define SR_BBC1_FSKRPCONT_FSKRPCONT |
Sub-registers of Register RG_BBC1_FSKRPCONT.
Access parameters for sub-register FSKRPCONT in register RG_BBC1_FSKRPCONT
| #define SR_BBC1_FSKRRXFLH_FSKRRXFLH |
Sub-registers of Register RG_BBC1_FSKRRXFLH.
Access parameters for sub-register FSKRRXFLH in register RG_BBC1_FSKRRXFLH
| #define SR_BBC1_FSKRRXFLL_FSKRRXFLL |
Sub-registers of Register RG_BBC1_FSKRRXFLL.
Access parameters for sub-register FSKRRXFLL in register RG_BBC1_FSKRRXFLL
| #define SR_BBC1_FSKSFD0H_FSKSFD0H |
Sub-registers of Register RG_BBC1_FSKSFD0H.
Access parameters for sub-register FSKSFD0H in register RG_BBC1_FSKSFD0H
| #define SR_BBC1_FSKSFD0L_FSKSFD0L |
Sub-registers of Register RG_BBC1_FSKSFD0L.
Access parameters for sub-register FSKSFD0L in register RG_BBC1_FSKSFD0L
| #define SR_BBC1_FSKSFD1H_FSKSFD1H |
Sub-registers of Register RG_BBC1_FSKSFD1H.
Access parameters for sub-register FSKSFD1H in register RG_BBC1_FSKSFD1H
| #define SR_BBC1_FSKSFD1L_FSKSFD1L |
Sub-registers of Register RG_BBC1_FSKSFD1L.
Access parameters for sub-register FSKSFD1L in register RG_BBC1_FSKSFD1L
| #define SR_BBC1_IRQM_AGCH |
Access parameters for sub-register AGCH in register RG_BBC1_IRQM.
| #define SR_BBC1_IRQM_AGCR |
Access parameters for sub-register AGCR in register RG_BBC1_IRQM.
| #define SR_BBC1_IRQM_FBLI |
Access parameters for sub-register FBLI in register RG_BBC1_IRQM.
| #define SR_BBC1_IRQM_RXAM |
Access parameters for sub-register RXAM in register RG_BBC1_IRQM.
| #define SR_BBC1_IRQM_RXEM |
Access parameters for sub-register RXEM in register RG_BBC1_IRQM.
| #define SR_BBC1_IRQM_RXFE |
Access parameters for sub-register RXFE in register RG_BBC1_IRQM.
| #define SR_BBC1_IRQM_RXFS |
Sub-registers of Register RG_BBC1_IRQM.
Access parameters for sub-register RXFS in register RG_BBC1_IRQM
| #define SR_BBC1_IRQM_TXFE |
Access parameters for sub-register TXFE in register RG_BBC1_IRQM.
| #define SR_BBC1_IRQS_AGCH |
Access parameters for sub-register AGCH in register RG_BBC1_IRQS.
| #define SR_BBC1_IRQS_AGCR |
Access parameters for sub-register AGCR in register RG_BBC1_IRQS.
| #define SR_BBC1_IRQS_FBLI |
Access parameters for sub-register FBLI in register RG_BBC1_IRQS.
| #define SR_BBC1_IRQS_RXAM |
Access parameters for sub-register RXAM in register RG_BBC1_IRQS.
| #define SR_BBC1_IRQS_RXEM |
Access parameters for sub-register RXEM in register RG_BBC1_IRQS.
| #define SR_BBC1_IRQS_RXFE |
Access parameters for sub-register RXFE in register RG_BBC1_IRQS.
| #define SR_BBC1_IRQS_RXFS |
Sub-registers of Register RG_BBC1_IRQS.
Access parameters for sub-register RXFS in register RG_BBC1_IRQS
| #define SR_BBC1_IRQS_TXFE |
Access parameters for sub-register TXFE in register RG_BBC1_IRQS.
| #define SR_BBC1_MACEA0_MACEA0 |
Sub-registers of Register RG_BBC1_MACEA0.
Access parameters for sub-register MACEA0 in register RG_BBC1_MACEA0
| #define SR_BBC1_MACEA1_MACEA1 |
Sub-registers of Register RG_BBC1_MACEA1.
Access parameters for sub-register MACEA1 in register RG_BBC1_MACEA1
| #define SR_BBC1_MACEA2_MACEA2 |
Sub-registers of Register RG_BBC1_MACEA2.
Access parameters for sub-register MACEA2 in register RG_BBC1_MACEA2
| #define SR_BBC1_MACEA3_MACEA3 |
Sub-registers of Register RG_BBC1_MACEA3.
Access parameters for sub-register MACEA3 in register RG_BBC1_MACEA3
| #define SR_BBC1_MACEA4_MACEA4 |
Sub-registers of Register RG_BBC1_MACEA4.
Access parameters for sub-register MACEA4 in register RG_BBC1_MACEA4
| #define SR_BBC1_MACEA5_MACEA5 |
Sub-registers of Register RG_BBC1_MACEA5.
Access parameters for sub-register MACEA5 in register RG_BBC1_MACEA5
| #define SR_BBC1_MACEA6_MACEA6 |
Sub-registers of Register RG_BBC1_MACEA6.
Access parameters for sub-register MACEA6 in register RG_BBC1_MACEA6
| #define SR_BBC1_MACEA7_MACEA7 |
Sub-registers of Register RG_BBC1_MACEA7.
Access parameters for sub-register MACEA7 in register RG_BBC1_MACEA7
| #define SR_BBC1_MACPID0F0_MACPID0F0 |
Sub-registers of Register RG_BBC1_MACPID0F0.
Access parameters for sub-register MACPID0F0 in register RG_BBC1_MACPID0F0
| #define SR_BBC1_MACPID0F1_MACPID0F1 |
Sub-registers of Register RG_BBC1_MACPID0F1.
Access parameters for sub-register MACPID0F1 in register RG_BBC1_MACPID0F1
| #define SR_BBC1_MACPID0F2_MACPID0F2 |
Sub-registers of Register RG_BBC1_MACPID0F2.
Access parameters for sub-register MACPID0F2 in register RG_BBC1_MACPID0F2
| #define SR_BBC1_MACPID0F3_MACPID0F3 |
Sub-registers of Register RG_BBC1_MACPID0F3.
Access parameters for sub-register MACPID0F3 in register RG_BBC1_MACPID0F3
| #define SR_BBC1_MACPID1F0_MACPID1F0 |
Sub-registers of Register RG_BBC1_MACPID1F0.
Access parameters for sub-register MACPID1F0 in register RG_BBC1_MACPID1F0
| #define SR_BBC1_MACPID1F1_MACPID1F1 |
Sub-registers of Register RG_BBC1_MACPID1F1.
Access parameters for sub-register MACPID1F1 in register RG_BBC1_MACPID1F1
| #define SR_BBC1_MACPID1F2_MACPID1F2 |
Sub-registers of Register RG_BBC1_MACPID1F2.
Access parameters for sub-register MACPID1F2 in register RG_BBC1_MACPID1F2
| #define SR_BBC1_MACPID1F3_MACPID1F3 |
Sub-registers of Register RG_BBC1_MACPID1F3.
Access parameters for sub-register MACPID1F3 in register RG_BBC1_MACPID1F3
| #define SR_BBC1_MACSHA0F0_MACSHA0F0 |
Sub-registers of Register RG_BBC1_MACSHA0F0.
Access parameters for sub-register MACSHA0F0 in register RG_BBC1_MACSHA0F0
| #define SR_BBC1_MACSHA0F1_MACSHA0F1 |
Sub-registers of Register RG_BBC1_MACSHA0F1.
Access parameters for sub-register MACSHA0F1 in register RG_BBC1_MACSHA0F1
| #define SR_BBC1_MACSHA0F2_MACSHA0F2 |
Sub-registers of Register RG_BBC1_MACSHA0F2.
Access parameters for sub-register MACSHA0F2 in register RG_BBC1_MACSHA0F2
| #define SR_BBC1_MACSHA0F3_MACSHA0F3 |
Sub-registers of Register RG_BBC1_MACSHA0F3.
Access parameters for sub-register MACSHA0F3 in register RG_BBC1_MACSHA0F3
| #define SR_BBC1_MACSHA1F0_MACSHA1F0 |
Sub-registers of Register RG_BBC1_MACSHA1F0.
Access parameters for sub-register MACSHA1F0 in register RG_BBC1_MACSHA1F0
| #define SR_BBC1_MACSHA1F1_MACSHA1F1 |
Sub-registers of Register RG_BBC1_MACSHA1F1.
Access parameters for sub-register MACSHA1F1 in register RG_BBC1_MACSHA1F1
| #define SR_BBC1_MACSHA1F2_MACSHA1F2 |
Sub-registers of Register RG_BBC1_MACSHA1F2.
Access parameters for sub-register MACSHA1F2 in register RG_BBC1_MACSHA1F2
| #define SR_BBC1_MACSHA1F3_MACSHA1F3 |
Sub-registers of Register RG_BBC1_MACSHA1F3.
Access parameters for sub-register MACSHA1F3 in register RG_BBC1_MACSHA1F3
| #define SR_BBC1_OFDMC_LFO |
Access parameters for sub-register LFO in register RG_BBC1_OFDMC.
| #define SR_BBC1_OFDMC_OPT |
Sub-registers of Register RG_BBC1_OFDMC.
Access parameters for sub-register OPT in register RG_BBC1_OFDMC
| #define SR_BBC1_OFDMC_POI |
Access parameters for sub-register POI in register RG_BBC1_OFDMC.
| #define SR_BBC1_OFDMC_SSRX |
Access parameters for sub-register SSRX in register RG_BBC1_OFDMC.
| #define SR_BBC1_OFDMC_SSTX |
Access parameters for sub-register SSTX in register RG_BBC1_OFDMC.
| #define SR_BBC1_OFDMPHRRX_MCS |
Sub-registers of Register RG_BBC1_OFDMPHRRX.
Access parameters for sub-register MCS in register RG_BBC1_OFDMPHRRX
| #define SR_BBC1_OFDMPHRRX_RB17 |
Access parameters for sub-register RB17 in register RG_BBC1_OFDMPHRRX.
| #define SR_BBC1_OFDMPHRRX_RB18 |
Access parameters for sub-register RB18 in register RG_BBC1_OFDMPHRRX.
| #define SR_BBC1_OFDMPHRRX_RB21 |
Access parameters for sub-register RB21 in register RG_BBC1_OFDMPHRRX.
| #define SR_BBC1_OFDMPHRRX_RB5 |
Access parameters for sub-register RB5 in register RG_BBC1_OFDMPHRRX.
| #define SR_BBC1_OFDMPHRRX_SPC |
Access parameters for sub-register SPC in register RG_BBC1_OFDMPHRRX.
| #define SR_BBC1_OFDMPHRTX_MCS |
Sub-registers of Register RG_BBC1_OFDMPHRTX.
Access parameters for sub-register MCS in register RG_BBC1_OFDMPHRTX
| #define SR_BBC1_OFDMPHRTX_RB17 |
Access parameters for sub-register RB17 in register RG_BBC1_OFDMPHRTX.
| #define SR_BBC1_OFDMPHRTX_RB18 |
Access parameters for sub-register RB18 in register RG_BBC1_OFDMPHRTX.
| #define SR_BBC1_OFDMPHRTX_RB21 |
Access parameters for sub-register RB21 in register RG_BBC1_OFDMPHRTX.
| #define SR_BBC1_OFDMPHRTX_RB5 |
Access parameters for sub-register RB5 in register RG_BBC1_OFDMPHRTX.
| #define SR_BBC1_OFDMSW_PDT |
Access parameters for sub-register PDT in register RG_BBC1_OFDMSW.
| #define SR_BBC1_OFDMSW_RXO |
Sub-registers of Register RG_BBC1_OFDMSW.
Access parameters for sub-register RXO in register RG_BBC1_OFDMSW
| #define SR_BBC1_OQPSKC0_DM |
Access parameters for sub-register DM in register RG_BBC1_OQPSKC0.
| #define SR_BBC1_OQPSKC0_FCHIP |
Sub-registers of Register RG_BBC1_OQPSKC0.
Access parameters for sub-register FCHIP in register RG_BBC1_OQPSKC0
| #define SR_BBC1_OQPSKC0_MOD |
Access parameters for sub-register MOD in register RG_BBC1_OQPSKC0.
| #define SR_BBC1_OQPSKC1_PDT0 |
Sub-registers of Register RG_BBC1_OQPSKC1.
Access parameters for sub-register PDT0 in register RG_BBC1_OQPSKC1
Referenced by tal_set_rx_sensitivity_level().
| #define SR_BBC1_OQPSKC1_PDT1 |
Access parameters for sub-register PDT1 in register RG_BBC1_OQPSKC1.
| #define SR_BBC1_OQPSKC1_RXO |
Access parameters for sub-register RXO in register RG_BBC1_OQPSKC1.
| #define SR_BBC1_OQPSKC1_RXOLEG |
Access parameters for sub-register RXOLEG in register RG_BBC1_OQPSKC1.
| #define SR_BBC1_OQPSKC2_ENPROP |
Access parameters for sub-register ENPROP in register RG_BBC1_OQPSKC2.
| #define SR_BBC1_OQPSKC2_FCSTLEG |
Access parameters for sub-register FCSTLEG in register RG_BBC1_OQPSKC2.
| #define SR_BBC1_OQPSKC2_RPC |
Access parameters for sub-register RPC in register RG_BBC1_OQPSKC2.
| #define SR_BBC1_OQPSKC2_RXM |
Sub-registers of Register RG_BBC1_OQPSKC2.
Access parameters for sub-register RXM in register RG_BBC1_OQPSKC2
| #define SR_BBC1_OQPSKC2_SPC |
Access parameters for sub-register SPC in register RG_BBC1_OQPSKC2.
| #define SR_BBC1_OQPSKC3_HRLEG |
Access parameters for sub-register HRLEG in register RG_BBC1_OQPSKC3.
| #define SR_BBC1_OQPSKC3_NSFD |
Sub-registers of Register RG_BBC1_OQPSKC3.
Access parameters for sub-register NSFD in register RG_BBC1_OQPSKC3
| #define SR_BBC1_OQPSKPHRRX_LEG |
Sub-registers of Register RG_BBC1_OQPSKPHRRX.
Access parameters for sub-register LEG in register RG_BBC1_OQPSKPHRRX
| #define SR_BBC1_OQPSKPHRRX_MOD |
Access parameters for sub-register MOD in register RG_BBC1_OQPSKPHRRX.
| #define SR_BBC1_OQPSKPHRRX_PPDUT |
Access parameters for sub-register PPDUT in register RG_BBC1_OQPSKPHRRX.
| #define SR_BBC1_OQPSKPHRRX_RB0 |
Access parameters for sub-register RB0 in register RG_BBC1_OQPSKPHRRX.
| #define SR_BBC1_OQPSKPHRTX_LEG |
Sub-registers of Register RG_BBC1_OQPSKPHRTX.
Access parameters for sub-register LEG in register RG_BBC1_OQPSKPHRTX
| #define SR_BBC1_OQPSKPHRTX_MOD |
Access parameters for sub-register MOD in register RG_BBC1_OQPSKPHRTX.
| #define SR_BBC1_OQPSKPHRTX_PPDUT |
Access parameters for sub-register PPDUT in register RG_BBC1_OQPSKPHRTX.
| #define SR_BBC1_OQPSKPHRTX_RB0 |
Access parameters for sub-register RB0 in register RG_BBC1_OQPSKPHRTX.
| #define SR_BBC1_PC_BBEN RG_BBC1_PC, PC_BBEN_MASK, PC_BBEN_SHIFT |
Access parameters for sub-register BBEN in register RG_BBC1_PC.
| #define SR_BBC1_PC_CTX RG_BBC1_PC, PC_CTX_MASK, PC_CTX_SHIFT |
Access parameters for sub-register CTX in register RG_BBC1_PC.
| #define SR_BBC1_PC_FCSFE |
Access parameters for sub-register FCSFE in register RG_BBC1_PC.
| #define SR_BBC1_PC_FCSOK |
Access parameters for sub-register FCSOK in register RG_BBC1_PC.
| #define SR_BBC1_PC_FCST RG_BBC1_PC, PC_FCST_MASK, PC_FCST_SHIFT |
Access parameters for sub-register FCST in register RG_BBC1_PC.
| #define SR_BBC1_PC_PT RG_BBC1_PC, PC_PT_MASK, PC_PT_SHIFT |
Sub-registers of Register RG_BBC1_PC.
Access parameters for sub-register PT in register RG_BBC1_PC
| #define SR_BBC1_PC_TXAFCS |
Access parameters for sub-register TXAFCS in register RG_BBC1_PC.
| #define SR_BBC1_PMUC_AVG |
Access parameters for sub-register AVG in register RG_BBC1_PMUC.
| #define SR_BBC1_PMUC_CCFTS |
Access parameters for sub-register CCFTS in register RG_BBC1_PMUC.
| #define SR_BBC1_PMUC_EN |
Sub-registers of Register RG_BBC1_PMUC.
Access parameters for sub-register EN in register RG_BBC1_PMUC
| #define SR_BBC1_PMUC_FED |
Access parameters for sub-register FED in register RG_BBC1_PMUC.
| #define SR_BBC1_PMUC_IQSEL |
Access parameters for sub-register IQSEL in register RG_BBC1_PMUC.
| #define SR_BBC1_PMUC_SYNC |
Access parameters for sub-register SYNC in register RG_BBC1_PMUC.
| #define SR_BBC1_PMUI_PMUI |
Sub-registers of Register RG_BBC1_PMUI.
Access parameters for sub-register PMUI in register RG_BBC1_PMUI
| #define SR_BBC1_PMUQ_PMUQ |
Sub-registers of Register RG_BBC1_PMUQ.
Access parameters for sub-register PMUQ in register RG_BBC1_PMUQ
| #define SR_BBC1_PMUQF_PMUQF |
Sub-registers of Register RG_BBC1_PMUQF.
Access parameters for sub-register PMUQF in register RG_BBC1_PMUQF
| #define SR_BBC1_PMUVAL_PMUVAL |
Sub-registers of Register RG_BBC1_PMUVAL.
Access parameters for sub-register PMUVAL in register RG_BBC1_PMUVAL
| #define SR_BBC1_PS_TXUR RG_BBC1_PS, PS_TXUR_MASK, PS_TXUR_SHIFT |
Sub-registers of Register RG_BBC1_PS.
Access parameters for sub-register TXUR in register RG_BBC1_PS
| #define SR_BBC1_RXFLH_RXFLH |
Sub-registers of Register RG_BBC1_RXFLH.
Access parameters for sub-register RXFLH in register RG_BBC1_RXFLH
| #define SR_BBC1_RXFLL_RXFLL |
Sub-registers of Register RG_BBC1_RXFLL.
Access parameters for sub-register RXFLL in register RG_BBC1_RXFLL
| #define SR_BBC1_TXFLH_TXFLH |
Sub-registers of Register RG_BBC1_TXFLH.
Access parameters for sub-register TXFLH in register RG_BBC1_TXFLH
| #define SR_BBC1_TXFLL_TXFLL |
Sub-registers of Register RG_BBC1_TXFLL.
Access parameters for sub-register TXFLL in register RG_BBC1_TXFLL
| #define SR_RF09_AGCC_AGCI |
Access parameters for sub-register AGCI in register RG_RF09_AGCC.
| #define SR_RF09_AGCC_AVGS |
Access parameters for sub-register AVGS in register RG_RF09_AGCC.
| #define SR_RF09_AGCC_EN |
Sub-registers of Register RG_RF09_AGCC.
Access parameters for sub-register EN in register RG_RF09_AGCC
| #define SR_RF09_AGCC_FRZC |
Access parameters for sub-register FRZC in register RG_RF09_AGCC.
| #define SR_RF09_AGCC_FRZS |
Access parameters for sub-register FRZS in register RG_RF09_AGCC.
Referenced by cca_start().
| #define SR_RF09_AGCC_RST |
Access parameters for sub-register RST in register RG_RF09_AGCC.
| #define SR_RF09_AGCS_GCW |
Sub-registers of Register RG_RF09_AGCS.
Access parameters for sub-register GCW in register RG_RF09_AGCS
| #define SR_RF09_AGCS_TGT |
Access parameters for sub-register TGT in register RG_RF09_AGCS.
| #define SR_RF09_AUXS_AGCMAP |
Access parameters for sub-register AGCMAP in register RG_RF09_AUXS.
| #define SR_RF09_AUXS_AVEN |
Access parameters for sub-register AVEN in register RG_RF09_AUXS.
Referenced by trx_config().
| #define SR_RF09_AUXS_AVEXT |
Access parameters for sub-register AVEXT in register RG_RF09_AUXS.
| #define SR_RF09_AUXS_AVS |
Access parameters for sub-register AVS in register RG_RF09_AUXS.
| #define SR_RF09_AUXS_EXTLNABYP |
Access parameters for sub-register EXTLNABYP in register RG_RF09_AUXS.
| #define SR_RF09_AUXS_PAVC |
Sub-registers of Register RG_RF09_AUXS.
Access parameters for sub-register PAVC in register RG_RF09_AUXS
| #define SR_RF09_CCF0H_CCF0H |
Sub-registers of Register RG_RF09_CCF0H.
Access parameters for sub-register CCF0H in register RG_RF09_CCF0H
| #define SR_RF09_CCF0L_CCF0L |
Sub-registers of Register RG_RF09_CCF0L.
Access parameters for sub-register CCF0L in register RG_RF09_CCF0L
| #define SR_RF09_CMD_CMD RG_RF09_CMD, CMD_CMD_MASK, CMD_CMD_SHIFT |
Sub-registers of Register RG_RF09_CMD.
Access parameters for sub-register CMD in register RG_RF09_CMD
Referenced by tal_generate_rand_seed().
| #define SR_RF09_CNL_CNL RG_RF09_CNL, CNL_CNL_MASK, CNL_CNL_SHIFT |
Sub-registers of Register RG_RF09_CNL.
Access parameters for sub-register CNL in register RG_RF09_CNL
| #define SR_RF09_CNM_CM RG_RF09_CNM, CNM_CM_MASK, CNM_CM_SHIFT |
Access parameters for sub-register CM in register RG_RF09_CNM.
| #define SR_RF09_CNM_CNH RG_RF09_CNM, CNM_CNH_MASK, CNM_CNH_SHIFT |
Sub-registers of Register RG_RF09_CNM.
Access parameters for sub-register CNH in register RG_RF09_CNM
| #define SR_RF09_CS_CS RG_RF09_CS, CS_CS_MASK, CS_CS_SHIFT |
Sub-registers of Register RG_RF09_CS.
Access parameters for sub-register CS in register RG_RF09_CS
| #define SR_RF09_EDC_EDM RG_RF09_EDC, EDC_EDM_MASK, EDC_EDM_SHIFT |
Sub-registers of Register RG_RF09_EDC.
Access parameters for sub-register EDM in register RG_RF09_EDC
Referenced by handle_ed_end_irq().
| #define SR_RF09_EDD_DF RG_RF09_EDD, EDD_DF_MASK, EDD_DF_SHIFT |
Access parameters for sub-register DF in register RG_RF09_EDD.
| #define SR_RF09_EDD_DTB RG_RF09_EDD, EDD_DTB_MASK, EDD_DTB_SHIFT |
Sub-registers of Register RG_RF09_EDD.
Access parameters for sub-register DTB in register RG_RF09_EDD
| #define SR_RF09_EDV_EDV RG_RF09_EDV, EDV_EDV_MASK, EDV_EDV_SHIFT |
Sub-registers of Register RG_RF09_EDV.
Access parameters for sub-register EDV in register RG_RF09_EDV
| #define SR_RF09_IRQM_BATLOW |
Access parameters for sub-register BATLOW in register RG_RF09_IRQM.
| #define SR_RF09_IRQM_EDC |
Access parameters for sub-register EDC in register RG_RF09_IRQM.
Referenced by handle_ed_end_irq().
| #define SR_RF09_IRQM_IQIFSF |
Access parameters for sub-register IQIFSF in register RG_RF09_IRQM.
| #define SR_RF09_IRQM_TRXERR |
Access parameters for sub-register TRXERR in register RG_RF09_IRQM.
| #define SR_RF09_IRQM_TRXRDY |
Access parameters for sub-register TRXRDY in register RG_RF09_IRQM.
| #define SR_RF09_IRQM_WAKEUP |
Sub-registers of Register RG_RF09_IRQM.
Access parameters for sub-register WAKEUP in register RG_RF09_IRQM
| #define SR_RF09_IRQS_BATLOW |
Access parameters for sub-register BATLOW in register RG_RF09_IRQS.
| #define SR_RF09_IRQS_EDC |
Access parameters for sub-register EDC in register RG_RF09_IRQS.
| #define SR_RF09_IRQS_IQIFSF |
Access parameters for sub-register IQIFSF in register RG_RF09_IRQS.
| #define SR_RF09_IRQS_TRXERR |
Access parameters for sub-register TRXERR in register RG_RF09_IRQS.
| #define SR_RF09_IRQS_TRXRDY |
Access parameters for sub-register TRXRDY in register RG_RF09_IRQS.
| #define SR_RF09_IRQS_WAKEUP |
Sub-registers of Register RG_RF09_IRQS.
Access parameters for sub-register WAKEUP in register RG_RF09_IRQS
| #define SR_RF09_PAC_PACUR |
Access parameters for sub-register PACUR in register RG_RF09_PAC.
| #define SR_RF09_PAC_TXPWR |
Sub-registers of Register RG_RF09_PAC.
Access parameters for sub-register TXPWR in register RG_RF09_PAC
Referenced by set_tx_pwr(), and tal_get_curr_trx_config().
| #define SR_RF09_PADFE_PADFE |
Sub-registers of Register RG_RF09_PADFE.
Access parameters for sub-register PADFE in register RG_RF09_PADFE
| #define SR_RF09_PLL_LBW RG_RF09_PLL, PLL_LBW_MASK, PLL_LBW_SHIFT |
Access parameters for sub-register LBW in register RG_RF09_PLL.
| #define SR_RF09_PLL_LS RG_RF09_PLL, PLL_LS_MASK, PLL_LS_SHIFT |
Sub-registers of Register RG_RF09_PLL.
Access parameters for sub-register LS in register RG_RF09_PLL
Referenced by wait_for_freq_settling().
| #define SR_RF09_PLLCF_CF |
Sub-registers of Register RG_RF09_PLLCF.
Access parameters for sub-register CF in register RG_RF09_PLLCF
| #define SR_RF09_RNDV_RNDV |
Sub-registers of Register RG_RF09_RNDV.
Access parameters for sub-register RNDV in register RG_RF09_RNDV
| #define SR_RF09_RSSI_RSSI |
Sub-registers of Register RG_RF09_RSSI.
Access parameters for sub-register RSSI in register RG_RF09_RSSI
| #define SR_RF09_RXBWC_BW |
Sub-registers of Register RG_RF09_RXBWC.
Access parameters for sub-register BW in register RG_RF09_RXBWC
| #define SR_RF09_RXBWC_IFI |
Access parameters for sub-register IFI in register RG_RF09_RXBWC.
| #define SR_RF09_RXBWC_IFS |
Access parameters for sub-register IFS in register RG_RF09_RXBWC.
| #define SR_RF09_RXDFE_RCUT |
Access parameters for sub-register RCUT in register RG_RF09_RXDFE.
| #define SR_RF09_RXDFE_SR |
Sub-registers of Register RG_RF09_RXDFE.
Access parameters for sub-register SR in register RG_RF09_RXDFE
| #define SR_RF09_STATE_STATE |
Sub-registers of Register RG_RF09_STATE.
Access parameters for sub-register STATE in register RG_RF09_STATE
Referenced by tal_get_trx_status().
| #define SR_RF09_TXCI_DCOI |
Sub-registers of Register RG_RF09_TXCI.
Access parameters for sub-register DCOI in register RG_RF09_TXCI
| #define SR_RF09_TXCQ_DCOQ |
Sub-registers of Register RG_RF09_TXCQ.
Access parameters for sub-register DCOQ in register RG_RF09_TXCQ
| #define SR_RF09_TXCUTC_LPFCUT |
Sub-registers of Register RG_RF09_TXCUTC.
Access parameters for sub-register LPFCUT in register RG_RF09_TXCUTC
| #define SR_RF09_TXCUTC_PARAMP |
Access parameters for sub-register PARAMP in register RG_RF09_TXCUTC.
Referenced by ofdm_rfcfg(), and oqpsk_rfcfg().
| #define SR_RF09_TXDACI_ENTXDACID |
Access parameters for sub-register ENTXDACID in register RG_RF09_TXDACI.
| #define SR_RF09_TXDACI_TXDACID |
Sub-registers of Register RG_RF09_TXDACI.
Access parameters for sub-register TXDACID in register RG_RF09_TXDACI
| #define SR_RF09_TXDACQ_ENTXDACQD |
Access parameters for sub-register ENTXDACQD in register RG_RF09_TXDACQ.
| #define SR_RF09_TXDACQ_TXDACQD |
Sub-registers of Register RG_RF09_TXDACQ.
Access parameters for sub-register TXDACQD in register RG_RF09_TXDACQ
| #define SR_RF09_TXDFE_DM |
Access parameters for sub-register DM in register RG_RF09_TXDFE.
| #define SR_RF09_TXDFE_RCUT |
Access parameters for sub-register RCUT in register RG_RF09_TXDFE.
| #define SR_RF09_TXDFE_SR |
Sub-registers of Register RG_RF09_TXDFE.
Access parameters for sub-register SR in register RG_RF09_TXDFE
| #define SR_RF24_AGCC_AGCI |
Access parameters for sub-register AGCI in register RG_RF24_AGCC.
| #define SR_RF24_AGCC_AVGS |
Access parameters for sub-register AVGS in register RG_RF24_AGCC.
| #define SR_RF24_AGCC_EN |
Sub-registers of Register RG_RF24_AGCC.
Access parameters for sub-register EN in register RG_RF24_AGCC
| #define SR_RF24_AGCC_FRZC |
Access parameters for sub-register FRZC in register RG_RF24_AGCC.
| #define SR_RF24_AGCC_FRZS |
Access parameters for sub-register FRZS in register RG_RF24_AGCC.
| #define SR_RF24_AGCC_RST |
Access parameters for sub-register RST in register RG_RF24_AGCC.
| #define SR_RF24_AGCS_GCW |
Sub-registers of Register RG_RF24_AGCS.
Access parameters for sub-register GCW in register RG_RF24_AGCS
| #define SR_RF24_AGCS_TGT |
Access parameters for sub-register TGT in register RG_RF24_AGCS.
| #define SR_RF24_AUXS_AGCMAP |
Access parameters for sub-register AGCMAP in register RG_RF24_AUXS.
| #define SR_RF24_AUXS_AVEN |
Access parameters for sub-register AVEN in register RG_RF24_AUXS.
| #define SR_RF24_AUXS_AVEXT |
Access parameters for sub-register AVEXT in register RG_RF24_AUXS.
| #define SR_RF24_AUXS_AVS |
Access parameters for sub-register AVS in register RG_RF24_AUXS.
| #define SR_RF24_AUXS_EXTLNABYP |
Access parameters for sub-register EXTLNABYP in register RG_RF24_AUXS.
| #define SR_RF24_AUXS_PAVC |
Sub-registers of Register RG_RF24_AUXS.
Access parameters for sub-register PAVC in register RG_RF24_AUXS
| #define SR_RF24_CCF0H_CCF0H |
Sub-registers of Register RG_RF24_CCF0H.
Access parameters for sub-register CCF0H in register RG_RF24_CCF0H
| #define SR_RF24_CCF0L_CCF0L |
Sub-registers of Register RG_RF24_CCF0L.
Access parameters for sub-register CCF0L in register RG_RF24_CCF0L
| #define SR_RF24_CMD_CMD RG_RF24_CMD, CMD_CMD_MASK, CMD_CMD_SHIFT |
Sub-registers of Register RG_RF24_CMD.
Access parameters for sub-register CMD in register RG_RF24_CMD
| #define SR_RF24_CNL_CNL RG_RF24_CNL, CNL_CNL_MASK, CNL_CNL_SHIFT |
Sub-registers of Register RG_RF24_CNL.
Access parameters for sub-register CNL in register RG_RF24_CNL
| #define SR_RF24_CNM_CM RG_RF24_CNM, CNM_CM_MASK, CNM_CM_SHIFT |
Access parameters for sub-register CM in register RG_RF24_CNM.
| #define SR_RF24_CNM_CNH RG_RF24_CNM, CNM_CNH_MASK, CNM_CNH_SHIFT |
Sub-registers of Register RG_RF24_CNM.
Access parameters for sub-register CNH in register RG_RF24_CNM
| #define SR_RF24_CS_CS RG_RF24_CS, CS_CS_MASK, CS_CS_SHIFT |
Sub-registers of Register RG_RF24_CS.
Access parameters for sub-register CS in register RG_RF24_CS
| #define SR_RF24_EDC_EDM RG_RF24_EDC, EDC_EDM_MASK, EDC_EDM_SHIFT |
Sub-registers of Register RG_RF24_EDC.
Access parameters for sub-register EDM in register RG_RF24_EDC
| #define SR_RF24_EDD_DF RG_RF24_EDD, EDD_DF_MASK, EDD_DF_SHIFT |
Access parameters for sub-register DF in register RG_RF24_EDD.
| #define SR_RF24_EDD_DTB RG_RF24_EDD, EDD_DTB_MASK, EDD_DTB_SHIFT |
Sub-registers of Register RG_RF24_EDD.
Access parameters for sub-register DTB in register RG_RF24_EDD
| #define SR_RF24_EDV_EDV RG_RF24_EDV, EDV_EDV_MASK, EDV_EDV_SHIFT |
Sub-registers of Register RG_RF24_EDV.
Access parameters for sub-register EDV in register RG_RF24_EDV
| #define SR_RF24_IRQM_BATLOW |
Access parameters for sub-register BATLOW in register RG_RF24_IRQM.
| #define SR_RF24_IRQM_EDC |
Access parameters for sub-register EDC in register RG_RF24_IRQM.
| #define SR_RF24_IRQM_IQIFSF |
Access parameters for sub-register IQIFSF in register RG_RF24_IRQM.
| #define SR_RF24_IRQM_TRXERR |
Access parameters for sub-register TRXERR in register RG_RF24_IRQM.
| #define SR_RF24_IRQM_TRXRDY |
Access parameters for sub-register TRXRDY in register RG_RF24_IRQM.
| #define SR_RF24_IRQM_WAKEUP |
Sub-registers of Register RG_RF24_IRQM.
Access parameters for sub-register WAKEUP in register RG_RF24_IRQM
| #define SR_RF24_IRQS_BATLOW |
Access parameters for sub-register BATLOW in register RG_RF24_IRQS.
| #define SR_RF24_IRQS_EDC |
Access parameters for sub-register EDC in register RG_RF24_IRQS.
| #define SR_RF24_IRQS_IQIFSF |
Access parameters for sub-register IQIFSF in register RG_RF24_IRQS.
| #define SR_RF24_IRQS_TRXERR |
Access parameters for sub-register TRXERR in register RG_RF24_IRQS.
| #define SR_RF24_IRQS_TRXRDY |
Access parameters for sub-register TRXRDY in register RG_RF24_IRQS.
| #define SR_RF24_IRQS_WAKEUP |
Sub-registers of Register RG_RF24_IRQS.
Access parameters for sub-register WAKEUP in register RG_RF24_IRQS
| #define SR_RF24_PAC_PACUR |
Access parameters for sub-register PACUR in register RG_RF24_PAC.
| #define SR_RF24_PAC_TXPWR |
Sub-registers of Register RG_RF24_PAC.
Access parameters for sub-register TXPWR in register RG_RF24_PAC
| #define SR_RF24_PADFE_PADFE |
Sub-registers of Register RG_RF24_PADFE.
Access parameters for sub-register PADFE in register RG_RF24_PADFE
| #define SR_RF24_PLL_LBW RG_RF24_PLL, PLL_LBW_MASK, PLL_LBW_SHIFT |
Access parameters for sub-register LBW in register RG_RF24_PLL.
| #define SR_RF24_PLL_LS RG_RF24_PLL, PLL_LS_MASK, PLL_LS_SHIFT |
Sub-registers of Register RG_RF24_PLL.
Access parameters for sub-register LS in register RG_RF24_PLL
| #define SR_RF24_PLLCF_CF |
Sub-registers of Register RG_RF24_PLLCF.
Access parameters for sub-register CF in register RG_RF24_PLLCF
| #define SR_RF24_RNDV_RNDV |
Sub-registers of Register RG_RF24_RNDV.
Access parameters for sub-register RNDV in register RG_RF24_RNDV
| #define SR_RF24_RSSI_RSSI |
Sub-registers of Register RG_RF24_RSSI.
Access parameters for sub-register RSSI in register RG_RF24_RSSI
| #define SR_RF24_RXBWC_BW |
Sub-registers of Register RG_RF24_RXBWC.
Access parameters for sub-register BW in register RG_RF24_RXBWC
| #define SR_RF24_RXBWC_IFI |
Access parameters for sub-register IFI in register RG_RF24_RXBWC.
| #define SR_RF24_RXBWC_IFS |
Access parameters for sub-register IFS in register RG_RF24_RXBWC.
| #define SR_RF24_RXDFE_RCUT |
Access parameters for sub-register RCUT in register RG_RF24_RXDFE.
| #define SR_RF24_RXDFE_SR |
Sub-registers of Register RG_RF24_RXDFE.
Access parameters for sub-register SR in register RG_RF24_RXDFE
| #define SR_RF24_STATE_STATE |
Sub-registers of Register RG_RF24_STATE.
Access parameters for sub-register STATE in register RG_RF24_STATE
| #define SR_RF24_TXCI_DCOI |
Sub-registers of Register RG_RF24_TXCI.
Access parameters for sub-register DCOI in register RG_RF24_TXCI
| #define SR_RF24_TXCQ_DCOQ |
Sub-registers of Register RG_RF24_TXCQ.
Access parameters for sub-register DCOQ in register RG_RF24_TXCQ
| #define SR_RF24_TXCUTC_LPFCUT |
Sub-registers of Register RG_RF24_TXCUTC.
Access parameters for sub-register LPFCUT in register RG_RF24_TXCUTC
| #define SR_RF24_TXCUTC_PARAMP |
Access parameters for sub-register PARAMP in register RG_RF24_TXCUTC.
| #define SR_RF24_TXDACI_ENTXDACID |
Access parameters for sub-register ENTXDACID in register RG_RF24_TXDACI.
| #define SR_RF24_TXDACI_TXDACID |
Sub-registers of Register RG_RF24_TXDACI.
Access parameters for sub-register TXDACID in register RG_RF24_TXDACI
| #define SR_RF24_TXDACQ_ENTXDACQD |
Access parameters for sub-register ENTXDACQD in register RG_RF24_TXDACQ.
| #define SR_RF24_TXDACQ_TXDACQD |
Sub-registers of Register RG_RF24_TXDACQ.
Access parameters for sub-register TXDACQD in register RG_RF24_TXDACQ
| #define SR_RF24_TXDFE_DM |
Access parameters for sub-register DM in register RG_RF24_TXDFE.
| #define SR_RF24_TXDFE_RCUT |
Access parameters for sub-register RCUT in register RG_RF24_TXDFE.
| #define SR_RF24_TXDFE_SR |
Sub-registers of Register RG_RF24_TXDFE.
Access parameters for sub-register SR in register RG_RF24_TXDFE
| #define SR_RF_BMDVC_BMHR |
Access parameters for sub-register BMHR in register RG_RF_BMDVC.
| #define SR_RF_BMDVC_BMS |
Access parameters for sub-register BMS in register RG_RF_BMDVC.
| #define SR_RF_BMDVC_BMVTH |
Sub-registers of Register RG_RF_BMDVC.
Access parameters for sub-register BMVTH in register RG_RF_BMDVC
| #define SR_RF_CFG_DRV RG_RF_CFG, CFG_DRV_MASK, CFG_DRV_SHIFT |
| #define SR_RF_CFG_IRQMM |
Access parameters for sub-register IRQMM in register RG_RF_CFG.
| #define SR_RF_CFG_IRQP RG_RF_CFG, CFG_IRQP_MASK, CFG_IRQP_SHIFT |
Access parameters for sub-register IRQP in register RG_RF_CFG.
Referenced by trx_init().
| #define SR_RF_CLKO_DRV |
Access parameters for sub-register DRV in register RG_RF_CLKO.
| #define SR_RF_CLKO_OS RG_RF_CLKO, CLKO_OS_MASK, CLKO_OS_SHIFT |
Sub-registers of Register RG_RF_CLKO.
Access parameters for sub-register OS in register RG_RF_CLKO
Referenced by trx_init().
| #define SR_RF_IQIFC0_CMV |
Access parameters for sub-register CMV in register RG_RF_IQIFC0.
| #define SR_RF_IQIFC0_CMV1V2 |
Access parameters for sub-register CMV1V2 in register RG_RF_IQIFC0.
| #define SR_RF_IQIFC0_DRV |
Access parameters for sub-register DRV in register RG_RF_IQIFC0.
| #define SR_RF_IQIFC0_EEC |
Sub-registers of Register RG_RF_IQIFC0.
Access parameters for sub-register EEC in register RG_RF_IQIFC0
Referenced by trx_config().
| #define SR_RF_IQIFC0_EXTLB |
Access parameters for sub-register EXTLB in register RG_RF_IQIFC0.
| #define SR_RF_IQIFC0_SF |
Access parameters for sub-register SF in register RG_RF_IQIFC0.
| #define SR_RF_IQIFC1_CHPM |
Access parameters for sub-register CHPM in register RG_RF_IQIFC1.
Referenced by trx_config().
| #define SR_RF_IQIFC1_FAILSF |
Access parameters for sub-register FAILSF in register RG_RF_IQIFC1.
| #define SR_RF_IQIFC1_SKEWDRV |
Sub-registers of Register RG_RF_IQIFC1.
Access parameters for sub-register SKEWDRV in register RG_RF_IQIFC1
| #define SR_RF_IQIFC2_SYNC |
Sub-registers of Register RG_RF_IQIFC2.
Access parameters for sub-register SYNC in register RG_RF_IQIFC2
| #define SR_RF_PN_PN RG_RF_PN, PN_PN_MASK, PN_PN_SHIFT |
| #define SR_RF_RST_CMD RG_RF_RST, RST_CMD_MASK, RST_CMD_SHIFT |
| #define SR_RF_VN_VN RG_RF_VN, VN_VN_MASK, VN_VN_SHIFT |
| #define SR_RF_XOC_FS RG_RF_XOC, XOC_FS_MASK, XOC_FS_SHIFT |
Access parameters for sub-register FS in register RG_RF_XOC.
| #define SR_RF_XOC_TRIM RG_RF_XOC, XOC_TRIM_MASK, XOC_TRIM_SHIFT |
| #define STATE_STATE_MASK 0x07 |
Sub-registers of Register STATE.
Bit Mask for Sub-Register STATE.STATE
| #define STATE_STATE_SHIFT 0 |
Bit Offset for Sub-Register STATE.STATE.
| #define TXCI_DCOI_MASK 0x3F |
Sub-registers of Register TXCI.
Bit Mask for Sub-Register TXCI.DCOI
| #define TXCI_DCOI_SHIFT 0 |
Bit Offset for Sub-Register TXCI.DCOI.
| #define TXCQ_DCOQ_MASK 0x3F |
Sub-registers of Register TXCQ.
Bit Mask for Sub-Register TXCQ.DCOQ
| #define TXCQ_DCOQ_SHIFT 0 |
Bit Offset for Sub-Register TXCQ.DCOQ.
| #define TXCUTC_LPFCUT_MASK 0x0F |
Sub-registers of Register TXCUTC.
Bit Mask for Sub-Register TXCUTC.LPFCUT
| #define TXCUTC_LPFCUT_SHIFT 0 |
Bit Offset for Sub-Register TXCUTC.LPFCUT.
Referenced by ofdm_rfcfg(), and oqpsk_rfcfg().
| #define TXCUTC_PARAMP_MASK 0xC0 |
Bit Mask for Sub-Register TXCUTC.PARAMP.
| #define TXCUTC_PARAMP_SHIFT 6 |
Bit Offset for Sub-Register TXCUTC.PARAMP.
Referenced by ofdm_rfcfg(), and oqpsk_rfcfg().
| #define TXDACI_ENTXDACID_MASK 0x80 |
Bit Mask for Sub-Register TXDACI.ENTXDACID.
| #define TXDACI_ENTXDACID_SHIFT 7 |
Bit Offset for Sub-Register TXDACI.ENTXDACID.
| #define TXDACI_TXDACID_MASK 0x7F |
Sub-registers of Register TXDACI.
Bit Mask for Sub-Register TXDACI.TXDACID
| #define TXDACI_TXDACID_SHIFT 0 |
Bit Offset for Sub-Register TXDACI.TXDACID.
| #define TXDACQ_ENTXDACQD_MASK 0x80 |
Bit Mask for Sub-Register TXDACQ.ENTXDACQD.
| #define TXDACQ_ENTXDACQD_SHIFT 7 |
Bit Offset for Sub-Register TXDACQ.ENTXDACQD.
| #define TXDACQ_TXDACQD_MASK 0x7F |
Sub-registers of Register TXDACQ.
Bit Mask for Sub-Register TXDACQ.TXDACQD
| #define TXDACQ_TXDACQD_SHIFT 0 |
Bit Offset for Sub-Register TXDACQ.TXDACQD.
| #define TXDFE_DM_MASK 0x10 |
Bit Mask for Sub-Register TXDFE.DM.
| #define TXDFE_DM_SHIFT 4 |
Bit Offset for Sub-Register TXDFE.DM.
Referenced by fsk_rfcfg(), and oqpsk_rfcfg().
| #define TXDFE_RCUT_MASK 0xE0 |
Bit Mask for Sub-Register TXDFE.RCUT.
| #define TXDFE_RCUT_SHIFT 5 |
Bit Offset for Sub-Register TXDFE.RCUT.
Referenced by ofdm_rfcfg(), and oqpsk_rfcfg().
| #define TXDFE_SR_MASK 0x0F |
Sub-registers of Register TXDFE.
Bit Mask for Sub-Register TXDFE.SR
| #define TXDFE_SR_SHIFT 0 |
Bit Offset for Sub-Register TXDFE.SR.
Referenced by ofdm_rfcfg(), and oqpsk_rfcfg().
| #define TXFLH_TXFLH_MASK 0x07 |
Sub-registers of Register TXFLH.
Bit Mask for Sub-Register TXFLH.TXFLH
| #define TXFLH_TXFLH_SHIFT 0 |
Bit Offset for Sub-Register TXFLH.TXFLH.
| #define TXFLL_TXFLL_MASK 0xFF |
Sub-registers of Register TXFLL.
Bit Mask for Sub-Register TXFLL.TXFLL
| #define TXFLL_TXFLL_SHIFT 0 |
Bit Offset for Sub-Register TXFLL.TXFLL.
| #define VN_VN_MASK 0xFF |
Sub-registers of Register VN.
Bit Mask for Sub-Register VN.VN
| #define VN_VN_SHIFT 0 |
Bit Offset for Sub-Register VN.VN.
| #define XOC_FS_MASK 0x10 |
Bit Mask for Sub-Register XOC.FS.
| #define XOC_FS_SHIFT 4 |
Bit Offset for Sub-Register XOC.FS.
| #define XOC_TRIM_MASK 0x0F |
Sub-registers of Register XOC.
Bit Mask for Sub-Register XOC.TRIM
| #define XOC_TRIM_SHIFT 0 |
Bit Offset for Sub-Register XOC.TRIM.
| typedef enum bb_irq_tag bb_irq_t |
Enumeration for BB IRQs.
| typedef enum rf_cmd_state_tag rf_cmd_state_t |
Enumerations.
Enumeration for RF commands and states used for trx command and state registers
| typedef enum rf_cmd_status_tag rf_cmd_status_t |
Enumeration for RF commands and states used for trx command and state registers.
| typedef enum rf_irq_tag rf_irq_t |
Enumeration for RF IRQs used for IRQS and IRQM registers.
| enum bb_irq_tag |
Enumeration for BB IRQs.
| enum rf_cmd_state_tag |
Enumerations.
Enumeration for RF commands and states used for trx command and state registers
| enum rf_cmd_status_tag |
Enumeration for RF commands and states used for trx command and state registers.
| enum rf_irq_tag |
Enumeration for RF IRQs used for IRQS and IRQM registers.
1.8.5