Configurations for the WILC3000 Serial Bridge Application.
Copyright (c) 2018 Microchip Technology Inc. and its subsidiaries.
Macros | |
#define | ALL_INTERRUPT_MASK 0xffffffff |
All interrupt mask. More... | |
#define | STATE_READ 0 |
USART is reading. More... | |
#define | STATE_WRITE 1 |
USART is writing. More... | |
Functions | |
void | bt_configure_usart (uint32_t baudrate) |
Configure USART in normal (serial rs232) mode, asynchronous, 8 bits, 1 stop bit, no parity, 115200 bauds and enable its transmitter and receiver. More... | |
void | bt_usart_receive (uint8_t *buffer, uint32_t size) |
void | bt_usart_stream_write_buffer (uint8_t *data, uint32_t size) |
void | bt_usart_transfer (uint8_t *buffer, uint32_t size) |
void | USART1_Handler (void) |
USART IRQ handler. More... | |
static void | usart_clear (void) |
Variables | |
static uint8_t | bt_usart_buffer [USART_BUFFER_MAX] |
int8_t | g_c_recv_buff [USART_BUFFER_MAX] = { 0 } |
Buffer for receiving. More... | |
Pdc * | g_p_pdc |
Pointer to PDC register base. More... | |
pdc_packet_t | g_st_packet |
PDC data packet. More... | |
uint8_t | g_uc_state = STATE_WRITE |
State of reading or writing. More... | |
volatile uint32_t | g_ul_sent_done = false |
Reception is done. More... | |
uint8_t | hci_recv_buffer [13] |
uint8_t | read_buffer [12] |
uint8_t * | tx_buffer = NULL |
uint32_t | tx_size = 0 |
static uint32_t | usart_recv_size = 0 |
#define ALL_INTERRUPT_MASK 0xffffffff |
All interrupt mask.
Referenced by bt_configure_usart().
#define STATE_READ 0 |
USART is reading.
Referenced by bt_usart_receive(), and USART1_Handler().
#define STATE_WRITE 1 |
USART is writing.
Referenced by bt_usart_transfer(), and USART1_Handler().
void bt_configure_usart | ( | uint32_t | baudrate | ) |
Configure USART in normal (serial rs232) mode, asynchronous, 8 bits, 1 stop bit, no parity, 115200 bauds and enable its transmitter and receiver.
References ALL_INTERRUPT_MASK, uart_rs232_options::baudrate, BT_CONF_UART, g_p_pdc, gpio_configure_group, pdc_enable_transfer(), sysclk_enable_peripheral_clock(), usart_disable_interrupt(), usart_enable_rx(), usart_enable_tx(), usart_get_pdc_base(), and usart_serial_init().
Referenced by main().
void bt_usart_receive | ( | uint8_t * | buffer, |
uint32_t | size | ||
) |
References BT_CONF_UART, g_p_pdc, g_uc_state, NULL, pdc_rx_init(), STATE_READ, pdc_packet::ul_addr, pdc_packet::ul_size, usart_clear(), and usart_enable_interrupt().
Referenced by bt_hci_reset_handler(), bt_hci_start_rx_handler(), bt_hci_start_tx_handler(), bt_hci_stop_txrx_handler(), serial_bridge(), usart_read_block_handler(), and usart_read_reg_with_ret_handler().
void bt_usart_stream_write_buffer | ( | uint8_t * | data, |
uint32_t | size | ||
) |
void bt_usart_transfer | ( | uint8_t * | buffer, |
uint32_t | size | ||
) |
void USART1_Handler | ( | void | ) |
USART IRQ handler.
Interrupt handler for USART. After reception is done, set g_ul_recv_done to true, and if transmission is done, set g_ul_sent_done to true.
References BT_CONF_UART, g_uc_state, g_ul_sent_done, hci_recv_buffer, STATE_READ, STATE_WRITE, pdc_packet::ul_size, usart_disable_interrupt(), usart_get_status(), and usart_stream_write_buffer().
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static |
References BT_CONF_UART, g_p_pdc, NULL, pdc_rx_init(), pdc_tx_init(), pdc_packet::ul_addr, pdc_packet::ul_size, usart_enable_rx(), usart_enable_tx(), usart_reset_rx(), and usart_reset_tx().
Referenced by bt_usart_receive(), and bt_usart_transfer().
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static |
int8_t g_c_recv_buff[USART_BUFFER_MAX] = { 0 } |
Buffer for receiving.
Pdc* g_p_pdc |
Pointer to PDC register base.
pdc_packet_t g_st_packet |
PDC data packet.
uint8_t g_uc_state = STATE_WRITE |
State of reading or writing.
volatile uint32_t g_ul_sent_done = false |
Reception is done.
Sending is done.
uint8_t hci_recv_buffer[13] |
Referenced by USART1_Handler().
uint8_t read_buffer[12] |
uint8_t* tx_buffer = NULL |
uint32_t tx_size = 0 |
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static |