This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration and management of the device's Reset Controller functionality.
The Reset Controller manages all Resets of the System including; external devices (via the NRST pin), Processor Reset and Peripheral Reset. It also provides the status of the last reset source.
The following peripheral is used by this module:
Devices from the following series can use this module:
The outline of this documentation is as follows:
There are no prerequisites for this module.
The Reset Controller contains an NRST Manager and a Reset State Manager. It runs at Slow Clock (SCLK) and generates the following:
These reset signals are asserted by the Reset Controller acting on external events or as the result of an action performed by software. The Reset State Manager controls the operation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required.
To control an external device reset the NRST Manager shapes the NRST assertion period using a programmable timer. While asserted, after power-up, NRST is an output and driven low. When the programmable time period has elapsed the pin behaves as an input and all the system is held in reset if NRST is tied to GND by an external signal.
The NRST Manager samples the NRST pin at Slow Clock (SCLK) speed and drives this pin low when required by the Reset State Manager. When the line is detected as being low a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed not to trigger a reset when NRST is asserted.
The Reset controller can also be programmed to generate an interrupt instead of generating a reset.
The NRST Manager can assert NRST for a programmable time period of between 60µs and 2s (approximately). This allows the Reset Controller to shape the NRST pin level and thus to guarantee that the NRST line is low for a time that is compliant with any external devices also connected to the system reset.
The Reset State Manager handles the different reset sources and generates the internal reset signals.
A general reset occurs when either a Power-on-reset is detected or the Supply Controller detects a Brownout or Voltage regulation loss.
A Backup Reset occurs when the chip returns from Backup Mode. The core_backup_reset signal is asserted by the Supply Controller when a Backup Reset occurs.
If User Reset is enabled then the state is entered when a low level is detected on the NRST pin. When User Reset is entered both the Processor Reset and the Peripheral Reset are asserted.
The User Reset state is left when NRST rises and the processor clock is re-enabled as soon as NRST is confirmed high.
The Reset Controller allows software to assert the the following reset signals:
The Watchdog Reset is entered when a watchdog fault occurs.
The Reset State Manager manages the following priorities between the different reset sources, given in descending order:
Particular cases are listed below:
System designs using any external devices that require a software controllable reset signal assertion longer than two seconds should use a dedicated I/O output of the microcontroller.
For extra information, see Extra Information for Reset Controller Driver. This includes:
For a list of examples related to this driver, see Examples for Reset Controller Driver.
Macros | |
#define | RSTC_BACKUP_RESET (1 << RSTC_SR_RSTTYP_Pos) |
#define | RSTC_CPMR_KEY_PASSWD RSTC_CPMR_CPKEY(0x5AU) |
#define | RSTC_GENERAL_RESET (0 << RSTC_SR_RSTTYP_Pos) |
#define | RSTC_NRST_HIGH (HIGH << 16) |
#define | RSTC_NRST_LOW (LOW << 16) |
#define | RSTC_SOFTWARE_RESET (3 << RSTC_SR_RSTTYP_Pos) |
#define | RSTC_USER_RESET (4 << RSTC_SR_RSTTYP_Pos) |
#define | RSTC_WATCHDOG_RESET (2 << RSTC_SR_RSTTYP_Pos) |
Functions | |
static void | rstc_assert_reset_of_coprocessor (Rstc *p_rstc, const uint32_t reset) |
Assert the reset of the Co-processor. More... | |
static void | rstc_deassert_reset_of_coprocessor (Rstc *p_rstc, const uint32_t reset) |
Deassert the reset of the Co-processor. More... | |
void | rstc_disable_user_reset (Rstc *p_rstc) |
Disable User Reset. More... | |
void | rstc_disable_user_reset_interrupt (Rstc *p_rstc) |
Disable the User Reset interrupt. More... | |
void | rstc_enable_user_reset (Rstc *p_rstc) |
Enable User Reset. More... | |
void | rstc_enable_user_reset_interrupt (Rstc *p_rstc) |
Enable the User Reset interrupt. More... | |
uint32_t | rstc_get_reset_cause (Rstc *p_rstc) |
Get the reset cause. More... | |
uint32_t | rstc_get_status (Rstc *p_rstc) |
Get the RSTC status. More... | |
void | rstc_reset_extern (Rstc *p_rstc) |
Asserts the NRST pin for external resets. More... | |
void | rstc_set_external_reset (Rstc *p_rstc, const uint32_t ul_length) |
Set the external reset length. More... | |
void | rstc_start_software_reset (Rstc *p_rstc) |
Perform a Software Reset. More... | |
#define RSTC_BACKUP_RESET (1 << RSTC_SR_RSTTYP_Pos) |
Referenced by display_reset_reason().
#define RSTC_CPMR_KEY_PASSWD RSTC_CPMR_CPKEY(0x5AU) |
Referenced by rstc_assert_reset_of_coprocessor(), and rstc_deassert_reset_of_coprocessor().
#define RSTC_GENERAL_RESET (0 << RSTC_SR_RSTTYP_Pos) |
Referenced by display_reset_reason().
#define RSTC_NRST_HIGH (HIGH << 16) |
#define RSTC_NRST_LOW (LOW << 16) |
#define RSTC_SOFTWARE_RESET (3 << RSTC_SR_RSTTYP_Pos) |
Referenced by display_reset_reason().
#define RSTC_USER_RESET (4 << RSTC_SR_RSTTYP_Pos) |
Referenced by display_reset_reason().
#define RSTC_WATCHDOG_RESET (2 << RSTC_SR_RSTTYP_Pos) |
Referenced by display_reset_reason().
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inlinestatic |
Assert the reset of the Co-processor.
[in,out] | p_rstc | Module hardware register base address pointer |
[in] | reset | The reset to be asserted as a bitmask, which could be RSTC_CPMR_CPEREN (peripheral reset) and/or RSTC_CPMR_CPROCEN (core reset). |
References Assert, and RSTC_CPMR_KEY_PASSWD.
|
inlinestatic |
Deassert the reset of the Co-processor.
[in,out] | p_rstc | Module hardware register base address pointer |
[in] | reset | The reset to be deasserted as a bitmask, which could be RSTC_CPMR_CPEREN (peripheral reset) and/or RSTC_CPMR_CPROCEN (core reset). |
References RSTC_CPMR_KEY_PASSWD.
void rstc_disable_user_reset | ( | Rstc * | p_rstc | ) |
void rstc_disable_user_reset_interrupt | ( | Rstc * | p_rstc | ) |
void rstc_enable_user_reset | ( | Rstc * | p_rstc | ) |
void rstc_enable_user_reset_interrupt | ( | Rstc * | p_rstc | ) |
uint32_t rstc_get_reset_cause | ( | Rstc * | p_rstc | ) |
Get the reset cause.
[in] | p_rstc | Module hardware register base address pointer |
uint32_t rstc_get_status | ( | Rstc * | p_rstc | ) |
Get the RSTC status.
[in] | p_rstc | Module hardware register base address pointer |
Referenced by display_reset_reason().
void rstc_reset_extern | ( | Rstc * | p_rstc | ) |
void rstc_set_external_reset | ( | Rstc * | p_rstc, |
const uint32_t | ul_length | ||
) |