phy.h File Reference

#include "miwi_config.h"
#include "miwi_config_p2p.h"
#include "miwi_api.h"

Data Structures
struct	_PhyTxFrame_t
struct	PHY_DataInd_t
struct	PHY_DataReq_t
union	RADIO_STATUS
struct	RxBuffer_t

Macros
#define	AACK_ACK_TIME   2
#define	AACK_FLTR_RES_FT   5
#define	AACK_PROM_MODE   1
#define	AACK_SPC_EN   0
#define	AACK_UPLD_RES_FT   4
#define	AMI   5
#define	ANT_CTRL   0
#define	ANT_DIV_EN   3
#define	ANT_DIV_REG   0x0d
#define	ANT_EXT_SW_EN   2
#define	ANT_SEL   7
#define	ARET_TX_TS_EN   7
#define	BANK_SIZE   4
#define	BAT_LOW   7
#define	BATMON_REG   0x11
#define	CCA_ED_DONE   4
#define	CCA_THRES_REG   0x09
#define	CSMA_BE_REG   0x2f
#define	CSMA_SEED_0_REG   0x2d
#define	CSMA_SEED_1_REG   0x2e
#define	FCF_FRAMETYPE_MASK   (0x07)
	Defines a mask for the frame type. More...
#define	FCF_GET_FRAMETYPE(x)   ((x) & FCF_FRAMETYPE_MASK)
	Macro to get the frame type. More...
#define	FTN_CTRL_REG   0x18
#define	IEEE_ADDR_0_REG   0x24
#define	IEEE_ADDR_1_REG   0x25
#define	IEEE_ADDR_2_REG   0x26
#define	IEEE_ADDR_3_REG   0x27
#define	IEEE_ADDR_4_REG   0x28
#define	IEEE_ADDR_5_REG   0x29
#define	IEEE_ADDR_6_REG   0x2a
#define	IEEE_ADDR_7_REG   0x2b
#define	IRQ_2_EXT_EN   6
#define	IRQ_MASK_MODE   1
#define	IRQ_MASK_REG   0x0e
#define	IRQ_POLARITY   0
#define	IRQ_STATUS_REG   0x0f
#define	KEY_SEQUENCE_NUMBER   0x00
#define	MAN_ID_0_REG   0x1e
#define	MAN_ID_1_REG   0x1f
#define	MAX_PSDU   127
#define	OQPSK_DATA_RATE   0
#define	OQPSK_SCRAM_EN   5
#define	PA_EXT_EN   7
#define	PAN_ID_0_REG   0x22
#define	PAN_ID_1_REG   0x23
#define	PART_NUM_REG   0x1c
#define	PHY_CC_CCA_REG   0x08
#define	PHY_CC_CCA_REG   0x08
#define	PHY_ED_LEVEL_REG   0x07
#define	PHY_PMU_VALUE_REG   0x3b
#define	PHY_RSSI_REG   0x06
#define	PHY_STATUS_CHANNEL_ACCESS_FAILURE   2
#define	PHY_STATUS_ERROR   1
#define	PHY_STATUS_NO_ACK   3
#define	PHY_STATUS_SUCCESS   0
#define	PHY_TX_PWR_REG   0x05
#define	PHY_TX_TIME_REG   0x3b
#define	PLL_CF_REG   0x1a
#define	PLL_DCU_REG   0x1b
#define	PLL_LOCK   0
#define	PLL_UNLOCK   1
#define	PROTOCOL_HEADER_SIZE   0
#define	PROTOCOL_HEADER_SIZE   32
#define	RND_VALUE   5
#define	RSSI   0
#define	RX_BL_CTRL   4
#define	RX_CRC_VALID   7
#define	RX_CTRL_REG   0x0a
#define	RX_PACKET_SIZE   (RX_BUFFER_SIZE+PROTOCOL_HEADER_SIZE+MY_ADDRESS_LENGTH+MY_ADDRESS_LENGTH+12)
#define	RX_SAFE_MODE   7
#define	RX_START   2
#define	RX_SYN_REG   0x15
#define	SEC_LEVEL_CBC_MAC_128   5
#define	SEC_LEVEL_CBC_MAC_128   5
#define	SEC_LEVEL_CBC_MAC_32   7
#define	SEC_LEVEL_CBC_MAC_32   7
#define	SEC_LEVEL_CBC_MAC_64   6
#define	SEC_LEVEL_CBC_MAC_64   6
#define	SEC_LEVEL_CCM_128   2
#define	SEC_LEVEL_CCM_128   2
#define	SEC_LEVEL_CCM_32   4
#define	SEC_LEVEL_CCM_32   4
#define	SEC_LEVEL_CCM_64   3
#define	SEC_LEVEL_CCM_64   3
#define	SEC_LEVEL_CTR   1
#define	SEC_LEVEL_CTR   1
#define	SECURITY_KEY_00   0x00
#define	SECURITY_KEY_01   0x01
#define	SECURITY_KEY_02   0x02
#define	SECURITY_KEY_03   0x03
#define	SECURITY_KEY_04   0x04
#define	SECURITY_KEY_05   0x05
#define	SECURITY_KEY_06   0x06
#define	SECURITY_KEY_07   0x07
#define	SECURITY_KEY_08   0x08
#define	SECURITY_KEY_09   0x09
#define	SECURITY_KEY_10   0x0a
#define	SECURITY_KEY_11   0x0b
#define	SECURITY_KEY_12   0x0c
#define	SECURITY_KEY_13   0x0d
#define	SECURITY_KEY_14   0x0e
#define	SECURITY_KEY_15   0x0f
#define	SECURITY_LEVEL   SEC_LEVEL_CCM_32
#define	SFD_VALUE_REG   0x0b
#define	SHORT_ADDR_0_REG   0x20
#define	SHORT_ADDR_1_REG   0x21
#define	SPI_CMD_MODE   2
#define	TRAC_STATUS   5
#define	TRAC_STATUS_CHANNEL_ACCESS_FAILURE   3
#define	TRAC_STATUS_INVALID   7
#define	TRAC_STATUS_NO_ACK   5
#define	TRAC_STATUS_SUCCESS   0
#define	TRAC_STATUS_SUCCESS_DATA_PENDING   1
#define	TRAC_STATUS_SUCCESS_WAIT_FOR_ACK   2
#define	TRX_CMD   0
#define	TRX_CMD_FORCE_PLL_ON   4
#define	TRX_CMD_FORCE_TRX_OFF   3
#define	TRX_CMD_NOP   0
#define	TRX_CMD_PLL_ON   9
#define	TRX_CMD_RX_AACK_ON   22
#define	TRX_CMD_RX_ON   6
#define	TRX_CMD_TRX_OFF   8
#define	TRX_CMD_TX_ARET_ON   25
#define	TRX_CMD_TX_START   2
#define	TRX_CTRL_0_REG   0x03
#define	TRX_CTRL_1_REG   0x04
#define	TRX_CTRL_2_REG   0x0c
#define	TRX_END   3
#define	TRX_RPC_REG   0x16
#define	TRX_STATE_REG   0x02
#define	TRX_STATUS_BUSY_RX   1
#define	TRX_STATUS_BUSY_RX_AACK   17
#define	TRX_STATUS_BUSY_RX_AACK_NOCLK   30
#define	TRX_STATUS_BUSY_TX   2
#define	TRX_STATUS_BUSY_TX_ARET   18
#define	TRX_STATUS_MASK   0x1f
#define	TRX_STATUS_P_ON   0
#define	TRX_STATUS_PLL_ON   9
#define	TRX_STATUS_REG   0x01
#define	TRX_STATUS_RX_AACK_ON   22
#define	TRX_STATUS_RX_AACK_ON_NOCLK   29
#define	TRX_STATUS_RX_ON   6
#define	TRX_STATUS_RX_ON_NOCLK   28
#define	TRX_STATUS_SLEEP   15
#define	TRX_STATUS_STATE_TRANSITION   31
#define	TRX_STATUS_TRX_OFF   8
#define	TRX_STATUS_TRX_STATUS_MASK   0x1f
#define	TRX_STATUS_TX_ARET_ON   25
#define	TRX_UR   6
#define	TST_AGC_REG   0x3c
#define	TST_CTRL_DIGI_REG   0x36
#define	TST_SDM_REG   0x3d
#define	TX_AUTO_CRC_ON   5
#define	VERSION_NUM_REG   0x1d
#define	VREG_CTRL_REG   0x10
#define	XAH_CTRL_0_REG   0x2c
#define	XAH_CTRL_1_REG   0x17
#define	XAH_CTRL_2_REG   0x19
#define	XOSC_CTRL_REG   0x12

Typedefs
typedef void(*	PHY_DataConfCb_t )(uint8_t status)
typedef struct PHY_DataInd_t	PHY_DataInd_t
typedef struct PHY_DataReq_t	PHY_DataReq_t
typedef void(*	PHY_ReservedFrameIndCallback_t )(PHY_DataInd_t *ind)
typedef struct _PhyTxFrame_t	PhyTxFrame_t

Functions
void	CONSOLE_PrintHex (uint8_t toPrint)
void	CONSOLE_PutString (char *str)
bool	DataDecrypt (uint8_t *Payload, uint8_t *PayloadLen, uint8_t *SourceIEEEAddress, API_UINT32_UNION FrameCounter, uint8_t FrameControl)
bool	DataEncrypt (uint8_t *, uint8_t *, API_UINT32_UNION, uint8_t)
void	mic_generator (uint8_t *Payloadinfo, uint8_t, uint8_t frame_control, API_UINT32_UNION FrameCounter, uint8_t *Address)
void	PHY_DataConf (uint8_t status)
void	PHY_DataReq (PHY_DataReq_t *phyDataReq)
void	PHY_DecryptReq (uint8_t *text, uint8_t *key)
uint8_t	PHY_EdReq (void)
void	PHY_EncryptReq (uint8_t *text, uint8_t *key)
void	PHY_EncryptReqCBC (uint8_t *text, uint8_t *key)
void	PHY_Init (void)
uint16_t	PHY_RandomReq (void)
void	PHY_SetChannel (uint8_t channel)
void	PHY_SetIEEEAddr (uint8_t *ieee_addr)
void	PHY_SetPanId (uint16_t panId)
void	PHY_SetRxState (bool rx)
void	PHY_SetShortAddr (uint16_t addr)
void	PHY_SetTxPower (uint8_t txPower)
void	PHY_Sleep (void)
void	PHY_TaskHandler (void)
void	PHY_TxHandler (void)
void	PHY_Wakeup (void)
void	print_rx_message (void)
bool	validate_mic (void)

Variables
RxBuffer_t	RxBuffer []

#define AACK_ACK_TIME   2

#define AACK_FLTR_RES_FT   5

#define AACK_PROM_MODE   1

#define AACK_SPC_EN   0

#define AACK_UPLD_RES_FT   4

#define AMI   5

#define ANT_CTRL   0

Referenced by tal_get_curr_trx_config().

#define ANT_DIV_EN   3

Referenced by PHY_Init().

#define ANT_DIV_REG   0x0d

Referenced by PHY_Init(), PHY_Sleep(), and PHY_Wakeup().

#define ANT_EXT_SW_EN   2

Referenced by PHY_Init(), PHY_Sleep(), and PHY_Wakeup().

#define ANT_SEL   7

#define ARET_TX_TS_EN   7

#define BANK_SIZE   4

Referenced by MiMAC_DiscardPacket(), MiMAC_Init(), MiMAC_ReceivedPacket(), and PHY_TaskHandler().

#define BAT_LOW   7

#define BATMON_REG   0x11

#define CCA_ED_DONE   4

Referenced by PHY_EdReq().

#define CCA_THRES_REG   0x09

#define CSMA_BE_REG   0x2f

#define CSMA_SEED_0_REG   0x2d

Referenced by PHY_SetShortAddr().

#define CSMA_SEED_1_REG   0x2e

#define FCF_FRAMETYPE_MASK   (0x07)

Defines a mask for the frame type.

(Table 65 IEEE 802.15.4 Specification)

Referenced by process_incoming_frame().

#define FCF_GET_FRAMETYPE

(

x

)

((x) & FCF_FRAMETYPE_MASK)

Macro to get the frame type.

Referenced by parse_mpdu().

#define FTN_CTRL_REG   0x18

#define IEEE_ADDR_0_REG   0x24

Referenced by PHY_SetIEEEAddr().

#define IEEE_ADDR_1_REG   0x25

#define IEEE_ADDR_2_REG   0x26

#define IEEE_ADDR_3_REG   0x27

#define IEEE_ADDR_4_REG   0x28

#define IEEE_ADDR_5_REG   0x29

#define IEEE_ADDR_6_REG   0x2a

#define IEEE_ADDR_7_REG   0x2b

#define IRQ_2_EXT_EN   6

#define IRQ_MASK_MODE   1

Referenced by PHY_Init().

#define IRQ_MASK_REG   0x0e

Referenced by PHY_Init().

#define IRQ_POLARITY   0

#define IRQ_STATUS_REG   0x0f

Referenced by PHY_EdReq(), PHY_TaskHandler(), PHY_TxHandler(), and phySetRxState().

#define KEY_SEQUENCE_NUMBER   0x00

#define MAN_ID_0_REG   0x1e

#define MAN_ID_1_REG   0x1f

#define MAX_PSDU   127

Referenced by PHY_TaskHandler(), and PHY_TxHandler().

#define OQPSK_DATA_RATE   0

#define OQPSK_SCRAM_EN   5

Referenced by PHY_Init().

#define PA_EXT_EN   7

#define PAN_ID_0_REG   0x22

Referenced by PHY_SetPanId().

#define PAN_ID_1_REG   0x23

Referenced by PHY_SetPanId().

#define PART_NUM_REG   0x1c

#define PHY_CC_CCA_REG   0x08

Referenced by PHY_SetChannel(), and phySetChannel().

#define PHY_CC_CCA_REG   0x08

#define PHY_ED_LEVEL_REG   0x07

Referenced by PHY_EdReq(), and PHY_TaskHandler().

#define PHY_PMU_VALUE_REG   0x3b

#define PHY_RSSI_REG   0x06

Referenced by PHY_RandomReq().

#define PHY_STATUS_CHANNEL_ACCESS_FAILURE   2

Referenced by PHY_TaskHandler(), and PHY_TxHandler().

#define PHY_STATUS_ERROR   1

Referenced by PHY_DataReq(), PHY_TaskHandler(), and PHY_TxHandler().

#define PHY_STATUS_NO_ACK   3

Referenced by PHY_TaskHandler(), and PHY_TxHandler().

#define PHY_STATUS_SUCCESS   0

Referenced by PHY_TaskHandler(), and PHY_TxHandler().

#define PHY_TX_PWR_REG   0x05

Referenced by PHY_Init(), and PHY_SetTxPower().

#define PHY_TX_TIME_REG   0x3b

#define PLL_CF_REG   0x1a

#define PLL_DCU_REG   0x1b

#define PLL_LOCK   0

#define PLL_UNLOCK   1

#define PROTOCOL_HEADER_SIZE   0

#define PROTOCOL_HEADER_SIZE   32

#define RND_VALUE   5

Referenced by PHY_RandomReq().

#define RSSI   0

#define RX_BL_CTRL   4

#define RX_CRC_VALID   7

#define RX_CTRL_REG   0x0a

#define RX_PACKET_SIZE   (RX_BUFFER_SIZE+PROTOCOL_HEADER_SIZE+MY_ADDRESS_LENGTH+MY_ADDRESS_LENGTH+12)

Referenced by PHY_TaskHandler().

#define RX_SAFE_MODE   7

Referenced by PHY_Init().

#define RX_START   2

#define RX_SYN_REG   0x15

Referenced by PHY_EdReq(), and PHY_RandomReq().

#define SEC_LEVEL_CBC_MAC_128   5

#define SEC_LEVEL_CBC_MAC_128   5

#define SEC_LEVEL_CBC_MAC_32   7

#define SEC_LEVEL_CBC_MAC_32   7

#define SEC_LEVEL_CBC_MAC_64   6

#define SEC_LEVEL_CBC_MAC_64   6

#define SEC_LEVEL_CCM_128   2

#define SEC_LEVEL_CCM_128   2

#define SEC_LEVEL_CCM_32   4

#define SEC_LEVEL_CCM_32   4

#define SEC_LEVEL_CCM_64   3

#define SEC_LEVEL_CCM_64   3

#define SEC_LEVEL_CTR   1

#define SEC_LEVEL_CTR   1

#define SECURITY_KEY_00   0x00

#define SECURITY_KEY_01   0x01

#define SECURITY_KEY_02   0x02

#define SECURITY_KEY_03   0x03

#define SECURITY_KEY_04   0x04

#define SECURITY_KEY_05   0x05

#define SECURITY_KEY_06   0x06

#define SECURITY_KEY_07   0x07

#define SECURITY_KEY_08   0x08

#define SECURITY_KEY_09   0x09

#define SECURITY_KEY_10   0x0a

#define SECURITY_KEY_11   0x0b

#define SECURITY_KEY_12   0x0c

#define SECURITY_KEY_13   0x0d

#define SECURITY_KEY_14   0x0e

#define SECURITY_KEY_15   0x0f

#define SECURITY_LEVEL   SEC_LEVEL_CCM_32

#define SFD_VALUE_REG   0x0b

#define SHORT_ADDR_0_REG   0x20

Referenced by PHY_SetShortAddr().

#define SHORT_ADDR_1_REG   0x21

Referenced by PHY_SetShortAddr().

#define SPI_CMD_MODE   2

Referenced by PHY_Init().

#define TRAC_STATUS   5

Referenced by PHY_TaskHandler(), and PHY_TxHandler().

#define TRAC_STATUS_CHANNEL_ACCESS_FAILURE   3

Referenced by PHY_TaskHandler(), and PHY_TxHandler().

#define TRAC_STATUS_INVALID   7

#define TRAC_STATUS_NO_ACK   5

Referenced by PHY_TaskHandler(), and PHY_TxHandler().

#define TRAC_STATUS_SUCCESS   0

Referenced by PHY_TaskHandler(), and PHY_TxHandler().

#define TRAC_STATUS_SUCCESS_DATA_PENDING   1

#define TRAC_STATUS_SUCCESS_WAIT_FOR_ACK   2

#define TRX_CMD   0

#define TRX_CMD_FORCE_PLL_ON   4

#define TRX_CMD_FORCE_TRX_OFF   3

Referenced by phyTrxSetState().

#define TRX_CMD_NOP   0

#define TRX_CMD_PLL_ON   9

Referenced by PHY_EdReq().

#define TRX_CMD_RX_AACK_ON   22

Referenced by phySetRxState().

#define TRX_CMD_RX_ON   6

Referenced by PHY_EdReq(), and PHY_RandomReq().

#define TRX_CMD_TRX_OFF   8

Referenced by PHY_Init(), PHY_Sleep(), PHY_TaskHandler(), and phySetRxState().

#define TRX_CMD_TX_ARET_ON   25

Referenced by PHY_TxHandler().

#define TRX_CMD_TX_START   2

#define TRX_CTRL_0_REG   0x03

#define TRX_CTRL_1_REG   0x04

Referenced by PHY_Init().

#define TRX_CTRL_2_REG   0x0c

Referenced by PHY_Init().

#define TRX_END   3

Referenced by PHY_Init(), PHY_TaskHandler(), and PHY_TxHandler().

#define TRX_RPC_REG   0x16

Referenced by PHY_Init().

#define TRX_STATE_REG   0x02

Referenced by PHY_Init(), PHY_TaskHandler(), PHY_TxHandler(), and phyTrxSetState().

#define TRX_STATUS_BUSY_RX   1

#define TRX_STATUS_BUSY_RX_AACK   17

#define TRX_STATUS_BUSY_RX_AACK_NOCLK   30

#define TRX_STATUS_BUSY_TX   2

#define TRX_STATUS_BUSY_TX_ARET   18

#define TRX_STATUS_MASK   0x1f

Referenced by PHY_Init(), phyTrxSetState(), and phyWaitState().

#define TRX_STATUS_P_ON   0

#define TRX_STATUS_PLL_ON   9

#define TRX_STATUS_REG   0x01

Referenced by PHY_Init(), phyTrxSetState(), and phyWaitState().

#define TRX_STATUS_RX_AACK_ON   22

Referenced by PHY_TaskHandler().

#define TRX_STATUS_RX_AACK_ON_NOCLK   29

#define TRX_STATUS_RX_ON   6

#define TRX_STATUS_RX_ON_NOCLK   28

#define TRX_STATUS_SLEEP   15

#define TRX_STATUS_STATE_TRANSITION   31

#define TRX_STATUS_TRX_OFF   8

Referenced by PHY_Init(), and phyTrxSetState().

#define TRX_STATUS_TRX_STATUS_MASK   0x1f

#define TRX_STATUS_TX_ARET_ON   25

#define TRX_UR   6

#define TST_AGC_REG   0x3c

#define TST_CTRL_DIGI_REG   0x36

#define TST_SDM_REG   0x3d

#define TX_AUTO_CRC_ON   5

Referenced by PHY_Init().

#define VERSION_NUM_REG   0x1d

#define VREG_CTRL_REG   0x10

#define XAH_CTRL_0_REG   0x2c

#define XAH_CTRL_1_REG   0x17

#define XAH_CTRL_2_REG   0x19

#define XOSC_CTRL_REG   0x12

typedef void(* PHY_DataConfCb_t)(uint8_t status)

typedef struct PHY_DataInd_t PHY_DataInd_t

typedef struct PHY_DataReq_t PHY_DataReq_t

typedef void(* PHY_ReservedFrameIndCallback_t)(PHY_DataInd_t *ind)

typedef struct _PhyTxFrame_t PhyTxFrame_t

void CONSOLE_PrintHex

(

uint8_t

toPrint

)

void CONSOLE_PutString

(

char *

str

)

bool DataDecrypt	(	uint8_t *	Payload,
		uint8_t *	PayloadLen,
		uint8_t *	SourceIEEEAddress,
		API_UINT32_UNION	FrameCounter,
		uint8_t	FrameControl
	)

Referenced by MiMAC_ReceivedPacket().

bool DataEncrypt	(	uint8_t *	,
		uint8_t *	,
		API_UINT32_UNION	,
		uint8_t
	)

Referenced by MiMAC_SendPacket().

void mic_generator	(	uint8_t *	Payloadinfo,
		uint8_t	,
		uint8_t	frame_control,
		API_UINT32_UNION	FrameCounter,
		uint8_t *	Address
	)

void PHY_DataConf

(

uint8_t

status

)

References dataConfAvailable, and dataStatus.

Referenced by MiMAC_SendPacket().

void PHY_DataReq

(

PHY_DataReq_t *

phyDataReq

)

References PHY_DataReq_t::confirmCallback, MiMem_Alloc(), miQueueAppend(), NULL, PHY_STATUS_ERROR, and _PhyTxFrame_t::phyDataReq.

Referenced by MiMAC_SendPacket().

void PHY_DecryptReq	(	uint8_t *	text,
		uint8_t *	key
	)

References AES_DIR_DECRYPT, AES_MODE_ECB, NULL, PHY_STATE_SLEEP, PHY_Wakeup(), phyState, sal_aes_read(), sal_aes_setup(), and sal_aes_wrrd().

uint8_t PHY_EdReq

(

void

)

References CCA_ED_DONE, IRQ_STATUS_REG, PHY_ED_LEVEL_REG, phyReadRegister(), phyRssiBaseVal(), phySetRxState(), phyTrxSetState(), phyWriteRegister(), RX_SYN_REG, TRX_CMD_PLL_ON, and TRX_CMD_RX_ON.

Referenced by MiMAC_ChannelAssessment().

void PHY_EncryptReq	(	uint8_t *	text,
		uint8_t *	key
	)

References AES_DIR_ENCRYPT, AES_MODE_ECB, NULL, PHY_STATE_SLEEP, PHY_Wakeup(), phyState, sal_aes_exec(), sal_aes_read(), sal_aes_setup(), and sal_aes_wrrd().

void PHY_EncryptReqCBC	(	uint8_t *	text,
		uint8_t *	key
	)

References AES_DIR_ENCRYPT, AES_MODE_CBC, NULL, PHY_STATE_SLEEP, PHY_Wakeup(), phyState, sal_aes_exec(), sal_aes_read(), sal_aes_setup(), and sal_aes_wrrd().

void PHY_Init

(

void

)

References ALT_SPECTRUM, ANT_DIV_EN, ANT_DIV_REG, ANT_EXT_SW_EN, BPSK_OQPSK, FUNC_PTR, IRQ_MASK_MODE, IRQ_MASK_REG, OQPSK_SCRAM_EN, PHY_STATE_IDLE, PHY_TX_PWR_REG, phyBand, phyModulation, phyReadRegister(), phyRxState, phyState, phyWriteRegister(), PWR_BPSK_OFFSET, RF_CTRL_0_REG, RX_SAFE_MODE, SPI_CMD_MODE, SUB_MODE, TRX_CMD_TRX_OFF, TRX_CTRL_1_REG, TRX_CTRL_2_REG, TRX_END, TRX_RPC_REG, TRX_STATE_REG, TRX_STATUS_MASK, TRX_STATUS_REG, TRX_STATUS_TRX_OFF, TX_AUTO_CRC_ON, and TX_PWR.

Referenced by MiMAC_Init().

uint16_t PHY_RandomReq

(

void

)

References delay_cycles_us(), delay_us, i, PHY_RSSI_REG, phyReadRegister(), phySetRxState(), phyTrxSetState(), phyWriteRegister(), RANDOM_NUMBER_UPDATE_INTERVAL, RND_VALUE, RX_SYN_REG, and TRX_CMD_RX_ON.

Referenced by longAddressValidationAndUpdation(), MiApp_StartConnection(), and MiMAC_Init().

void PHY_SetChannel

(

uint8_t

channel

)

References PHY_CC_CCA_REG, PHY_STATE_SLEEP, PHY_Wakeup(), phyChannel, phyReadRegister(), phySetChannel(), phyState, and phyWriteRegister().

Referenced by MiMAC_Set().

void PHY_SetIEEEAddr

(

uint8_t *

ieee_addr

)

References i, and IEEE_ADDR_0_REG.

Referenced by longAddressValidationAndUpdation(), MiMAC_Init(), and wsndemo_init().

void PHY_SetPanId

(

uint16_t

panId

)

References PAN_ID_0_REG, PAN_ID_1_REG, and phyWriteRegister().

Referenced by MiMAC_SetAltAddress().

void PHY_SetRxState

(

bool

rx

)

References phyRxState, and phySetRxState().

Referenced by MiMAC_Init().

void PHY_SetShortAddr

(

uint16_t

addr

)

References CSMA_SEED_0_REG, phyWriteRegister(), SHORT_ADDR_0_REG, and SHORT_ADDR_1_REG.

Referenced by MiMAC_SetAltAddress().

void PHY_SetTxPower

(

uint8_t

txPower

)

References PHY_TX_PWR_REG, phyReadRegister(), and phyWriteRegister().

void PHY_Sleep

(

void

)

References ANT_DIV_REG, ANT_EXT_SW_EN, PHY_STATE_SLEEP, phyReadRegister(), phyState, phyTrxSetState(), phyWriteRegister(), and TRX_CMD_TRX_OFF.

Referenced by MiMAC_PowerState().

void PHY_TaskHandler

(

void

)

References BANK_SIZE, PHY_DataReq_t::confirmCallback, i, IRQ_STATUS_REG, MAX_PSDU, NULL, RxBuffer_t::Payload, RxBuffer_t::PayloadLen, PHY_ED_LEVEL_REG, PHY_RSSI_BASE_VAL, PHY_STATE_IDLE, PHY_STATE_SLEEP, PHY_STATE_TX_WAIT_END, PHY_STATUS_CHANNEL_ACCESS_FAILURE, PHY_STATUS_ERROR, PHY_STATUS_NO_ACK, PHY_STATUS_SUCCESS, PHY_TxHandler(), phyReadRegister(), phyRssiBaseVal(), phyRxBuffer, phySetRxState(), phyState, phyTrxSetState(), phyWaitState(), RX_PACKET_SIZE, TRAC_STATUS, TRAC_STATUS_CHANNEL_ACCESS_FAILURE, TRAC_STATUS_NO_ACK, TRAC_STATUS_SUCCESS, TRX_CMD_TRX_OFF, TRX_END, TRX_STATE_REG, and TRX_STATUS_RX_AACK_ON.

Referenced by MiMAC_Task().

void PHY_TxHandler

(

void

)

References PHY_DataReq_t::confirmCallback, PHY_DataReq_t::data, IRQ_STATUS_REG, MAX_PSDU, MiMem_Free(), miQueueRemove(), NULL, PHY_STATE_IDLE, PHY_STATE_SLEEP, PHY_STATE_TX_WAIT_END, PHY_STATUS_CHANNEL_ACCESS_FAILURE, PHY_STATUS_ERROR, PHY_STATUS_NO_ACK, PHY_STATUS_SUCCESS, _PhyTxFrame_t::phyDataReq, phyReadRegister(), phySetRxState(), phyState, phyTrxSetState(), PHY_DataReq_t::polledConfirmation, MiQueue::size, TRAC_STATUS, TRAC_STATUS_CHANNEL_ACCESS_FAILURE, TRAC_STATUS_NO_ACK, TRAC_STATUS_SUCCESS, TRX_CMD_TX_ARET_ON, TRX_END, and TRX_STATE_REG.

Referenced by PHY_TaskHandler().

void PHY_Wakeup

(

void

)

References ANT_DIV_REG, ANT_EXT_SW_EN, PHY_STATE_IDLE, PHY_STATE_SLEEP, phyReadRegister(), phySetRxState(), phyState, and phyWriteRegister().

Referenced by MiMAC_PowerState(), PHY_DecryptReq(), PHY_EncryptReq(), PHY_EncryptReqCBC(), PHY_SetChannel(), and stb_ccm_secure().

void print_rx_message

(

void

)

bool validate_mic

(

void

)

RxBuffer_t RxBuffer[]

Referenced by MiMAC_DiscardPacket(), MiMAC_Init(), and MiMAC_ReceivedPacket().