|
| #define | AVR32_PM_AWEN_CANIF0WEN_MASK 0x02 |
| |
| #define | AVR32_PM_AWEN_CANIF1WEN_MASK 0x04 |
| |
| #define | BRP_MAX 64 |
| |
| #define | BRP_MIN 1 |
| |
| #define | CANIF_channel_enable_status(ch) ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_CES_MASK) >> AVR32_CANIF_CANSR_CES_OFFSET ) |
| | CANIFSR Register Access. More...
|
| |
| #define | CANIF_CHANNEL_MODE_LISTENING 1 |
| |
| #define | CANIF_CHANNEL_MODE_LOOPBACK 2 |
| |
| #define | CANIF_CHANNEL_MODE_NORMAL 0 |
| | CANIFCFG Register Access. More...
|
| |
| #define | CANIF_channel_overload_status(ch) ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_OVS_MASK) >> AVR32_CANIF_CANSR_OVS_OFFSET ) |
| |
| #define | CANIF_channel_receive_status(ch) ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_RS_MASK) >> AVR32_CANIF_CANSR_RS_OFFSET ) |
| |
| #define | CANIF_channel_transmit_status(ch) ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_TS_MASK) >> AVR32_CANIF_CANSR_TS_OFFSET ) |
| |
| #define | CANIF_clr_ide(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->ide_bit = 0;} |
| |
| #define | CANIF_clr_idemask(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->ide_mask_bit = 0);} |
| |
| #define | CANIF_clr_interrupt_status(ch) { AVR32_CANIF.channel[ch].caniscr = CANIF_get_interrupt_status(ch); } |
| |
| #define | CANIF_clr_mob(ch, mob) |
| |
| #define | CANIF_clr_overrun_mode(ch) { AVR32_CANIF.channel[ch].cancfg &= ~(1<<AVR32_CANIF_CANCFG_OVRM_OFFSET); } |
| |
| #define | CANIF_clr_reset(ch) { AVR32_CANIF.channel[ch].canctrl = (0<<AVR32_CANIF_CANCTRL_INIT_OFFSET); } |
| |
| #define | CANIF_clr_rtr(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->rtr_bit = 0;} |
| |
| #define | CANIF_clr_rtrmask(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->rtr_mask_bit = 0;} |
| |
| #define | CANIF_conf_bt(ch) |
| |
| #define | CANIF_config_rx(ch, mob) {CANIF_mob_clr_dir(ch,mob) } |
| |
| #define | CANIF_config_tx(ch, mob) {CANIF_mob_set_dir(ch,mob) } |
| |
| #define | CANIF_disable(ch) { AVR32_CANIF.channel[ch].canctrl &= ~(1<<AVR32_CANIF_CANCTRL_CEN_OFFSET); } |
| |
| #define | CANIF_disable_interrupt(ch) |
| |
| #define | CANIF_disable_wakeup(ch) { AVR32_CANIF.channel[ch].canctrl &= ~(1<<AVR32_CANIF_CANCTRL_WKEN_OFFSET); } |
| |
| #define | CANIF_disable_wakeup_interrupt(ch) { AVR32_CANIF.channel[ch].canidr = AVR32_CANIF_CANIDR_WKUPIM_MASK; } |
| | CANIFIDR Register Access. More...
|
| |
| #define | CANIF_enable(ch) { AVR32_CANIF.channel[ch].canctrl |= (1<<AVR32_CANIF_CANCTRL_CEN_OFFSET); } |
| |
| #define | CANIF_enable_interrupt(ch) |
| |
| #define | CANIF_enable_wakeup(ch) { AVR32_CANIF.channel[ch].canctrl |= (1<<AVR32_CANIF_CANCTRL_WKEN_OFFSET); } |
| |
| #define | CANIF_enable_wakeup_interrupt(ch) { AVR32_CANIF.channel[ch].canier = AVR32_CANIF_CANIER_WKUPIM_MASK; } |
| | CANIFIER Register Access. More...
|
| |
| #define | CANIF_full_abort(ch) { CANIF_disable(ch) } |
| |
| #define | CANIF_get_channel_mode(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_CMODE_MASK)>> AVR32_CANIF_CANCFG_CMODE_OFFSET) ) |
| |
| #define | CANIF_get_error_mode(ch) ( ((AVR32_CANIF.channel[ch].canfc & AVR32_CANIF_CANFC_EMODE_MASK) >> AVR32_CANIF_CANFC_EMODE_OFFSET) ) |
| | CANIFFC Register Access. More...
|
| |
| #define | CANIF_get_ext_id(ch, mob) ((CANIF_mob_get_ptr_data(ch,mob))->id & 0x1FFFFFFF ) |
| |
| #define | CANIF_get_ide(ch, mob) ((CANIF_mob_get_ptr_data(ch,mob))->ide_bit) |
| |
| #define | CANIF_get_idemask(ch, mob) ((CANIF_mob_get_ptr_data(ch,mob))->ide_mask_bit) |
| |
| #define | CANIF_get_interrupt_aerr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_AERR_MASK)>> AVR32_CANIF_CANISR_AERR_OFFSET )) |
| |
| #define | CANIF_get_interrupt_berr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_BERR_MASK)>> AVR32_CANIF_CANISR_BERR_OFFSET )) |
| |
| #define | CANIF_get_interrupt_boff_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_BOFF_MASK)>> AVR32_CANIF_CANISR_BOFF_OFFSET )) |
| |
| #define | CANIF_get_interrupt_cerr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_CERR_MASK)>> AVR32_CANIF_CANISR_CERR_OFFSET )) |
| |
| #define | CANIF_get_interrupt_error_status(ch) ( AVR32_CANIF.channel[ch].canisr & 0x3F) |
| |
| #define | CANIF_get_interrupt_ferr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_FERR_MASK)>> AVR32_CANIF_CANISR_FERR_OFFSET )) |
| |
| #define | CANIF_get_interrupt_lastmob_selected(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_LSMOB_MASK)>> AVR32_CANIF_CANISR_LSMOB_OFFSET )) |
| |
| #define | CANIF_get_interrupt_serr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_SERR_MASK)>> AVR32_CANIF_CANISR_SERR_OFFSET )) |
| |
| #define | CANIF_get_interrupt_status(ch) ( AVR32_CANIF.channel[ch].canisr) |
| | CANIFISCR Register Access. More...
|
| |
| #define | CANIF_get_interrupt_wakeup_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_WKUP_MASK)>> AVR32_CANIF_CANISR_WKUP_OFFSET )) |
| |
| #define | CANIF_get_mobctrl(ch, mob) (((unsigned volatile long*)&(AVR32_CANIF.channel[ch].mobctrl))[mob*3]) |
| | MOBCTRL Register Access. More...
|
| |
| #define | CANIF_get_overrun_mode(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_OVRM_MASK)>> AVR32_CANIF_CANCFG_OVRM_OFFSET) ) |
| |
| #define | CANIF_get_phs1(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_PHS1_MASK)>> AVR32_CANIF_CANCFG_PHS1_OFFSET) ) |
| |
| #define | CANIF_get_phs2(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_PHS2_MASK)>> AVR32_CANIF_CANCFG_PHS2_OFFSET) ) |
| |
| #define | CANIF_get_pres(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_PRES_MASK)>> AVR32_CANIF_CANCFG_PRES_OFFSET) ) |
| |
| #define | CANIF_get_prs(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_PRS_MASK)>> AVR32_CANIF_CANCFG_PRS_OFFSET) ) |
| |
| #define | CANIF_get_ram_add(ch) ( AVR32_CANIF.channel[ch].canramb ) |
| | CANRAMB Register Access. More...
|
| |
| #define | CANIF_get_rec(ch) ( ((AVR32_CANIF.channel[ch].canfc & AVR32_CANIF_CANFC_REC_MASK) >> AVR32_CANIF_CANFC_REC_OFFSET) ) |
| |
| #define | CANIF_get_rtr(ch, mob) ((CANIF_mob_get_ptr_data(ch,mob))->rtr_bit ) |
| |
| #define | CANIF_get_rtrmask(ch, mob) ((CANIF_mob_get_ptr_data(ch,mob))->rtr_mask_bit) |
| |
| #define | CANIF_get_sjw(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_SJW_MASK)>> AVR32_CANIF_CANCFG_SJW_OFFSET) ) |
| |
| #define | CANIF_get_sm(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_SM_MASK)>> AVR32_CANIF_CANCFG_SM_OFFSET) ) |
| |
| #define | CANIF_get_std_id(ch, mob) ((CANIF_mob_get_ptr_data(ch,mob))->id & 0x000007FF ) |
| |
| #define | CANIF_get_tec(ch) ( ((AVR32_CANIF.channel[ch].canfc & AVR32_CANIF_CANFC_TEC_MASK) >> AVR32_CANIF_CANFC_TEC_OFFSET) ) |
| |
| #define | CANIF_mob_allocate(ch) (CANIF_mob_get_mob_free(ch)) |
| |
| #define | CANIF_mob_clear_rxok_status(ch, mob) {AVR32_CANIF.channel[ch].mrxiscr = 1<<mob;} |
| | MRXISCR Register Access. More...
|
| |
| #define | CANIF_mob_clear_status(ch, mob) {CANIF_mob_set_status(ch,mob,0x0F)} |
| |
| #define | CANIF_mob_clear_txok_status(ch, mob) {AVR32_CANIF.channel[ch].mtxiscr = 1<<mob;} |
| | MTXISCR Register Access. More...
|
| |
| #define | CANIF_mob_clr_automode(ch, mob) { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)&~(1<<AVR32_CANIF_AM_OFFSET));} |
| |
| #define | CANIF_mob_clr_dir(ch, mob) { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)&~(1<<AVR32_CANIF_DIR_OFFSET));} |
| |
| #define | CANIF_mob_clr_dlc(ch, mob) { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)&~(0x0F<<AVR32_CANIF_DLC_OFFSET));} |
| |
| #define | CANIF_mob_disable(ch, mob) {AVR32_CANIF.channel[ch].mobdr = 1<<mob;} |
| | MOBDR Register Access. More...
|
| |
| #define | CANIF_mob_disable_interrupt(ch, mob) {AVR32_CANIF.channel[ch].mobidr = 1<<mob;} |
| | MOBIDR Register Access. More...
|
| |
| #define | CANIF_mob_enable(ch, mob) {AVR32_CANIF.channel[ch].mober = 1<<mob;} |
| | MOBER Register Access. More...
|
| |
| #define | CANIF_mob_enable_interrupt(ch, mob) {AVR32_CANIF.channel[ch].mobier = 1<<mob;} |
| | MOBIER Register Access. More...
|
| |
| #define | CANIF_mob_enable_status(ch, mob) ((AVR32_CANIF.channel[ch].mobesr >> mob)&1) |
| | MOBESR Register Access. More...
|
| |
| #define | CANIF_mob_free(ch, mob) {CANIF_mob_disable(ch,mob)} |
| |
| #define | CANIF_mob_free_get_addr_data(ch) (CANIF_SIZE_OF_CANIF_MSG*CANIF_mob_get_mob_free(ch)+CANIF_get_ram_add(ch)) |
| |
| #define | CANIF_mob_free_get_ptr_data(ch) ((can_msg_t *)(CANIF_SIZE_OF_CANIF_MSG*CANIF_mob_get_mob_free(ch)+CANIF_get_ram_add(ch))) |
| |
| #define | CANIF_mob_get_addr_data(ch, mob) ((CANIF_SIZE_OF_CANIF_MSG*mob+CANIF_get_ram_add(ch))) |
| |
| #define | CANIF_mob_get_dir(ch, mob) ( (CANIF_get_mobctrl(ch,mob)&AVR32_CANIF_DIR_MASK) >> AVR32_CANIF_DIR_OFFSET ) |
| |
| #define | CANIF_mob_get_dlc(ch, mob) ( (CANIF_get_mobctrl(ch,mob)&AVR32_CANIF_DLC_MASK)>>AVR32_CANIF_DLC_OFFSET ) |
| |
| #define | CANIF_mob_get_mob_free(ch) ((AVR32_CANIF.channel[ch].mobsch&AVR32_CANIF_MOBSCH_MAV_MASK)>>AVR32_CANIF_MOBSCH_MAV_OFFSET) |
| | MOBSCH Register Access. More...
|
| |
| #define | CANIF_mob_get_mob_rxok(ch) ((AVR32_CANIF.channel[ch].mobsch&AVR32_CANIF_MOBSCH_MRXOK_MASK)>>AVR32_CANIF_MOBSCH_MRXOK_OFFSET) |
| |
| #define | CANIF_mob_get_mob_txok(ch) ((AVR32_CANIF.channel[ch].mobsch&AVR32_CANIF_MOBSCH_MTXOK_MASK)>>AVR32_CANIF_MOBSCH_MTXOK_OFFSET) |
| |
| #define | CANIF_mob_get_ptr_data(ch, mob) ((can_msg_t *)(CANIF_SIZE_OF_CANIF_MSG*mob+CANIF_get_ram_add(ch))) |
| |
| #define | CANIF_mob_get_rxok_status(ch, mob) ((AVR32_CANIF.channel[ch].mrxisr >> mob)& 1) |
| | MRXISR Register Access. More...
|
| |
| #define | CANIF_mob_get_status(ch, mob) (((unsigned volatile long*) &(AVR32_CANIF.channel[ch].mobsr))[mob*3]) |
| | MOBSR Register Access. More...
|
| |
| #define | CANIF_mob_get_txok_status(ch, mob) ((AVR32_CANIF.channel[ch].mtxisr >> mob)& 1) |
| | MTXISR Register Access. More...
|
| |
| #define | CANIF_mob_set_automode(ch, mob) { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)| (1<<AVR32_CANIF_AM_OFFSET));} |
| |
| #define | CANIF_mob_set_dir(ch, mob) { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)| (1<<AVR32_CANIF_DIR_OFFSET));} |
| |
| #define | CANIF_mob_set_dlc(ch, mob, dlc) { CANIF_set_mobctrl(ch,mob,(CANIF_get_mobctrl(ch,mob)| (dlc<<AVR32_CANIF_DLC_OFFSET))); } |
| |
| #define | CANIF_mob_set_status(ch, mob, val) {((unsigned volatile long*) &(AVR32_CANIF.channel[ch].mobscr))[mob*3]=val;} |
| |
| #define | CANIF_mobctrl(ch, mob) (((unsigned volatile long*)&(AVR32_CANIF.channel[ch].mobctrl))[mob*3]) |
| |
| #define | CANIF_send_overload(ch) { AVR32_CANIF.channel[ch].canctrl |= (1<<AVR32_CANIF_CANCTRL_OVRQ_OFFSET); } |
| |
| #define | CANIF_set_channel_mode(ch, mode) |
| |
| #define | CANIF_set_data(ch, mob, _data) {(CANIF_mob_get_ptr_data(ch,mob))->data.u64 = _data;} |
| |
| #define | CANIF_set_ext_id(ch, mob, _id) {(CANIF_mob_get_ptr_data(ch,mob))->id = (1<<IDE_BIT)|(_id);} |
| |
| #define | CANIF_set_ext_idmask(ch, mob, mask) {(CANIF_mob_get_ptr_data(ch,mob))->id_mask = mask;} |
| |
| #define | CANIF_set_ide(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->ide_bit = 1;} |
| |
| #define | CANIF_set_idemask(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->ide_mask_bit = 1;} |
| |
| #define | CANIF_set_mobctrl(ch, mob, val) (((unsigned volatile long*)&(AVR32_CANIF.channel[ch].mobctrl))[mob*3]=val) |
| |
| #define | CANIF_set_overrun_mode(ch) { AVR32_CANIF.channel[ch].cancfg |= (1<<AVR32_CANIF_CANCFG_OVRM_OFFSET); } |
| |
| #define | CANIF_set_phs1(ch, phs1) |
| |
| #define | CANIF_set_phs2(ch, phs2) |
| |
| #define | CANIF_set_pres(ch, pres) |
| |
| #define | CANIF_set_prs(ch, prs) |
| |
| #define | CANIF_set_ram_add(ch, add) { AVR32_CANIF.channel[ch].canramb = add; } |
| |
| #define | CANIF_set_reset(ch) { AVR32_CANIF.channel[ch].canctrl = (1<<AVR32_CANIF_CANCTRL_INIT_OFFSET); } |
| | CANCTRL Register Access. More...
|
| |
| #define | CANIF_set_rtr(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->rtr_bit = 1;} |
| |
| #define | CANIF_set_rtrmask(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->rtr_mask_bit = 1;} |
| |
| #define | CANIF_set_sjw(ch, sjw) |
| |
| #define | CANIF_set_sm(ch, sm) { AVR32_CANIF.channel[ch].cancfg |= (sm<<AVR32_CANIF_CANCFG_SM_OFFSET); } |
| |
| #define | CANIF_set_std_id(ch, mob, _id) {(CANIF_mob_get_ptr_data(ch,mob))->id = (_id);} |
| |
| #define | CANIF_set_std_idmask(ch, mob, mask) {(CANIF_mob_get_ptr_data(ch,mob))->id_mask = mask;} |
| |
| #define | CANIF_SIZE_OF_CANIF_MSG (sizeof(can_msg_t)) |
| |
| #define | DATA 0 |
| |
| #define | EXTD 1 |
| |
| #define | IDE_BIT 29 |
| |
| #define | MOB_ACK_ERROR (AVR32_CANIF_AERR_MASK) |
| |
| #define | MOB_BIT_ERROR (AVR32_CANIF_BERR_MASK) |
| |
| #define | MOB_CRC_ERROR (AVR32_CANIF_CERR_MASK) |
| |
| #define | MOB_DISABLE 0xFF |
| |
| #define | MOB_FORM_ERROR (AVR32_CANIF_FERR_MASK) |
| |
| #define | MOB_NOT_COMPLETED 0x00 |
| |
| #define | MOB_NOT_REACHED |
| |
| #define | MOB_RX_COMPLETED (AVR32_CANIF_MOBSR_RXOK_MASK) |
| |
| #define | MOB_RX_COMPLETED_DLCW ((AVR32_CANIF_MOBSR_RXOK_MASK)|(AVR32_CANIF_MOBSR_DLCW_MASK)) |
| |
| #define | MOB_STUFF_ERROR (AVR32_CANIF_SERR_MASK) |
| |
| #define | MOB_TX_COMPLETED (AVR32_CANIF_MOBSR_TXOK_MASK) |
| |
| #define | NO_MOB 0xff |
| |
| #define | NTQ_MAX 25 |
| |
| #define | NTQ_MIN 8 |
| |
| #define | PHS1_MAX 8 |
| |
| #define | PHS1_MIN 2 |
| |
| #define | PHS2_MAX 8 |
| |
| #define | PHS2_MIN 2 |
| |
| #define | PRS_MAX 8 |
| |
| #define | PRS_MIN 1 |
| |
| #define | REMOTE 1 |
| |
| #define | RTR_BIT 30 |
| |
| #define | SJW_MAX 4 |
| |
| #define | SJW_MIN 1 |
| |
| #define | STATUS_CLEARED 0x00 |
| |
| #define | STD 0 |
| |
1.8.5