Chip-specific DFLL definitions.
Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
Data Structures | |
| struct | dfll_config |
| Hardware-specific representation of DFLL configuration. More... | |
Macros | |
| #define | DFLL_COARSE_MAX (AVR32_SCIF_COARSE_MASK >> AVR32_SCIF_COARSE_OFFSET) |
| #define | DFLL_FINE_HALF (1UL << (AVR32_SCIF_FINE_SIZE - 1)) |
| #define | DFLL_FINE_MAX (AVR32_SCIF_FINE_MASK >> AVR32_SCIF_FINE_OFFSET) |
| #define | DFLL_MAX_KHZ (DFLL_MAX_HZ / 1000) |
| #define | DFLL_MIN_KHZ (DFLL_MIN_HZ / 1000) |
Chip-specific DFLL characteristics | |
| #define | NR_DFLLS 1 |
| Number of on-chip DFLLs. More... | |
| #define | DFLL_MIN_HZ 20000000UL |
| Minimum frequency that the DFLL can generate. More... | |
| #define | DFLL_MAX_HZ 150000000UL |
| Maximum frequency that the DFLL can generate. More... | |
Typedefs | |
| typedef enum genclk_source | dfll_refclk_t |
| Type used for identifying a reference clock source for the DFLL. More... | |
Functions | |
| static void | dfll_config_tune_for_target_hz (struct dfll_config *cfg, uint32_t target_hz) |
| Tune the DFLL configuration for a specific target frequency. More... | |
| void | dfll_disable_closed_loop (unsigned int dfll_id) |
| Disable the DFLL identified by dfll_id. More... | |
| void | dfll_disable_open_loop (unsigned int dfll_id) |
| Disable the DFLL identified by dfll_id. More... | |
| void | dfll_enable_closed_loop (const struct dfll_config *cfg, unsigned int dfll_id) |
| Activate the configuration cfg and enable DFLL dfll_id in closed-loop mode. More... | |
| void | dfll_enable_config_defaults (unsigned int dfll_id) |
| Enable the dfll with the default configuration. More... | |
| void | dfll_enable_open_loop (const struct dfll_config *cfg, unsigned int dfll_id) |
| Activate the configuration cfg and enable DFLL dfll_id in open-loop mode. More... | |
| static uint32_t | dfll_priv_get_source_hz (dfll_refclk_t src) |
Interaction with the DFLL hardware | |
| static bool | dfll_is_coarse_locked (unsigned int dfll_id) |
| Determine whether or not a DFLL has achieved coarse lock. More... | |
| static bool | dfll_is_fine_locked (unsigned int dfll_id) |
| Determine whether or not a DFLL has achieved fine lock. More... | |
| static bool | dfll_is_accurate_locked (unsigned int dfll_id) |
| Determine whether or not a DFLL has achieved accurate lock. More... | |
| static void | dfll_enable_source (dfll_refclk_t src) |
| Enable the source of the dfll. More... | |
DFLL Configuration | |
| #define | dfll_config_defaults(cfg, dfll_id) |
| Initialize DFLL configuration using default parameters. More... | |
| #define | dfll_get_default_rate(dfll_id) |
| Return the default rate in Hz of dfll_id. More... | |
| static void | dfll_config_init_open_loop_mode (struct dfll_config *cfg) |
| Configure the DFLL configuration cfg for open-loop mode. More... | |
| static void | dfll_config_init_closed_loop_mode (struct dfll_config *cfg, dfll_refclk_t refclk, uint16_t div, uint16_t mul) |
| Configure the DFLL configuration cfg for closed-loop mode. More... | |
| static void | dfll_config_set_fractional_multiplier (struct dfll_config *cfg, uint16_t mul_i, uint16_t mul_f) |
| Set a fractional multiplier. More... | |
| static void | dfll_config_enable_dithering (struct dfll_config *cfg) |
| Enable dithering for more accurate frequency generation. More... | |
| static void | dfll_config_disable_dithering (struct dfll_config *cfg) |
| Disable dithering. More... | |
| static void | dfll_config_set_initial_tuning (struct dfll_config *cfg, uint16_t coarse, uint16_t fine) |
| Set initial VCO tuning. More... | |
| static void | dfll_config_set_max_step (struct dfll_config *cfg, uint16_t coarse, uint16_t fine) |
| Set the maximum VCO tuning step size. More... | |
| static void | dfll_config_enable_ssg (struct dfll_config *cfg, uint16_t amplitude, uint16_t step_size) |
| Enable Spread Spectrum Generator. More... | |
| static void | dfll_config_disable_ssg (struct dfll_config *cfg) |
| Disable Spread Spectrum Generator. More... | |
1.8.5