Chip-specific DFLL definitions.
Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
Data Structures | |
| struct | dfll_config |
| Hardware-specific representation of DFLL configuration. More... | |
Macros | |
| #define | DFLL_CALIB_VALUE (0x0B) |
| #define | DFLL_COARSE_MAX (255) |
| #define | DFLL_FINE_HALF (255) |
| #define | DFLL_FINE_MAX (511) |
| #define | DFLL_MAX_KHZ (DFLL_MAX_HZ / 1000) |
| #define | DFLL_MAX_RANGE1 (110000000) |
| #define | DFLL_MAX_RANGE2 (55000000) |
| #define | DFLL_MAX_RANGE3 (30000000) |
| #define | DFLL_MIN_KHZ (DFLL_MIN_HZ / 1000) |
| #define | DFLL_RANGE0 (0) |
| #define | DFLL_RANGE1 (1) |
| #define | DFLL_RANGE2 (2) |
| #define | DFLL_RANGE3 (3) |
Chip-specific DFLL characteristics | |
| #define | NR_DFLLS 1 |
| Number of on-chip DFLLs. More... | |
| #define | DFLL_MIN_HZ 20000000UL |
| Minimum frequency that the DFLL can generate. More... | |
| #define | DFLL_MAX_HZ 150000000UL |
| Maximum frequency that the DFLL can generate. More... | |
Typedefs | |
| typedef enum genclk_source | dfll_refclk_t |
| Type used for identifying a reference clock source for the DFLL. More... | |
Functions | |
| static void | dfll_config_tune_for_target_hz (struct dfll_config *cfg, uint32_t target_hz) |
| Tune the DFLL configuration for a specific target frequency. More... | |
| void | dfll_disable_closed_loop (uint32_t dfll_id) |
| void | dfll_disable_open_loop (uint32_t dfll_id) |
| void | dfll_enable_closed_loop (const struct dfll_config *cfg, uint32_t dfll_id) |
| void | dfll_enable_config_defaults (uint32_t dfll_id) |
| void | dfll_enable_open_loop (const struct dfll_config *cfg, uint32_t dfll_id) |
| static bool | dfll_is_accurate_locked (uint32_t dfll_id) |
| static bool | dfll_is_coarse_locked (uint32_t dfll_id) |
| static bool | dfll_is_fine_locked (uint32_t dfll_id) |
| static uint32_t | dfll_priv_get_source_hz (dfll_refclk_t src) |
| static void | dfll_priv_set_frequency_range (struct dfll_config *cfg, uint32_t freq) |
Interaction with the DFLL hardware | |
| static void | dfll_enable_source (dfll_refclk_t src) |
| Enable the source of the dfll. More... | |
DFLL Configuration | |
| #define | dfll_config_defaults(cfg, dfll_id) |
| Initialize DFLL configuration using default parameters. More... | |
| #define | dfll_get_default_rate(dfll_id) |
| Return the default rate in Hz of dfll_id. More... | |
| static void | dfll_config_set_max_step (struct dfll_config *cfg, uint16_t coarse, uint16_t fine) |
| Set the maximum VCO tuning step size. More... | |
| static void | dfll_config_init_open_loop_mode (struct dfll_config *cfg) |
| Configure the DFLL configuration cfg for open-loop mode. More... | |
| static void | dfll_config_set_initial_tuning (struct dfll_config *cfg, uint16_t coarse, uint16_t fine) |
| Set initial VCO tuning. More... | |
| static void | dfll_config_enable_ssg (struct dfll_config *cfg, uint16_t amplitude, uint16_t step_size) |
| Enable Spread Spectrum Generator. More... | |
| static void | dfll_config_disable_ssg (struct dfll_config *cfg) |
| Disable Spread Spectrum Generator. More... | |
1.8.5