Hardware-specific representation of DFLL configuration.
This structure contains one or more device-specific values representing the current DFLL configuration. The contents of this structure is typically different from platform to platform, and the user should not access any fields except through the DFLL configuration API.
#include <dfll.h>
Data Fields | |
uint32_t | conf |
DFLLnCONF. More... | |
uint8_t | freq_range |
Frequency Range. More... | |
uint32_t | mul |
DFLLnMUL. More... | |
struct genclk_config | ref_cfg |
Reference clock. More... | |
uint32_t | ssg |
DFLLnSSG. More... | |
uint32_t | step |
DFLLnSTEP. More... | |
uint32_t | val |
DFLLnVAL. More... | |
uint32_t dfll_config::conf |
DFLLnCONF.
Referenced by dfll_config_init_open_loop_mode(), dfll_enable_closed_loop(), dfll_enable_open_loop(), and dfll_priv_set_frequency_range().
uint8_t dfll_config::freq_range |
Frequency Range.
Referenced by dfll_config_init_open_loop_mode(), and dfll_priv_set_frequency_range().
uint32_t dfll_config::mul |
DFLLnMUL.
Referenced by dfll_config_init_open_loop_mode(), dfll_enable_closed_loop(), and dfll_enable_open_loop().
struct genclk_config dfll_config::ref_cfg |
Reference clock.
Referenced by dfll_config_init_open_loop_mode(), and dfll_enable_closed_loop().
uint32_t dfll_config::ssg |
DFLLnSSG.
Referenced by dfll_config_disable_ssg(), dfll_config_enable_ssg(), dfll_config_init_open_loop_mode(), dfll_enable_closed_loop(), and dfll_enable_open_loop().
uint32_t dfll_config::step |
DFLLnSTEP.
Referenced by dfll_config_init_open_loop_mode(), dfll_config_set_max_step(), and dfll_enable_closed_loop().
uint32_t dfll_config::val |
DFLLnVAL.
Referenced by dfll_config_init_open_loop_mode(), dfll_config_set_initial_tuning(), and dfll_enable_open_loop().