sam4l/pll.h File Reference

Chip-specific PLL definitions.

Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.

#include <compiler.h>
#include <osc.h>

Data Structures
struct	pll_config
	Hardware-specific representation of PLL configuration. More...

Macros
#define	DIV_MAX   15
#define	DIV_MIN   0
#define	MUL_MAX   16
#define	MUL_MIN   2
#define	PLL_TIMEOUT_MS   div_ceil(1000 * (PLL_MAX_STARTUP_CYCLES * 2), OSC_RCSYS_MIN_HZ)
	Number of milliseconds to wait for PLL lock. More...
#define	SCIF0_PLL_VCO_RANGE1_MAX_FREQ   240000000
#define	SCIF_PLL0_VCO_RANGE0_MAX_FREQ   180000000
#define	SCIF_PLL0_VCO_RANGE0_MIN_FREQ   80000000
#define	SCIF_PLL0_VCO_RANGE1_MIN_FREQ   160000000
Chip-specific PLL characteristics
#define	PLL_MAX_STARTUP_CYCLES   (SCIF_PLL_PLLCOUNT_Msk >> SCIF_PLL_PLLCOUNT_Pos)
	Maximum PLL startup time in number of slow clock cycles. More...
#define	NR_PLLS   1
	Number of on-chip PLLs. More...
#define	PLL_MIN_HZ   40000000
	Minimum frequency that the PLL can generate. More...
#define	PLL_MAX_HZ   240000000
	Maximum frequency that the PLL can generate. More...
Chip-specific PLL options
#define	PLL_OPT_VCO_RANGE_HIGH   0
	VCO frequency range is 160-240 MHz (80-180 MHz if unset). More...
#define	PLL_OPT_OUTPUT_DIV   1
	Divide output frequency by two. More...
#define	PLL_OPT_WBM_DISABLE   2
	Disable wide-bandwidth mode. More...
#define	PLL_NR_OPTIONS   3
	Number of PLL option bits. More...
#define	PLL_VCO_LOW_THRESHOLD
	The threshold above which to set the PLL_OPT_VCO_RANGE_HIGH option. More...
PLL configuration
#define	pll_get_default_rate(pll_id)
	Get the default rate in Hz of pll_id. More...
#define	pll_config_defaults(cfg, pll_id)
	Initialize PLL configuration using default parameters. More...

Enumerations
enum	pll_source {   PLL_SRC_OSC0 = 0,   PLL_SRC_GCLK9 = 1,   PLL_NR_SOURCES }
	PLL clock source. More...

Functions
static void	pll_config_clear_option (struct pll_config *cfg, uint32_t option)
static void	pll_config_init (struct pll_config *cfg, enum pll_source src, uint32_t divide, uint32_t mul)
	The PLL options PLL_OPT_VCO_RANGE_HIGH and PLL_OPT_OUTPUT_DIV will be set automatically based on the calculated target frequency. More...
static void	pll_config_read (struct pll_config *cfg, uint32_t pll_id)
static void	pll_config_set_option (struct pll_config *cfg, uint32_t option)
void	pll_config_write (const struct pll_config *cfg, uint32_t pll_id)
void	pll_disable (uint32_t pll_id)
void	pll_enable (const struct pll_config *cfg, uint32_t pll_id)
static void	pll_enable_config_defaults (uint32_t pll_id)
static bool	pll_is_locked (uint32_t pll_id)
Interaction with the PLL hardware
static void	pll_enable_source (enum pll_source src)
	Enable the source of the pll. More...

#define DIV_MAX   15

Referenced by pll_config_init().

#define DIV_MIN   0

Referenced by pll_config_init().

#define MUL_MAX   16

Referenced by pll_config_init().

#define MUL_MIN   2

Referenced by pll_config_init().

#define SCIF0_PLL_VCO_RANGE1_MAX_FREQ   240000000

#define SCIF_PLL0_VCO_RANGE0_MAX_FREQ   180000000

#define SCIF_PLL0_VCO_RANGE0_MIN_FREQ   80000000

#define SCIF_PLL0_VCO_RANGE1_MIN_FREQ   160000000