QSPI flash memory driver for S25FL116K.
Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
#include "qspi.h"Macros | |
| #define | S25FL1XX_ATMEL_SPI_FLASH 0x1F |
| QSPI Flash Manufacturer JEDEC ID. More... | |
| #define | S25FL1XX_BLOCK_ERASE_32K 0x52 |
| Block erase command code (32K block). More... | |
| #define | S25FL1XX_BLOCK_ERASE_4K 0x20 |
| Block erase command code (4K block). More... | |
| #define | S25FL1XX_BLOCK_ERASE_64K 0xD8 |
| Block erase command code (64K block). More... | |
| #define | S25FL1XX_BLOCK_PROTECT_Msk (7 << 2) |
| #define | S25FL1XX_BYTE_PAGE_PROGRAM 0x02 |
| Byte/page program command code. More... | |
| #define | S25FL1XX_CHIP_ERASE_1 0x60 |
| Chip erase command code 1. More... | |
| #define | S25FL1XX_CHIP_ERASE_2 0xC7 |
| Chip erase command code 2. More... | |
| #define | S25FL1XX_CHIP_PROTECT_Msk (0x1F << 2) |
| #define | S25FL1XX_CONT_MODE_RESET 0xFF |
| Continuous Read Mode Reset command code. More... | |
| #define | S25FL1XX_DEEP_PDOWN 0xB9 |
| Deep power-down command code. More... | |
| #define | S25FL1XX_ERROR_BUSY 2 |
| Device is busy executing a command. More... | |
| #define | S25FL1XX_ERROR_PROGRAM 3 |
| There was a problem while trying to program page data. More... | |
| #define | S25FL1XX_ERROR_PROTECTED 1 |
| Device is protected, operation cannot be carried out. More... | |
| #define | S25FL1XX_ERROR_SPI 4 |
| There was an SPI communication error. More... | |
| #define | S25FL1XX_MACRONIX_SPI_FLASH 0xC2 |
| #define | S25FL1XX_MANUFACTURER_DEVICE_ID 0x90 |
| Manufacturer/ Device ID command code. More... | |
| #define | S25FL1XX_PROTECT_SECTOR 0x36 |
| Protect sector command code. More... | |
| #define | S25FL1XX_READ_ARRAY 0x0B |
| Read array command code. More... | |
| #define | S25FL1XX_READ_ARRAY_DUAL 0x3B |
| Fast Read array command code. More... | |
| #define | S25FL1XX_READ_ARRAY_DUAL_IO 0xBB |
| Fast Read array command code. More... | |
| #define | S25FL1XX_READ_ARRAY_LF 0x03 |
| Read array (low frequency) command code. More... | |
| #define | S25FL1XX_READ_ARRAY_QUAD 0x6B |
| Fast Read array command code. More... | |
| #define | S25FL1XX_READ_ARRAY_QUAD_IO 0xEB |
| Fast Read array command code. More... | |
| #define | S25FL1XX_READ_JEDEC_ID 0x9F |
| Read manufacturer and device ID command code. More... | |
| #define | S25FL1XX_READ_SECTOR_PROT 0x3C |
| Read sector protection registers command code. More... | |
| #define | S25FL1XX_READ_STATUS_1 0x05 |
| Read status register command code. More... | |
| #define | S25FL1XX_READ_STATUS_2 0x35 |
| Read status register command code. More... | |
| #define | S25FL1XX_READ_STATUS_3 0x33 |
| Read status register command code. More... | |
| #define | S25FL1XX_RES_DEEP_PDOWN 0xAB |
| Resume from deep power-down command code. More... | |
| #define | S25FL1XX_SEC_PROTECT_Msk (1 << 6) |
| #define | S25FL1XX_SEQUENTIAL_PROGRAM_1 0xAD |
| Sequential program mode command code 1. More... | |
| #define | S25FL1XX_SEQUENTIAL_PROGRAM_2 0xAF |
| Sequential program mode command code 2. More... | |
| #define | S25FL1XX_SOFT_RESET 0x99 |
| Resume from deep power-down command code. More... | |
| #define | S25FL1XX_SOFT_RESET_ENABLE 0x66 |
| Resume from deep power-down command code. More... | |
| #define | S25FL1XX_SST_SPI_FLASH 0xBF |
| #define | S25FL1XX_ST_SPI_FLASH 0x20 |
| #define | S25FL1XX_STATUS_EPE (1 << 5) |
| Erase/program error bit. More... | |
| #define | S25FL1XX_STATUS_EPE_ERROR (1 << 5) |
| Erase or program error detected. More... | |
| #define | S25FL1XX_STATUS_EPE_SUCCESS (0 << 5) |
| Erase or program operation was successful. More... | |
| #define | S25FL1XX_STATUS_LATENCY_CTRL (0xF << 0) |
| Latency control bits. More... | |
| #define | S25FL1XX_STATUS_QUAD_ENABLE (1 << 1) |
| Quad enable bit. More... | |
| #define | S25FL1XX_STATUS_RDYBSY (1 << 0) |
| Device ready/busy status bit. More... | |
| #define | S25FL1XX_STATUS_RDYBSY_BUSY (1 << 0) |
| Device is busy with internal operations. More... | |
| #define | S25FL1XX_STATUS_RDYBSY_READY (0 << 0) |
| Device is ready. More... | |
| #define | S25FL1XX_STATUS_SPRL (1 << 7) |
| Sector protection registers locked bit. More... | |
| #define | S25FL1XX_STATUS_SPRL_LOCKED (1 << 7) |
| Sector protection registers are locked. More... | |
| #define | S25FL1XX_STATUS_SPRL_UNLOCKED (0 << 7) |
| Sector protection registers are unlocked. More... | |
| #define | S25FL1XX_STATUS_SWP (3 << 2) |
| Software protection status bit-field. More... | |
| #define | S25FL1XX_STATUS_SWP_PROTALL (3 << 2) |
| All sectors are software protected. More... | |
| #define | S25FL1XX_STATUS_SWP_PROTNONE (0 << 2) |
| No sector is software protected. More... | |
| #define | S25FL1XX_STATUS_SWP_PROTSOME (1 << 2) |
| Some sectors are software protected. More... | |
| #define | S25FL1XX_STATUS_WEL (1 << 1) |
| Write enable latch status bit. More... | |
| #define | S25FL1XX_STATUS_WEL_DISABLED (0 << 1) |
| Device is not write enabled. More... | |
| #define | S25FL1XX_STATUS_WEL_ENABLED (1 << 1) |
| Device is write enabled. More... | |
| #define | S25FL1XX_STATUS_WPP (1 << 4) |
| Write protect pin status bit. More... | |
| #define | S25FL1XX_STATUS_WPP_ASSERTED (1 << 4) |
| Write protect signal is asserted. More... | |
| #define | S25FL1XX_STATUS_WPP_NOTASSERTED (0 << 4) |
| Write protect signal is not asserted. More... | |
| #define | S25FL1XX_STATUS_WRAP_BYTE (1 << 5) |
| #define | S25FL1XX_STATUS_WRAP_ENABLE (0 << 4) |
| Quad enable bit. More... | |
| #define | S25FL1XX_TOP_BTM_PROTECT_Msk (1 << 5) |
| #define | S25FL1XX_UNPROTECT_SECTOR 0x39 |
| Unprotected sector command code. More... | |
| #define | S25FL1XX_WINBOND_SPI_FLASH 0xEF |
| #define | S25FL1XX_WRAP_ENABLE 0x77 |
| Resume from deep power-down command code. More... | |
| #define | S25FL1XX_WRITE_DISABLE 0x04 |
| Write disable command code. More... | |
| #define | S25FL1XX_WRITE_ENABLE 0x06 |
| Write enable command code. More... | |
| #define | S25FL1XX_WRITE_ENABLE_FOR_VOLATILE_STATUS 0x50 |
| Write Enable for Volatile Status Register. More... | |
| #define | S25FL1XX_WRITE_STATUS 0x01 |
| Write status register command code. More... | |
Enumerations | |
| enum | block_size { S25FL1XX_SIZE_4K = 0, S25FL1XX_SIZE_8K, S25FL1XX_SIZE_16K, S25FL1XX_SIZE_32K, S25FL1XX_SIZE_64K, S25FL1XX_SIZE_128K, S25FL1XX_SIZE_256K, S25FL1XX_SIZE_512K, S25FL1XX_SIZE_1M, S25FL1XX_SIZE_2M } |
Functions | |
| void | s25fl1xx_continous_read_mode_reset (struct qspid_t *qspid) |
| Issue 'CContinuous Read Mode' command, the device can return to normal SPI command mode, in which all commands can be accepts. More... | |
| uint8_t | s25fl1xx_data_protect (struct qspid_t *qspid, bool dir, enum block_size protect_size) |
| Protect the contents of the serial flash device. More... | |
| uint8_t | s25fl1xx_data_unprotect (struct qspid_t *qspid) |
| Unprotected the contents of the serial flash device. More... | |
| void | s25fl1xx_enable_wrap (struct qspid_t *qspid, uint8_t byte_align) |
| Enables critical writes operation on a serial flash device, such as sector protection, status register, etc. More... | |
| void | s25fl1xx_enter_continous_read_mode (struct qspid_t *qspid) |
| Reads data from the specified address on the serial flash. More... | |
| uint8_t | s25fl1xx_erase_64k_block (struct qspid_t *qspid, uint32_t address) |
| Erases the specified 64KB block of the serial firmware dataflash. More... | |
| uint8_t | s25fl1xx_erase_chip (struct qspid_t *qspid) |
| Erases all the content of the memory chip. More... | |
| uint8_t | s25fl1xx_erase_sector (struct qspid_t *qspid, uint32_t address) |
| Erases the specified block of the serial firmware dataflash. More... | |
| enum status_code | s25fl1xx_initialize (Qspi *qspi, struct qspi_config_t *mode_config, uint32_t use_default_config) |
| Initialize QSPI serial memory mode. More... | |
| uint8_t | s25fl1xx_protect (struct qspid_t *qspid) |
| Unprotected the contents of the serial flash device. More... | |
| uint8_t | s25fl1xx_read (struct qspid_t *qspid, uint32_t *data, uint32_t size, uint32_t address) |
| Reads data from the specified address on the serial flash. More... | |
| uint8_t | s25fl1xx_read_dual (struct qspid_t *qspid, uint32_t *data, uint32_t size, uint32_t address) |
| Reads data from the specified address on the serial flash. More... | |
| uint8_t | s25fl1xx_read_dual_io (struct qspid_t *qspid, uint32_t *data, uint32_t size, uint32_t address, uint8_t cont_mode, uint8_t secure) |
| Reads data from the specified address on the serial flash. More... | |
| uint32_t | s25fl1xx_read_jedec_id (struct qspid_t *qspid) |
| Reads and returns the serial flash device ID. More... | |
| uint8_t | s25fl1xx_read_quad (struct qspid_t *qspid, uint32_t *data, uint32_t size, uint32_t address) |
| Reads data from the specified address on the serial flash. More... | |
| uint8_t | s25fl1xx_read_quad_io (struct qspid_t *qspid, uint32_t *data, uint32_t size, uint32_t address, uint8_t cont_mode, uint8_t secure) |
| Reads data from the specified address on the serial flash. More... | |
| void | s25fl1xx_set_quad_mode (struct qspid_t *qspid, uint8_t mode) |
| Enables critical writes operation on a serial flash device, such as sector protection, status register, etc. More... | |
| void | s25fl1xx_set_read_latency_control (struct qspid_t *qspid, uint8_t latency) |
| Enables critical writes operation on a serial flash device, such as sector protection, status register, etc. More... | |
| void | s25fl1xx_soft_reset (struct qspid_t *qspid) |
| s25fl1d software reset. More... | |
| uint8_t | s25fl1xx_unprotect (struct qspid_t *qspid) |
| Unprotected the control bits of the serial flash device. More... | |
| uint8_t | s25fl1xx_write (struct qspid_t *qspid, uint32_t *pdata, uint32_t size, uint32_t address, uint8_t secure) |
| Writes data at the specified address on the serial firmware dataflash. More... | |
| #define S25FL1XX_ATMEL_SPI_FLASH 0x1F |
QSPI Flash Manufacturer JEDEC ID.
| #define S25FL1XX_BLOCK_ERASE_32K 0x52 |
Block erase command code (32K block).
| #define S25FL1XX_BLOCK_ERASE_4K 0x20 |
Block erase command code (4K block).
Referenced by s25fl1xx_erase_sector().
| #define S25FL1XX_BLOCK_ERASE_64K 0xD8 |
Block erase command code (64K block).
Referenced by s25fl1xx_erase_64k_block().
| #define S25FL1XX_BLOCK_PROTECT_Msk (7 << 2) |
Referenced by s25fl1xx_check_protected_addr(), and s25fl1xx_erase_sector().
| #define S25FL1XX_BYTE_PAGE_PROGRAM 0x02 |
Byte/page program command code.
Referenced by s25fl1xx_write().
| #define S25FL1XX_CHIP_ERASE_1 0x60 |
Chip erase command code 1.
| #define S25FL1XX_CHIP_ERASE_2 0xC7 |
Chip erase command code 2.
Referenced by s25fl1xx_erase_chip().
| #define S25FL1XX_CHIP_PROTECT_Msk (0x1F << 2) |
Referenced by s25fl1xx_data_unprotect(), and s25fl1xx_erase_chip().
| #define S25FL1XX_CONT_MODE_RESET 0xFF |
Continuous Read Mode Reset command code.
Referenced by s25fl1xx_continous_read_mode_reset().
| #define S25FL1XX_DEEP_PDOWN 0xB9 |
Deep power-down command code.
| #define S25FL1XX_ERROR_BUSY 2 |
Device is busy executing a command.
Referenced by s25fl1xx_erase_64k_block(), and s25fl1xx_erase_sector().
| #define S25FL1XX_ERROR_PROGRAM 3 |
There was a problem while trying to program page data.
| #define S25FL1XX_ERROR_PROTECTED 1 |
Device is protected, operation cannot be carried out.
Referenced by s25fl1xx_data_protect(), s25fl1xx_data_unprotect(), s25fl1xx_erase_64k_block(), s25fl1xx_erase_sector(), s25fl1xx_protect(), and s25fl1xx_unprotect().
| #define S25FL1XX_ERROR_SPI 4 |
There was an SPI communication error.
| #define S25FL1XX_MACRONIX_SPI_FLASH 0xC2 |
| #define S25FL1XX_MANUFACTURER_DEVICE_ID 0x90 |
Manufacturer/ Device ID command code.
| #define S25FL1XX_PROTECT_SECTOR 0x36 |
Protect sector command code.
| #define S25FL1XX_READ_ARRAY 0x0B |
Read array command code.
Referenced by s25fl1xx_read().
| #define S25FL1XX_READ_ARRAY_DUAL 0x3B |
Fast Read array command code.
Referenced by s25fl1xx_read_dual().
| #define S25FL1XX_READ_ARRAY_DUAL_IO 0xBB |
Fast Read array command code.
Referenced by s25fl1xx_read_dual_io().
| #define S25FL1XX_READ_ARRAY_LF 0x03 |
Read array (low frequency) command code.
| #define S25FL1XX_READ_ARRAY_QUAD 0x6B |
Fast Read array command code.
Referenced by s25fl1xx_read_quad().
| #define S25FL1XX_READ_ARRAY_QUAD_IO 0xEB |
Fast Read array command code.
Referenced by s25fl1xx_enter_continous_read_mode(), and s25fl1xx_read_quad_io().
| #define S25FL1XX_READ_JEDEC_ID 0x9F |
Read manufacturer and device ID command code.
Referenced by s25fl1xx_read_jedec_id().
| #define S25FL1XX_READ_SECTOR_PROT 0x3C |
Read sector protection registers command code.
| #define S25FL1XX_READ_STATUS_1 0x05 |
Read status register command code.
Referenced by s25fl1xx_read_status1().
| #define S25FL1XX_READ_STATUS_2 0x35 |
Read status register command code.
Referenced by s25fl1xx_read_status2().
| #define S25FL1XX_READ_STATUS_3 0x33 |
Read status register command code.
Referenced by s25fl1xx_read_status3().
| #define S25FL1XX_RES_DEEP_PDOWN 0xAB |
Resume from deep power-down command code.
| #define S25FL1XX_SEC_PROTECT_Msk (1 << 6) |
Referenced by s25fl1xx_check_protected_addr().
| #define S25FL1XX_SEQUENTIAL_PROGRAM_1 0xAD |
Sequential program mode command code 1.
| #define S25FL1XX_SEQUENTIAL_PROGRAM_2 0xAF |
Sequential program mode command code 2.
| #define S25FL1XX_SOFT_RESET 0x99 |
Resume from deep power-down command code.
Referenced by s25fl1xx_soft_reset().
| #define S25FL1XX_SOFT_RESET_ENABLE 0x66 |
Resume from deep power-down command code.
Referenced by s25fl1xx_soft_reset().
| #define S25FL1XX_SST_SPI_FLASH 0xBF |
| #define S25FL1XX_ST_SPI_FLASH 0x20 |
| #define S25FL1XX_STATUS_EPE (1 << 5) |
Erase/program error bit.
| #define S25FL1XX_STATUS_EPE_ERROR (1 << 5) |
Erase or program error detected.
| #define S25FL1XX_STATUS_EPE_SUCCESS (0 << 5) |
Erase or program operation was successful.
| #define S25FL1XX_STATUS_LATENCY_CTRL (0xF << 0) |
Latency control bits.
Referenced by s25fl1xx_set_read_latency_control().
| #define S25FL1XX_STATUS_QUAD_ENABLE (1 << 1) |
Quad enable bit.
Referenced by s25fl1xx_set_quad_mode().
| #define S25FL1XX_STATUS_RDYBSY (1 << 0) |
Device ready/busy status bit.
Referenced by s25fl1xx_erase_64k_block(), s25fl1xx_erase_chip(), s25fl1xx_erase_sector(), and s25fl1xx_wait_memory_access_end().
| #define S25FL1XX_STATUS_RDYBSY_BUSY (1 << 0) |
Device is busy with internal operations.
| #define S25FL1XX_STATUS_RDYBSY_READY (0 << 0) |
Device is ready.
Referenced by s25fl1xx_erase_64k_block(), and s25fl1xx_erase_sector().
| #define S25FL1XX_STATUS_SPRL (1 << 7) |
Sector protection registers locked bit.
Referenced by s25fl1xx_protect(), and s25fl1xx_unprotect().
| #define S25FL1XX_STATUS_SPRL_LOCKED (1 << 7) |
Sector protection registers are locked.
Referenced by s25fl1xx_protect(), and s25fl1xx_unprotect().
| #define S25FL1XX_STATUS_SPRL_UNLOCKED (0 << 7) |
Sector protection registers are unlocked.
| #define S25FL1XX_STATUS_SWP (3 << 2) |
Software protection status bit-field.
Referenced by s25fl1xx_erase_64k_block(), s25fl1xx_protect(), and s25fl1xx_unprotect().
| #define S25FL1XX_STATUS_SWP_PROTALL (3 << 2) |
All sectors are software protected.
| #define S25FL1XX_STATUS_SWP_PROTNONE (0 << 2) |
No sector is software protected.
Referenced by s25fl1xx_erase_64k_block(), and s25fl1xx_unprotect().
| #define S25FL1XX_STATUS_SWP_PROTSOME (1 << 2) |
Some sectors are software protected.
| #define S25FL1XX_STATUS_WEL (1 << 1) |
Write enable latch status bit.
Referenced by s25fl1xx_disable_write(), and s25fl1xx_enable_write().
| #define S25FL1XX_STATUS_WEL_DISABLED (0 << 1) |
Device is not write enabled.
| #define S25FL1XX_STATUS_WEL_ENABLED (1 << 1) |
Device is write enabled.
| #define S25FL1XX_STATUS_WPP (1 << 4) |
Write protect pin status bit.
| #define S25FL1XX_STATUS_WPP_ASSERTED (1 << 4) |
Write protect signal is asserted.
| #define S25FL1XX_STATUS_WPP_NOTASSERTED (0 << 4) |
Write protect signal is not asserted.
| #define S25FL1XX_STATUS_WRAP_BYTE (1 << 5) |
| #define S25FL1XX_STATUS_WRAP_ENABLE (0 << 4) |
Quad enable bit.
| #define S25FL1XX_TOP_BTM_PROTECT_Msk (1 << 5) |
Referenced by s25fl1xx_check_protected_addr().
| #define S25FL1XX_UNPROTECT_SECTOR 0x39 |
Unprotected sector command code.
| #define S25FL1XX_WINBOND_SPI_FLASH 0xEF |
| #define S25FL1XX_WRAP_ENABLE 0x77 |
Resume from deep power-down command code.
Referenced by s25fl1xx_enable_wrap().
| #define S25FL1XX_WRITE_DISABLE 0x04 |
Write disable command code.
Referenced by s25fl1xx_disable_write().
| #define S25FL1XX_WRITE_ENABLE 0x06 |
Write enable command code.
Referenced by s25fl1xx_enable_write().
| #define S25FL1XX_WRITE_ENABLE_FOR_VOLATILE_STATUS 0x50 |
Write Enable for Volatile Status Register.
| #define S25FL1XX_WRITE_STATUS 0x01 |
Write status register command code.
Referenced by s25fl1xx_write_status(), and s25fl1xx_write_volatile_status().
| enum block_size |
1.8.5