Related Project(s)

In this section you can find all the projects related to the CPU - SCIF - System Control Interface.

Example(s)

	SCIF Example 1 for STK600_RCUC3L0
	Configure a DFLL in closed-loop mode at 22MHz and set-up a generic clock GCLK with the DFLL as input. Output the generic clock on a pin. Switch into the FROZEN sleep mode while still maintaining the generic clock output.
	SCIF Example 1 for UC3L_EK
	Configure a DFLL in closed-loop mode at 22MHz and set-up a generic clock GCLK with the DFLL as input. Output the generic clock on a pin. Switch into the FROZEN sleep mode while still maintaining the generic clock output.
	SCIF Example 2 for UC3L_EK
	Configure a DFLL in closed-loop mode at 24MHz. Switch the main clock source to the DFLL and set the clock domains to 12MHz. Set-up a generic clock GCLK with the DFLL as input. Output the generic clock on a pin. Switch into the FROZEN sleep mode while still maintaining the generic clock output.
	SCIF Example3 for UC3L_EK
	Configure and start the OSC32K 32kHz oscillator. Set-up a generic clock GCLK with the OSC32K as input. Output the generic clock on a pin. Switch into the STATIC sleep mode while still maintaining the generic clock output.