PLL Management

This group contains functions and definitions related to configuring and enabling/disabling on-chip PLLs.

A PLL will take an input signal (the source), optionally divide the frequency by a configurable divider, and then multiply the frequency by a configurable multiplier.

Some devices don't support input dividers; specifying any other divisor than 1 on these devices will result in an assertion failure. Other devices may have various restrictions to the frequency range of the input and output signals.

Example: Setting up PLL0 with default parameters

The following example shows how to configure and enable PLL0 using the default parameters specified using the configuration symbols listed above.

pll_enable_config_defaults(0); 

To configure, enable PLL0 using the default parameters and to disable a specific feature like Wide Bandwidth Mode (a UC3A3-specific PLL option.), you can use this initialization process.

struct pll_config pllcfg;
if (pll_is_locked(pll_id)) {
   return; // Pll already running
}
pll_enable_source(CONFIG_PLL0_SOURCE);
pll_config_defaults(&pllcfg, 0);
pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);
pll_enable(&pllcfg, 0);
pll_wait_for_lock(0); 

When the last function call returns, PLL0 is ready to be used as the main system clock source.

Configuration Symbols

Each PLL has a set of default parameters determined by the following configuration symbols in the application's configuration file:

• CONFIG_PLLn_SOURCE: The default clock source connected to the input of PLL n. Must be one of the values defined by the pll_source enum.
• CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL n.
• CONFIG_PLLn_DIV: The default input divider of PLL n.

These configuration symbols determine the result of calling pll_config_defaults() and pll_get_default_rate().

Data Structures
struct	pll_config
	Hardware-specific representation of PLL configuration. More...

Enumerations
enum	pll_source {   PLL_SRC_RC2MHZ = OSC_PLLSRC_RC2M_gc,   PLL_SRC_RC32MHZ = OSC_PLLSRC_RC32M_gc,   PLL_SRC_XOSC = OSC_PLLSRC_XOSC_gc }
	PLL clock source. More...

Functions
static uint32_t	pll_get_default_rate_priv (enum pll_source src, unsigned int mul, unsigned int div)
	Return clock rate for specified PLL settings. More...

Chip-specific PLL characteristics
#define	NR_PLLS   1
	Number of on-chip PLLs. More...
#define	PLL_MIN_HZ   10000000UL
	Minimum frequency that the PLL can generate. More...
#define	PLL_MAX_HZ   200000000UL
	Maximum frequency that the PLL can generate. More...
#define	PLL_NR_OPTIONS   0
	Number of PLL option bits. More...

PLL configuration
static void	pll_config_init (struct pll_config *cfg, enum pll_source src, unsigned int div, unsigned int mul)
	Initialize PLL configuration from standard parameters. More...
static void	pll_config_read (struct pll_config *cfg, unsigned int pll_id)
	Read the currently active configuration of pll_id. More...
static void	pll_config_write (const struct pll_config *cfg, unsigned int pll_id)
	Activate the configuration cfg on pll_id. More...
#define	pll_get_default_rate(pll_id)
	Get the default rate in Hz of pll_id. More...
#define	pll_config_defaults(cfg, pll_id)
	Initialize PLL configuration using default parameters. More...

Interaction with the PLL hardware
static void	pll_enable (const struct pll_config *cfg, unsigned int pll_id)
	Activate the configuration cfg and enable PLL pll_id. More...
static void	pll_disable (unsigned int pll_id)
	Disable the PLL identified by pll_id. More...
static bool	pll_is_locked (unsigned int pll_id)
	Determine whether the PLL is locked or not. More...
static void	pll_enable_source (enum pll_source src)
	Enable the source of the pll. More...
static void	pll_enable_config_defaults (unsigned int pll_id)
	Enable the pll with the default configuration. More...
static int	pll_wait_for_lock (unsigned int pll_id)
	Wait for PLL pll_id to become locked. More...

#define NR_PLLS   1

Number of on-chip PLLs.

Referenced by pll_config_read(), pll_config_write(), pll_disable(), pll_enable(), pll_is_locked(), and pll_wait_for_lock().

#define pll_config_defaults	(		cfg,
			pll_id
	)

Value:

pll_config_init(cfg,                                            \
            CONFIG_PLL##pll_id##_SOURCE,                    \
            CONFIG_PLL##pll_id##_DIV,                       \
            CONFIG_PLL##pll_id##_MUL)

Initialize PLL configuration using default parameters.

After this function returns, cfg will contain a configuration which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV) times the frequency of CONFIG_PLLx_SOURCE.

Parameters

cfg	The PLL configuration to be initialized.
pll_id	Use defaults for this PLL.

#define pll_get_default_rate

(

pll_id

)

Value:

pll_get_default_rate_priv(CONFIG_PLL##pll_id##_SOURCE,    \
            CONFIG_PLL##pll_id##_MUL,                 \
            CONFIG_PLL##pll_id##_DIV)

Get the default rate in Hz of pll_id.

Referenced by sysclk_get_main_hz().

#define PLL_MAX_HZ   200000000UL

Maximum frequency that the PLL can generate.

Referenced by pll_get_default_rate_priv().

#define PLL_MIN_HZ   10000000UL

Minimum frequency that the PLL can generate.

Referenced by pll_get_default_rate_priv().

#define PLL_NR_OPTIONS   0

Number of PLL option bits.

enum pll_source

PLL clock source.

Enumerator
PLL_SRC_RC2MHZ	2 MHz Internal RC Oscillator
PLL_SRC_RC32MHZ	32 MHz Internal RC Oscillator
PLL_SRC_XOSC	External Clock Source.

void pll_config_init ( struct pll_config *  cfg, enum pll_source  src, unsigned int  div, unsigned int  mul  )

inlinestatic

Initialize PLL configuration from standard parameters.

Note

The XMEGA PLL hardware uses hard-wired input dividers, so the user must ensure that div is set as follows:

• If src is PLL_SRC_32MHZ, div must be set to 4.
• Otherwise, div must be set to 1.

This function may be defined inline because it is assumed to be called very few times, and usually with constant parameters. Inlining it will in such cases reduce the code size significantly.

Parameters

cfg	The PLL configuration to be initialized.
src	The oscillator to be used as input to the PLL.
div	PLL input divider.
mul	PLL loop divider (i.e. multiplier).

Returns

A configuration which will make the PLL run at (mul / div) times the frequency of src

References Assert, pll_config::ctrl, and PLL_SRC_RC32MHZ.

Referenced by main(), and pll_enable_config_defaults().

void pll_config_read ( struct pll_config *  cfg, unsigned int  pll_id  )

inlinestatic

Read the currently active configuration of pll_id.

Parameters

cfg	The configuration object into which to store the currently active configuration.
pll_id	The ID of the PLL to be accessed.

References Assert, pll_config::ctrl, and NR_PLLS.

void pll_config_write ( const struct pll_config *  cfg, unsigned int  pll_id  )

inlinestatic

Activate the configuration cfg on pll_id.

Parameters

cfg	The configuration object representing the PLL configuration to be activated.
pll_id	The ID of the PLL to be updated.

References Assert, pll_config::ctrl, and NR_PLLS.

Referenced by pll_enable().

void pll_disable ( unsigned int  pll_id )

inlinestatic

Disable the PLL identified by pll_id.

Note

This will not automatically disable the reference oscillator that is configured for the PLL.

After this function is called, the PLL identified by pll_id will be disabled. The PLL configuration stored in hardware may be affected by this, so if the caller needs to restore the same configuration later, it should either do a pll_config_read() before disabling the PLL, or remember the last configuration written to the PLL.

Parameters

pll_id

The ID of the PLL to be disabled.

References Assert, cpu_irq_restore(), cpu_irq_save(), and NR_PLLS.

Referenced by main().

void pll_enable ( const struct pll_config *  cfg, unsigned int  pll_id  )

inlinestatic

Activate the configuration cfg and enable PLL pll_id.

Note

If a different PLL reference oscillator than those enabled by sysclk_init() is used, the user must ensure that the desired reference is enabled prior to calling this function.

Parameters

cfg	The PLL configuration to be activated.
pll_id	The ID of the PLL to be enabled.

References Assert, cpu_irq_restore(), cpu_irq_save(), NR_PLLS, and pll_config_write().

Referenced by main(), and pll_enable_config_defaults().

void pll_enable_config_defaults ( unsigned int  pll_id )

inlinestatic

Enable the pll with the default configuration.

PLL is enabled, if the PLL is not already locked.

Parameters

pll_id

The ID of the PLL to enable.

References Assert, pll_config_init(), pll_enable(), pll_enable_source(), and pll_is_locked().

Referenced by sysclk_enable_usb(), and sysclk_init().

void pll_enable_source ( enum pll_source  src )

inlinestatic

Enable the source of the pll.

The source is enabled, if the source is not already running.

Parameters

src	The ID of the PLL source to enable.

References Assert, osc_enable(), osc_enable_autocalibration(), OSC_ID_RC32MHZ, OSC_ID_USBSOF, OSC_ID_XOSC, osc_is_ready(), osc_wait_ready(), PLL_SRC_RC2MHZ, PLL_SRC_RC32MHZ, and PLL_SRC_XOSC.

Referenced by pll_enable_config_defaults().

static uint32_t pll_get_default_rate_priv ( enum pll_source  src, unsigned int  mul, unsigned int  div  )

inlinestatic

Return clock rate for specified PLL settings.

Note

Due to the hardware implementation of the PLL, div must be 4 if the 32 MHz RC oscillator is used as reference and 1 otherwise. The reference must be above 440 kHz, and the output between 10 and 200 MHz.

Parameters

src	ID of the PLL's reference source oscillator.
mul	Multiplier for the PLL.
div	Divisor for the PLL.

Return values

Output

clock rate from PLL.

References Assert, osc_get_rate(), OSC_ID_XOSC, PLL_MAX_HZ, PLL_MIN_HZ, PLL_SRC_RC2MHZ, PLL_SRC_RC32MHZ, and PLL_SRC_XOSC.

bool pll_is_locked ( unsigned int  pll_id )

inlinestatic

Determine whether the PLL is locked or not.

Parameters

pll_id

The ID of the PLL to check.

Return values

true	The PLL is locked and ready to use as a clock source
false	The PLL is not yet locked, or has not been enabled.

References Assert, and NR_PLLS.

Referenced by main(), pll_enable_config_defaults(), and pll_wait_for_lock().

static int pll_wait_for_lock ( unsigned int  pll_id )

inlinestatic

Wait for PLL pll_id to become locked.

Todo:

Use a timeout to avoid waiting forever and hanging the system

Parameters

pll_id

The ID of the PLL to wait for.

Return values

STATUS_OK	The PLL is now locked.
ERR_TIMEOUT	Timed out waiting for PLL to become locked.

References Assert, NR_PLLS, and pll_is_locked().