Quick Start Guide for the System Clock Management service (XMEGA)

This is the quick start guide for the System Clock Management service, with step-by-step instructions on how to configure and use the service for specific use cases.

System Clock Management use cases

• Basic usage of the System Clock Management service
• Advanced use case - Peripheral Bus Clock Management (XMEGA)
• Advanced use case - DFLL auto-calibration (XMEGA)

Basic usage of the System Clock Management service

This section will present a basic use case for the System Clock Management service. This use case will configure the main system clock to 32MHz, using an internal PLL module to multiply the frequency of a crystal attached to the microcontroller. The secondary peripheral bus clock and CPU clock are scaled down from the speed of the main system clock.

Prerequisites

• None

Initialization code

Add to the application initialization code:

sysclk_init();

Workflow

1. Configure the system clocks according to the settings in conf_clock.h:

   sysclk_init(); 

Example code

Add or uncomment the following in your conf_clock.h header file, commenting out all other definitions of the same symbol(s):

#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLL

// Fpll0 = (Fclk * PLL_mul) / PLL_div
#define CONFIG_PLL0_SOURCE          PLL_SRC_XOSC
#define CONFIG_PLL0_MUL             (32000000UL / BOARD_XOSC_HZ)
#define CONFIG_PLL0_DIV             1

// Fbus = Fsys / (2 ^ BUS_div)
#define CONFIG_SYSCLK_PSADIV        SYSCLK_PSADIV_1
#define CONFIG_SYSCLK_PSBCDIV       SYSCLK_PSBCDIV_1_2

Workflow

1. Configure the main system clock to use the output of the PLL module as its source:

   #define CONFIG_SYSCLK_SOURCE          SYSCLK_SRC_PLL 

2. Configure the PLL0 module to use external crystal oscillator XOSC as its source:

   #define CONFIG_PLL0_SOURCE            PLL_SRC_XOSC 

3. Configure the PLL0 module to multiply the external oscillator XOSC frequency up to 32MHz:

   #define CONFIG_PLL0_MUL             (32000000UL / BOARD_XOSC_HZ)
   #define CONFIG_PLL0_DIV             1

   Note

   For user boards, BOARD_XOSC_HZ should be defined in the board conf_board.h configuration file as the frequency of the crystal attached to XOSC.

4. Configure the main CPU clock and slow peripheral bus to run at 16MHz, run the fast peripheral bus at the full 32MHz speed:

   #define CONFIG_SYSCLK_PSADIV       SYSCLK_PSADIV_1
   #define CONFIG_SYSCLK_PSBCDIV      SYSCLK_PSBCDIV_1_2

   Note

   Some dividers are powers of two, while others are integer division factors. Refer to the formulas in the conf_clock.h template commented above each division define.