Eth_phy_mii

Modules
	PHY registers Addresses
	Basic Mode Control Register (BMCR, 0)
	List Bit definitions: MII_BMCR.
	Basic Mode Status Register (BMSR, 1)
	Reserved bits: 6 to 0, Read as 0, ignore on write.
	PHY ID Identifier Register (PHYID, 2,3)
	List definitions: MII_PHYID1, MII_PHYID2.
	Auto-negotiation (ANAR, 4; ANLPAR, 5)
	Auto-negotiation Expansion Register (ANER, 6)
	List Bit definitions: MII_ANER.
	Specified Configuration Register (DSCR, 16)
	List Bit definitions: MII_DSCR.
	Specified Configuration and Status Register (DSCSR, 17)
	List Bit definitions: MII_DSCSR.
	10BASE-T Configuration/Status (10BTCSR, 18)
	List Bit definitions: MII_10BTCSR.
	Specified Interrupt Register (MDINTR, 21)
	List Bit definitions: MII_MDINTR.