Include definitions for the MII.
Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
Macros | |
| #define | MII_100BASE_T4 (1u << 15) |
| 100BASE-T4 Capable More... | |
| #define | MII_100BASE_T4_HD (1u << 13) |
| 100BASE-TX Half Duplex Capable More... | |
| #define | MII_100BASE_TX_FD (1u << 14) |
| 100BASE-TX Full Duplex Capable More... | |
| #define | MII_100FDX (1u << 15) |
| 100M Full Duplex Operation Mode More... | |
| #define | MII_100HDX (1u << 14) |
| 100M Half Duplex Operation Mode More... | |
| #define | MII_10_FDX (1u << 6) |
| 10BASE-T Full Duplex Support More... | |
| #define | MII_10_HDX (1u << 5) |
| 10BASE-T Support More... | |
| #define | MII_10BASE_T_FD (1u << 12) |
| 10BASE-T Full Duplex Capable More... | |
| #define | MII_10BASE_T_HD (1u << 11) |
| 10BASE-T Half Duplex Capable More... | |
| #define | MII_10BT_SER (1u << 10) |
| 10BASE-T GPSI Mode More... | |
| #define | MII_10BTCSR 18 |
| 10BASE-T Configuration and Status Register More... | |
| #define | MII_10FDX (1u << 13) |
| 10M Full Duplex Operation Mode More... | |
| #define | MII_10HDX (1u << 12) |
| 10M Half Duplex Operation Mode More... | |
| #define | MII_ACK (1u << 14) |
| Acknowledge. More... | |
| #define | MII_AN_IEEE_802_3 0x0001 |
| Selector: 4 to 0, Protocol Selection Bits. More... | |
| #define | MII_ANAR 4 |
| Auto_negotiation Advertisement Register. More... | |
| #define | MII_ANER 6 |
| Auto-negotiation Expansion Register. More... | |
| #define | MII_ANLPAR 5 |
| Auto_negotiation Link Partner Ability Register. More... | |
| #define | MII_AUTONEG (1u << 12) |
| Auto-negotiation Enable. More... | |
| #define | MII_AUTONEG_ABILITY (1u << 3) |
| Auto Configuration Ability. More... | |
| #define | MII_AUTONEG_COMP (1u << 5) |
| Auto-negotiation is completed. More... | |
| #define | MII_BMCR 0 |
| Basic Mode Control Register. More... | |
| #define | MII_BMSR 1 |
| Basic Mode Status Register. More... | |
| #define | MII_BP4B5B (1u << 15) |
| Bypass 4B5B Encoding and 5B4B Decoding. More... | |
| #define | MII_BP_ADPOK (1u << 12) |
| Bypass ADPOK. More... | |
| #define | MII_BP_ALIGN (1u << 13) |
| Bypass Symbol Alignment Function. More... | |
| #define | MII_BP_SCR (1u << 14) |
| Bypass Scrambler/Descrambler Function. More... | |
| #define | MII_COLLED_CTL (1u << 5) |
| Collision LED Enable. More... | |
| #define | MII_COLLISION_TEST (1u << 7) |
| 1 = Collision test enabled 0 = Normal operation More... | |
| #define | MII_CONFIGR 20 |
| Specified configure Register. More... | |
| #define | MII_DISCR 23 |
| Specified Disconnect Counter Register. More... | |
| #define | MII_DSCR 16 |
| Specified Configuration Register. More... | |
| #define | MII_DSCSR 17 |
| Specified Configuration and Status Register. More... | |
| #define | MII_DUPLEX_MODE (1u << 8) |
| 1 = Full duplex operation 0 = Normal operation More... | |
| #define | MII_EXTEND_CAPAB (1u << 0) |
| Extended Capability. More... | |
| #define | MII_F_LINK_100 (1u << 7) |
| Force Good Link in 100Mbps. More... | |
| #define | MII_FCS (1u << 10) |
| Reserved: 12 to 11, Write as 0, ignore on read. More... | |
| #define | MII_FDX_CHANGE (1u << 4) |
| Reserved: 7 to 5, Reserved. More... | |
| #define | MII_FDX_MASK (1u << 11) |
| Reserved: 14 to 12, Reserved. More... | |
| #define | MII_FEF (1u << 9) |
| Far end Fault Enable. More... | |
| #define | MII_HBE (1u << 13) |
| Heartbeat Enable. More... | |
| #define | MII_INTR_MASK (1u << 8) |
| Master Interrupt Mask. More... | |
| #define | MII_INTR_PEND (1u << 15) |
| Interrupt Pending. More... | |
| #define | MII_INTR_STATUS (1u << 0) |
| Reserved: 1, Reserved. More... | |
| #define | MII_ISOLATE (1u << 10) |
| 1 = Isolate 0 = Normal operation More... | |
| #define | MII_JABBER_DETECT (1u << 1) |
| Jabber Detect. More... | |
| #define | MII_JABEN (1u << 11) |
| Jabber Enable. More... | |
| #define | MII_LINK_CHANGE (1u << 2) |
| Link Status Change Interrupt. More... | |
| #define | MII_LINK_MASK (1u << 9) |
| Link Interrupt Mask. More... | |
| #define | MII_LINK_STATUS (1u << 2) |
| Link Status. More... | |
| #define | MII_LOOPBACK (1u << 14) |
| 1=loopback Enabled; 0=Normal Operation More... | |
| #define | MII_LP_AN_ABLE (1u << 0) |
| Link Partner Auto-negotiation Able. More... | |
| #define | MII_LP_EN (1u << 14) |
| Reserved: 18 to 15, Read as 0, ignore on write. More... | |
| #define | MII_LP_NP_ABLE (1u << 3) |
| Link Partner Next Page Able. More... | |
| #define | MII_LSB_MASK 0x3F |
| Mask for PHY ID LSB. More... | |
| #define | MII_MDINTR 21 |
| Specified Interrupt Register. More... | |
| #define | MII_MF_PREAMB_SUPPR (1u << 6) |
| Reserved bits: 10 to 7, Read as 0, ignore on write. More... | |
| #define | MII_MFP_SC (1u << 2) |
| MF Preamble Suppression Control. More... | |
| #define | MII_NP (1u << 15) |
| Next page Indication. More... | |
| #define | MII_NP_ABLE (1u << 2) |
| Local Device Next Page Able. More... | |
| #define | MII_OUI_LSB 0x2E /** Davicom PHY OUI LSB */ |
| #define | MII_OUI_MSB 0x0181 /** Davicom PHY OUI MSB */ |
| #define | MII_PAGE_RX (1u << 1) |
| New Page Received. More... | |
| #define | MII_PDF (1u << 4) |
| Reserved: 15 to 5, Read as 0, ignore on write. More... | |
| #define | MII_PHYID1 2 |
| PHY Identifier Register 1. More... | |
| #define | MII_PHYID2 3 |
| PHY Identifier Register 2. More... | |
| #define | MII_POLR (1u << 0) |
| Reserved: 9 to 1, Read as 0, ignore on write. More... | |
| #define | MII_POWER_DOWN (1u << 11) |
| 1=Power down 0=Normal operation More... | |
| #define | MII_PWDOR 19 |
| Power Down Control Register. More... | |
| #define | MII_RECR 22 |
| Specified Receive Error Counter Register. More... | |
| #define | MII_REMOTE_FAULT (1u << 4) |
| Remote Fault. More... | |
| #define | MII_REPEATER (1u << 11) |
| Repeater/Node Mode. More... | |
| #define | MII_RESET (1u << 15) |
| 1= Software Reset; 0=Normal Operation More... | |
| #define | MII_RESTART_AUTONEG (1u << 9) |
| 1 = Restart auto-negotiation 0 = Normal operation More... | |
| #define | MII_RF (1u << 13) |
| Remote Fault. More... | |
| #define | MII_RLOUT (1u << 0) |
| Remote Loopout Control. More... | |
| #define | MII_RLSR 24 |
| Hardware Reset Latch State Register. More... | |
| #define | MII_RMII_ENABLE (1u << 8) |
| Reduced MII Enable. More... | |
| #define | MII_RPDCTR_EN (1u << 4) |
| Reduced Power Down Control Enable. More... | |
| #define | MII_SLEEP (1u << 1) |
| Sleep Mode. More... | |
| #define | MII_SM_RST (1u << 3) |
| Reset State Machine. More... | |
| #define | MII_SPD_CHANGE (1u << 3) |
| Speed Status Change Interrupt. More... | |
| #define | MII_SPD_MASK (1u << 10) |
| Speed Interrupt Mask. More... | |
| #define | MII_SPEED_SELECT (1u << 13) |
| 1=100Mbps; 0=10Mbps More... | |
| #define | MII_SPLED_CTL (1u << 6) |
| Speed LED Disable. More... | |
| #define | MII_SQUELCH (1u << 12) |
| Squelch Enable. More... | |
| #define | MII_T4 (1u << 9) |
| 100BASE-T4 Support More... | |
| #define | MII_TX (1u << 10) |
| 100BASE-TX Mode Control More... | |
| #define | MII_TX_FDX (1u << 8) |
| 100BASE-TX Full Duplex Support More... | |
| #define | MII_TX_HDX (1u << 7) |
| 100BASE-TX Support More... | |
1.8.5