#include "tal_types.h"

Macros
#define	AACK_ACK_TIME_12_SYMBOLS (0)
	Constants. More...

#define	AACK_ACK_TIME_2_SYMBOLS (1)
	Constant AACK_ACK_TIME_2_symbols for sub-register SR_AACK_ACK_TIME. More...

#define	ACK_DISABLE (1)
	Constant ACK_DISABLE for sub-register AACK_DIS_ACK in register RG_CSMA_SEED_1. More...

#define	ACK_ENABLE (0)
	Constant ACK_ENABLE for sub-register AACK_DIS_ACK in register RG_CSMA_SEED_1. More...

#define	AES_BASE_ADDR (0x80)
	Register addresses. More...

#define	AES_DIR_DECRYPT (1)
	AES core operation direction: Decryption (ECB) More...

#define	AES_DIR_ENCRYPT (0)
	AES core operation direction: Encryption (ECB, CBC) More...

#define	AES_DONE (1)
	AES core operation status: AES module finished. More...

#define	AES_MODE_CBC (2)
	Set CBC mode. More...

#define	AES_MODE_ECB (0)
	Set ECB mode. More...

#define	AES_MODE_KEY (1)
	Set key mode. More...

#define	AES_NOT_DONE (0)
	AES core operation status: AES module did not finish. More...

#define	AES_REQUEST (1)
	Initiate an AES operation. More...

#define	ALTRATE_1MBPS (2)
	Constant ALTRATE_1Mbps for sub-register SR_OQPSK_DATA_RATE. More...

#define	ALTRATE_250KBPS (0)
	Constant ALTRATE_250kbps for sub-register SR_OQPSK_DATA_RATE. More...

#define	ALTRATE_2MBPS (3)
	Constant ALTRATE_2Mbps for sub-register SR_OQPSK_DATA_RATE. More...

#define	ALTRATE_500KBPS (1)
	Constant ALTRATE_500kbps for sub-register SR_OQPSK_DATA_RATE. More...

#define	ANT_CTRL_0 (0)
	Constant ANT_CTRL_0 for sub-register SR_ANT_CTRL in register RG_ANT_DIV. More...

#define	ANT_CTRL_1 (1)
	Constant ANT_CTRL_1 for sub-register SR_ANT_CTRL in register RG_ANT_DIV. More...

#define	ANT_CTRL_2 (2)
	Constant ANT_CTRL_2 for sub-register SR_ANT_CTRL in register RG_ANT_DIV. More...

#define	ANT_CTRL_3 (3)
	Constant ANT_CTRL_3 for sub-register SR_ANT_CTRL in register RG_ANT_DIV. More...

#define	ANT_DIV_DISABLE (0)
	Constant ANT_DIV_disable for sub-register SR_ANT_DIV_EN. More...

#define	ANT_DIV_ENABLE (1)
	Constant ANT_DIV_enable for sub-register SR_ANT_DIV_EN. More...

#define	ANT_EXT_SW_DISABLE (0)
	Constant ANT_EXT_SW_DISABLE for sub-register SR_ANT_EXT_SW_EN. More...

#define	ANT_EXT_SW_ENABLE (1)
	Constant ANT_EXT_SW_ENABLE for sub-register SR_ANT_EXT_SW_EN. More...

#define	ANT_SEL_ANTENNA_0 (0)
	Constant ANT_SEL_antenna_0 for sub-register SR_ANT_SEL. More...

#define	ANT_SEL_ANTENNA_1 (1)
	Constant ANT_SEL_antenna_1 for sub-register SR_ANT_SEL. More...

#define	AT86RF231_PART_NUM (3)
	Constant RF231 for sub-register SR_PART_NUM. More...

#define	AT86RF231_VERSION_NUM (2)
	Constant RF231 for sub-register SR_VERSION_NUM. More...

#define	BATMON_ABOVE_THRES (1)
	Constant BATMON_ABOVE_THRES for sub-register SR_BATMON_OK. More...

#define	BATMON_BELOW_THRES (0)
	Constant BATMON_BELOW_THRES for sub-register SR_BATMON_OK. More...

#define	BATMON_HIGH_RANGE (1)
	Constant BATMON_HIGH_RANGE for sub-register BATMON_HR in register RG_BATMON. More...

#define	BATMON_LOW_RANGE (0)
	Constant BATMON_LOW_RANGE for sub-register BATMON_HR in register RG_BATMON. More...

#define	CCA_DETECTION_DONE (1)
	Constant CCA_calculation_done for sub-register SR_CCA_DONE. More...

#define	CCA_DETECTION_NOT_DONE (0)
	Constant CCA_calculation_not_finished for sub-register SR_CCA_DONE. More...

#define	CCA_DETECTION_TIME_SYM (8)

#define	CCA_DURATION_SYM

#define	CCA_MODE_0 (0)
	Constant CCA_Mode_0 for sub-register SR_CCA_MODE. More...

#define	CCA_MODE_1 (1)
	Constant CCA_Mode_1 for sub-register SR_CCA_MODE. More...

#define	CCA_MODE_2 (2)
	Constant CCA_Mode_2 for sub-register SR_CCA_MODE. More...

#define	CCA_MODE_3 (3)
	Constant CCA_Mode_3 for sub-register SR_CCA_MODE. More...

#define	CCA_PRE_START_DURATION_US (20)

#define	CCA_PREPARATION_DURATION_US (50)

#define	CCA_PROCESS_TIME_SYM (1)

#define	CCA_START (1)
	Constant CCA_START for sub-register CCA_REQUEST in register RG_PHY_CC_CCA. More...

#define	CCA_STATUS_CHANNEL_IS_BUSY (0)
	Constant CCA_STATUS_channel_is_busy for sub-register SR_CCA_STATUS. More...

#define	CCA_STATUS_CHANNEL_IS_IDLE (1)
	Constant CCA_STATUS_channel_is_idle for sub-register SR_CCA_STATUS. More...

#define	CLKM_16MHZ (5)
	Constant CLKM_16MHz for sub-register SR_CLKM_CTRL. More...

#define	CLKM_1_16MHZ (7)
	Constant CLKM_1_16MHz for sub-register SR_CLKM_CTRL. More...

#define	CLKM_1_4MHZ (6)
	Constant CLKM_1_4MHz for sub-register SR_CLKM_CTRL. More...

#define	CLKM_1MHZ (1)
	Constant CLKM_1MHz for sub-register SR_CLKM_CTRL. More...

#define	CLKM_2MHZ (2)
	Constant CLKM_2MHz for sub-register SR_CLKM_CTRL. More...

#define	CLKM_4MHZ (3)
	Constant CLKM_4MHz for sub-register SR_CLKM_CTRL. More...

#define	CLKM_8MHZ (4)
	Constant CLKM_8MHz for sub-register SR_CLKM_CTRL. More...

#define	CLKM_NO_CLOCK (0)
	Constant CLKM_no_clock for sub-register SR_CLKM_CTRL. More...

#define	CLKM_SHA_DISABLE (0)
	Constant CLKM_SHA_disable for sub-register SR_CLKM_SHA_SEL. More...

#define	CLKM_SHA_ENABLE (1)
	Constant CLKM_SHA_enable for sub-register SR_CLKM_SHA_SEL. More...

#define	CRC16_NOT_VALID (0)
	Constant CRC16_not_valid for sub-register SR_RX_CRC_VALID. More...

#define	CRC16_VALID (1)
	Constant CRC16_valid for sub-register SR_RX_CRC_VALID. More...

#define	CSMA_PROCESSING_TIME_US (100)

#define	FRAME_VERSION_0 (0)
	Constant FRAME_VERSION_0 for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1. More...

#define	FRAME_VERSION_01 (1)
	Constant FRAME_VERSION_01 for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1. More...

#define	FRAME_VERSION_012 (2)
	Constant FRAME_VERSION_012 for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1. More...

#define	FRAME_VERSION_IGNORED (3)
	Constant FRAME_VERSION_IGNORED for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1. More...

#define	IRQ_MASK_MODE_OFF (0)
	Constant IRQ_MASK_MODE_off for sub-register SR_IRQ_MASK_MODE. More...

#define	IRQ_MASK_MODE_ON (1)
	Constant IRQ_MASK_MODE_on for sub-register SR_IRQ_MASK_MODE. More...

#define	IRQ_POL_HIGH_ACTIVE_IRQ (0)
	Constant IRQ_POL_high_active_IRQ for sub-register SR_IRQ_POLARITY. More...

#define	IRQ_POL_LOW_ACTIVE_IRQ (1)
	Constant IRQ_POL_low_active_IRQ for sub-register SR_IRQ_POLARITY. More...

#define	IRQ_PROCESSING_DLY_US (32)

#define	OQPSK_SCRAM_DISABLE (0)
	Constant OQPSK_SCRAM_DISABLE for sub-register OQPSK_SCRAM_EN in register RG_TRX_CTRL_2. More...

#define	OQPSK_SCRAM_ENABLE (1)
	Constant OQPSK_SCRAM_ENABLE for sub-register OQPSK_SCRAM_EN in register RG_TRX_CTRL_2. More...

#define	P_ON_TO_CLKM_AVAILABLE_MAX_US

#define	P_ON_TO_CLKM_AVAILABLE_TYP_US

#define	PA_BUF_LT_0_US (0)
	Constant PA_BUF_LT_0s for sub-register SR_PA_BUF_LT. More...

#define	PA_BUF_LT_2_US (1)
	Constant PA_BUF_LT_2s for sub-register SR_PA_BUF_LT. More...

#define	PA_BUF_LT_4_US (2)
	Constant PA_BUF_LT_4s for sub-register SR_PA_BUF_LT. More...

#define	PA_BUF_LT_6_US (3)
	Constant PA_BUF_LT_6s for sub-register SR_PA_BUF_LT. More...

#define	PA_EXT_DISABLE (0)
	Constant PA_EXT_disable for sub-register SR_PA_EXT_EN. More...

#define	PA_EXT_ENABLE (1)
	Constant PA_EXT_enable for sub-register SR_PA_EXT_EN. More...

#define	PA_LT_2_US (0)
	Constant PA_LT_2s for sub-register SR_PA_LT. More...

#define	PA_LT_4_US (1)
	Constant PA_LT_4s for sub-register SR_PA_LT. More...

#define	PA_LT_6_US (2)
	Constant PA_LT_6s for sub-register SR_PA_LT. More...

#define	PA_LT_8_US (3)
	Constant PA_LT_8s for sub-register SR_PA_LT. More...

#define	PAD_CLKM_2_MA (0)
	Constant PAD_CLKM_2mA for sub-register SR_PAD_IO_CLKM. More...

#define	PAD_CLKM_4_MA (1)
	Constant PAD_CLKM_4mA for sub-register SR_PAD_IO_CLKM. More...

#define	PAD_CLKM_6_MA (2)
	Constant PAD_CLKM_6mA for sub-register SR_PAD_IO_CLKM. More...

#define	PAD_CLKM_8_MA (3)
	Constant PAD_CLKM_8mA for sub-register SR_PAD_IO_CLKM. More...

#define	PAD_IO_2_MA (0)
	Constant PAD_IO_2mA for sub-register SR_PAD_IO. More...

#define	PAD_IO_4_MA (1)
	Constant PAD_IO_4mA for sub-register SR_PAD_IO. More...

#define	PAD_IO_6_MA (2)
	Constant PAD_IO_6mA for sub-register SR_PAD_IO. More...

#define	PAD_IO_8_MA (3)
	Constant PAD_IO_8mA for sub-register SR_PAD_IO. More...

#define	PD_ACK_BIT_SET_DISABLE (0)
	Constant PD_ACK_BIT_SET_DISABLE for sub-register AACK_SET_PD in register RG_CSMA_SEED_1. More...

#define	PD_ACK_BIT_SET_ENABLE (1)
	Constant PD_ACK_BIT_SET_ENABLE for sub-register AACK_SET_PD in register RG_CSMA_SEED_1. More...

#define	PRE_TX_DURATION_US (32)

#define	PROM_MODE_DISABLE (0)
	Constant PROM_MODE_DISABLE for sub-register AACK_PROM_MODE in register RG_XAH_CTRL_1. More...

#define	PROM_MODE_ENABLE (1)
	Constant PROM_MODE_ENABLE for sub-register AACK_PROM_MODE in register RG_XAH_CTRL_1. More...

#define	RF231_RAM_SIZE (0x80)
	RF231 FIFO size. More...

#define	RG_AES_CTRL (0x03)
	Offset for register AES_CTRL. More...

#define	RG_AES_CTRL_MIRROR (0x94)
	mirrored version of AES_CTRL, SRAM address More...

#define	RG_AES_STATE_KEY_0 (0x04)
	Offset for register AES_STATE_KEY_0. More...

#define	RG_AES_STATUS (0x02)
	Offset for register AES_STATUS. More...

#define	RG_ANT_DIV (0x0d)
	Offset for register ANT_DIV. More...

#define	RG_BATMON (0x11)
	Offset for register BATMON. More...

#define	RG_CCA_THRES (0x09)
	Offset for register CCA_THRES. More...

#define	RG_CSMA_BE (0x2f)
	Offset for register CSMA_BE. More...

#define	RG_CSMA_SEED_0 (0x2d)
	Offset for register CSMA_SEED_0. More...

#define	RG_CSMA_SEED_1 (0x2e)
	Offset for register CSMA_SEED_1. More...

#define	RG_FTN_CTRL (0x18)
	Offset for register FTN_CTRL. More...

#define	RG_IEEE_ADDR_0 (0x24)
	Offset for register IEEE_ADDR_0. More...

#define	RG_IEEE_ADDR_1 (0x25)
	Offset for register IEEE_ADDR_1. More...

#define	RG_IEEE_ADDR_2 (0x26)
	Offset for register IEEE_ADDR_2. More...

#define	RG_IEEE_ADDR_3 (0x27)
	Offset for register IEEE_ADDR_3. More...

#define	RG_IEEE_ADDR_4 (0x28)
	Offset for register IEEE_ADDR_4. More...

#define	RG_IEEE_ADDR_5 (0x29)
	Offset for register IEEE_ADDR_5. More...

#define	RG_IEEE_ADDR_6 (0x2a)
	Offset for register IEEE_ADDR_6. More...

#define	RG_IEEE_ADDR_7 (0x2b)
	Offset for register IEEE_ADDR_7. More...

#define	RG_IRQ_MASK (0x0e)
	Offset for register IRQ_MASK. More...

#define	RG_IRQ_STATUS (0x0f)
	Offset for register IRQ_STATUS. More...

#define	RG_MAN_ID_0 (0x1e)
	Offset for register MAN_ID_0. More...

#define	RG_MAN_ID_1 (0x1f)
	Offset for register MAN_ID_1. More...

#define	RG_PAN_ID_0 (0x22)
	Offset for register PAN_ID_0. More...

#define	RG_PAN_ID_1 (0x23)
	Offset for register PAN_ID_1. More...

#define	RG_PART_NUM (0x1c)
	Offset for register PART_NUM. More...

#define	RG_PHY_CC_CCA (0x08)
	Offset for register PHY_CC_CCA. More...

#define	RG_PHY_ED_LEVEL (0x07)
	Offset for register PHY_ED_LEVEL. More...

#define	RG_PHY_RSSI (0x06)
	Offset for register PHY_RSSI. More...

#define	RG_PHY_TX_PWR (0x05)
	Offset for register PHY_TX_PWR. More...

#define	RG_PLL_CF (0x1a)
	Offset for register PLL_CF. More...

#define	RG_PLL_DCU (0x1b)
	Offset for register PLL_DCU. More...

#define	RG_RX_CTRL (0x0a)
	Offset for register RX_CTRL. More...

#define	RG_RX_SYN (0x15)
	Offset for register RX_SYN. More...

#define	RG_SFD_VALUE (0x0b)
	Offset for register SFD_VALUE. More...

#define	RG_SHORT_ADDR_0 (0x20)
	Offset for register SHORT_ADDR_0. More...

#define	RG_SHORT_ADDR_1 (0x21)
	Offset for register SHORT_ADDR_1. More...

#define	RG_TRX_CTRL_0 (0x03)
	Offset for register TRX_CTRL_0. More...

#define	RG_TRX_CTRL_1 (0x04)
	Offset for register TRX_CTRL_1. More...

#define	RG_TRX_CTRL_2 (0x0c)
	Offset for register TRX_CTRL_2. More...

#define	RG_TRX_STATE (0x02)
	Offset for register TRX_STATE. More...

#define	RG_TRX_STATUS (0x01)
	Offset for register TRX_STATUS. More...

#define	RG_VERSION_NUM (0x1d)
	Offset for register VERSION_NUM. More...

#define	RG_VREG_CTRL (0x10)
	Offset for register VREG_CTRL. More...

#define	RG_XAH_CTRL_0 (0x2c)
	Offset for register XAH_CTRL_0. More...

#define	RG_XAH_CTRL_1 (0x17)
	Offset for register XAH_CTRL_1. More...

#define	RG_XOSC_CTRL (0x12)
	Offset for register XOSC_CTRL. More...

#define	RSSI_BASE_VAL_DBM (-91)
	Minimum RSSI sensitivity value in dBm, which is equivalent to the value 0 in sub register SR_RSSI. More...

#define	RST_PULSE_WIDTH_US (10)

#define	RX_DISABLE (1)
	Constant RX_DISABLE for sub-register RX_PDT_DIS. More...

#define	RX_ENABLE (0)
	Constant RX_ENABLE for sub-register RX_PDT_DIS. More...

#define	RX_SAFE_MODE_DISABLE (0)
	Constant RX_SAFE_MODE_DISABLE for sub-register RX_SAFE_MODE in register RG_TRX_CTRL_2. More...

#define	RX_SAFE_MODE_ENABLE (1)
	Constant RX_SAFE_MODE_ENABLE for sub-register RX_SAFE_MODE in register RG_TRX_CTRL_2. More...

#define	SLEEP_TO_TRX_OFF_MAX_US

#define	SLEEP_TO_TRX_OFF_TYP_US

#define	SPI_CMD_MODE_DEFAULT (0)
	Constant SPI_CMD_MODE_default for sub-register SR_SPI_CMD_MODE. More...

#define	SPI_CMD_MODE_MONITOR_IRQ_STATUS (3)
	Constant SPI_CMD_MODE_monitor_IRQ_STATUS for sub-register SR_SPI_CMD_MODE. More...

#define	SPI_CMD_MODE_MONITOR_PHY_RSSI (2)
	Constant SPI_CMD_MODE_monitor_PHY_RSSI for sub-register SR_SPI_CMD_MODE. More...

#define	SPI_CMD_MODE_MONITOR_TRX_STATUS (1)
	Constant SPI_CMD_MODE_monitor_TRX_STATUS for sub-register SR_SPI_CMD_MODE. More...

#define	SR_AACK_ACK_TIME 0x17, 0x04, 2
	Subregister access. More...

#define	SR_AACK_DIS_ACK 0x2e, 0x10, 4
	Access parameters for sub-register AACK_DIS_ACK in register RG_CSMA_SEED_1. More...

#define	SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
	Access parameters for sub-register AACK_FLTR_RES_FT in register RG_XAH_CTRL_1. More...

#define	SR_AACK_FVN_MODE 0x2e, 0xc0, 6
	Access parameters for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1. More...

#define	SR_AACK_I_AM_COORD 0x2e, 0x08, 3
	Access parameters for sub-register AACK_I_AM_COORD in register RG_CSMA_SEED_1. More...

#define	SR_AACK_PROM_MODE 0x17, 0x02, 1
	Access parameters for sub-register AACK_PROM_MODE in register RG_XAH_CTRL_1. More...

#define	SR_AACK_SET_PD 0x2e, 0x20, 5
	Access parameters for sub-register AACK_SET_PD in register RG_CSMA_SEED_1. More...

#define	SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
	Access parameters for sub-register AACK_UPLD_RES_FT in register RG_XAH_CTRL_1. More...

#define	SR_AES_DIR 0x03, 0x08, 3
	Access parameters for sub-register AES_DIR in register RG_AES_CTRL. More...

#define	SR_AES_MODE 0x03, 0x70, 4
	Access parameters for sub-register AES_MODE in register RG_AES_CTRL. More...

#define	SR_AES_REQUEST 0x03, 0x80, 7
	Access parameters for sub-register AES_REQUEST in register RG_AES_CTRL. More...

#define	SR_ANT_CTRL 0x0d, 0x03, 0
	Access parameters for sub-register ANT_CTRL in register RG_ANT_DIV. More...

#define	SR_ANT_DIV_EN 0x0d, 0x08, 3
	Access parameters for sub-register ANT_DIV_EN in register RG_ANT_DIV. More...

#define	SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
	Access parameters for sub-register ANT_EXT_SW_EN in register RG_ANT_DIV. More...

#define	SR_ANT_SEL 0x0d, 0x80, 7
	Access parameters for sub-register ANT_SEL in register RG_ANT_DIV. More...

#define	SR_AVDD_OK 0x10, 0x40, 6
	Access parameters for sub-register AVDD_OK in register RG_VREG_CTRL. More...

#define	SR_AVREG_EXT 0x10, 0x80, 7
	Access parameters for sub-register AVREG_EXT in register RG_VREG_CTRL. More...

#define	SR_BATMON_HR 0x11, 0x10, 4
	Access parameters for sub-register BATMON_HR in register RG_BATMON. More...

#define	SR_BATMON_OK 0x11, 0x20, 5
	Access parameters for sub-register BATMON_OK in register RG_BATMON. More...

#define	SR_BATMON_VTH 0x11, 0x0f, 0
	Access parameters for sub-register BATMON_VTH in register RG_BATMON. More...

#define	SR_CCA_DONE 0x01, 0x80, 7
	Access parameters for sub-register CCA_DONE in register RG_TRX_STATUS. More...

#define	SR_CCA_ED_THRES 0x09, 0x0f, 0
	Access parameters for sub-register CCA_ED_THRES in register RG_CCA_THRES. More...

#define	SR_CCA_MODE 0x08, 0x60, 5
	Access parameters for sub-register CCA_MODE in register RG_PHY_CC_CCA. More...

#define	SR_CCA_REQUEST 0x08, 0x80, 7
	Access parameters for sub-register CCA_REQUEST in register RG_PHY_CC_CCA. More...

#define	SR_CCA_STATUS 0x01, 0x40, 6
	Access parameters for sub-register CCA_STATUS in register RG_TRX_STATUS. More...

#define	SR_CHANNEL 0x08, 0x1f, 0
	Access parameters for sub-register CHANNEL in register RG_PHY_CC_CCA. More...

#define	SR_CLKM_CTRL 0x03, 0x07, 0
	Access parameters for sub-register CLKM_CTRL in register RG_TRX_CTRL_0. More...

#define	SR_CLKM_SHA_SEL 0x03, 0x08, 3
	Access parameters for sub-register CLKM_SHA_SEL in register RG_TRX_CTRL_0. More...

#define	SR_CSMA_SEED_0 0x2d, 0xff, 0
	Access parameters for sub-register CSMA_SEED_0 in register RG_CSMA_SEED_0. More...

#define	SR_CSMA_SEED_1 0x2e, 0x07, 0
	Access parameters for sub-register CSMA_SEED_1 in register RG_CSMA_SEED_1. More...

#define	SR_DVDD_OK 0x10, 0x04, 2
	Access parameters for sub-register DVDD_OK in register RG_VREG_CTRL. More...

#define	SR_DVREG_EXT 0x10, 0x08, 3
	Access parameters for sub-register DVREG_EXT in register RG_VREG_CTRL. More...

#define	SR_ED_LEVEL 0x07, 0xff, 0
	Access parameters for sub-register ED_LEVEL in register RG_PHY_ED_LEVEL. More...

#define	SR_FTN_START 0x18, 0x80, 7
	Access parameters for sub-register FTN_START in register RG_FTN_CTRL. More...

#define	SR_IEEE_ADDR_0 0x24, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_0 in register RG_IEEE_ADDR_0. More...

#define	SR_IEEE_ADDR_1 0x25, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_1 in register RG_IEEE_ADDR_1. More...

#define	SR_IEEE_ADDR_2 0x26, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_2 in register RG_IEEE_ADDR_2. More...

#define	SR_IEEE_ADDR_3 0x27, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_3 in register RG_IEEE_ADDR_3. More...

#define	SR_IEEE_ADDR_4 0x28, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_4 in register RG_IEEE_ADDR_4. More...

#define	SR_IEEE_ADDR_5 0x29, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_5 in register RG_IEEE_ADDR_5. More...

#define	SR_IEEE_ADDR_6 0x2a, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_6 in register RG_IEEE_ADDR_6. More...

#define	SR_IEEE_ADDR_7 0x2b, 0xff, 0
	Access parameters for sub-register IEEE_ADDR_7 in register RG_IEEE_ADDR_7. More...

#define	SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
	Access parameters for sub-register IRQ_0_PLL_LOCK in register RG_IRQ_STATUS. More...

#define	SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
	Access parameters for sub-register IRQ_1_PLL_UNLOCK in register RG_IRQ_STATUS. More...

#define	SR_IRQ_2_EXT_EN 0x04, 0x40, 6
	Access parameters for sub-register IRQ_2_EXT_EN in register RG_TRX_CTRL_1. More...

#define	SR_IRQ_2_RX_START 0x0f, 0x04, 2
	Access parameters for sub-register IRQ_2_RX_START in register RG_IRQ_STATUS. More...

#define	SR_IRQ_3_TRX_END 0x0f, 0x08, 3
	Access parameters for sub-register IRQ_3_TRX_END in register RG_IRQ_STATUS. More...

#define	SR_IRQ_4_CCA_ED_READY 0x0f, 0x10, 4
	Access parameters for sub-register IRQ_4_CCA_ED_READY in register RG_IRQ_STATUS. More...

#define	SR_IRQ_5_AMI 0x0f, 0x20, 5
	Access parameters for sub-register IRQ_5_AMI in register RG_IRQ_STATUS. More...

#define	SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
	Access parameters for sub-register IRQ_6_TRX_UR in register RG_IRQ_STATUS. More...

#define	SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
	Access parameters for sub-register IRQ_7_BAT_LOW in register RG_IRQ_STATUS. More...

#define	SR_IRQ_MASK 0x0e, 0xff, 0
	Access parameters for sub-register IRQ_MASK in register RG_IRQ_MASK. More...

#define	SR_IRQ_MASK_MODE 0x04, 0x02, 1
	Access parameters for sub-register IRQ_MASK_MODE in register RG_TRX_CTRL_1. More...

#define	SR_IRQ_POLARITY 0x04, 0x01, 0
	Access parameters for sub-register IRQ_POLARITY in register RG_TRX_CTRL_1. More...

#define	SR_MAN_ID_0 0x1e, 0xff, 0
	Access parameters for sub-register MAN_ID_0 in register RG_MAN_ID_0. More...

#define	SR_MAN_ID_1 0x1f, 0xff, 0
	Access parameters for sub-register MAN_ID_1 in register RG_MAN_ID_1. More...

#define	SR_MAX_BE 0x2f, 0xf0, 4
	Access parameters for sub-register MAX_BE in register RG_CSMA_BE. More...

#define	SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
	Access parameters for sub-register MAX_CSMA_RETRIES in register RG_XAH_CTRL_0. More...

#define	SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
	Access parameters for sub-register MAX_FRAME_RETRIES in register RG_XAH_CTRL_0. More...

#define	SR_MIN_BE 0x2f, 0x0f, 0
	Access parameters for sub-register MIN_BE in register RG_CSMA_BE. More...

#define	SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
	Access parameters for sub-register OQPSK_DATA_RATE in register RG_TRX_CTRL_2. More...

#define	SR_OQPSK_SCRAM_EN 0x0C, 0x20, 5
	Access parameters for sub-register OQPSK_SCRAM_EN in register RG_TRX_CTRL_2. More...

#define	SR_PA_BUF_LT 0x05, 0xc0, 6
	Access parameters for sub-register PA_BUF_LT in register RG_PHY_TX_PWR. More...

#define	SR_PA_EXT_EN 0x04, 0x80, 7
	Access parameters for sub-register PA_EXT_EN in register RG_TRX_CTRL_1. More...

#define	SR_PA_LT 0x05, 0x30, 4
	Access parameters for sub-register PA_LT in register RG_PHY_TX_PWR. More...

#define	SR_PAD_IO 0x03, 0xc0, 6
	Access parameters for sub-register PAD_IO in register RG_TRX_CTRL_0. More...

#define	SR_PAD_IO_CLKM 0x03, 0x30, 4
	Access parameters for sub-register PAD_IO_CLKM in register RG_TRX_CTRL_0. More...

#define	SR_PAN_ID_0 0x22, 0xff, 0
	Access parameters for sub-register PAN_ID_0 in register RG_PAN_ID_0. More...

#define	SR_PAN_ID_1 0x23, 0xff, 0
	Access parameters for sub-register PAN_ID_1 in register RG_PAN_ID_1. More...

#define	SR_PART_NUM 0x1c, 0xff, 0
	Access parameters for sub-register PART_NUM in register RG_PART_NUM. More...

#define	SR_PDT_THRES 0x0a, 0x0f, 0
	Access parameters for sub-register PDT_THRES in register RG_RX_CTRL. More...

#define	SR_PLL_CF_START 0x1a, 0x80, 7
	Access parameters for sub-register PLL_CF_START in register RG_PLL_CF. More...

#define	SR_PLL_DCU_START 0x1b, 0x80, 7
	Access parameters for sub-register PLL_DCU_START in register RG_PLL_DCU. More...

#define	SR_RND_VALUE 0x06, 0x60, 5
	Access parameters for sub-register RND_VALUE in register RG_PHY_RSSI. More...

#define	SR_RSSI 0x06, 0x1f, 0
	Access parameters for sub-register RSSI in register RG_PHY_RSSI. More...

#define	SR_RX_BL_CTRL 0x04, 0x10, 4
	Access parameters for sub-register RX_BL_CTRL in register RG_TRX_CTRL_1. More...

#define	SR_RX_CRC_VALID 0x06, 0x80, 7
	Access parameters for sub-register RX_CRC_VALID in register RG_PHY_RSSI. More...

#define	SR_RX_PDT_DIS 0x15, 0x80, 7
	Access parameters for sub-register RX_PDT_DIS in register RG_RX_SYN. More...

#define	SR_RX_PDT_LEVEL 0x15, 0x0f, 0
	Access parameters for sub-register RX_PDT_LEVEL in register RG_RX_SYN. More...

#define	SR_RX_SAFE_MODE 0x0c, 0x80, 7
	Access parameters for sub-register RX_SAFE_MODE in register RG_TRX_CTRL_2. More...

#define	SR_SFD_VALUE 0x0b, 0xff, 0
	Access parameters for sub-register SFD_VALUE in register RG_SFD_VALUE. More...

#define	SR_SHORT_ADDR_0 0x20, 0xff, 0
	Access parameters for sub-register SHORT_ADDR_0 in register RG_SHORT_ADDR_0. More...

#define	SR_SHORT_ADDR_1 0x21, 0xff, 0
	Access parameters for sub-register SHORT_ADDR_1 in register RG_SHORT_ADDR_1. More...

#define	SR_SLOTTED_OPERATION 0x2c, 0x01, 0
	Access parameters for sub-register SLOTTED_OPERATION in register RG_XAH_CTRL_0. More...

#define	SR_SPI_CMD_MODE 0x04, 0x0c, 2
	Access parameters for sub-register SPI_CMD_MODE in register RG_TRX_CTRL_1. More...

#define	SR_TRAC_STATUS 0x02, 0xe0, 5
	Access parameters for sub-register TRAC_STATUS in register RG_TRX_STATE. More...

#define	SR_TRX_CMD 0x02, 0x1f, 0
	Access parameters for sub-register TRX_CMD in register RG_TRX_STATE. More...

#define	SR_TRX_STATUS 0x01, 0x1f, 0
	Access parameters for sub-register TRX_STATUS in register RG_TRX_STATUS. More...

#define	SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
	Access parameters for sub-register TX_AUTO_CRC_ON in register RG_TRX_CTRL_1. More...

#define	SR_TX_PWR 0x05, 0x0f, 0
	Access parameters for sub-register TX_PWR in register RG_PHY_TX_PWR. More...

#define	SR_VERSION_NUM 0x1d, 0xff, 0
	Access parameters for sub-register VERSION_NUM in register RG_VERSION_NUM. More...

#define	SR_XTAL_MODE 0x12, 0xf0, 4
	Access parameters for sub-register XTAL_MODE in register RG_XOSC_CTRL. More...

#define	SR_XTAL_TRIM 0x12, 0x0f, 0
	Access parameters for sub-register XTAL_TRIM in register RG_XOSC_CTRL. More...

#define	T_OCT 32
	Duration of an octet for 250kb/s OQPSK mode in us. More...

#define	T_SYM 16
	Duration of an symbol for 250kb/s OQPSK mode in us. More...

#define	THRES_ANT_DIV_DISABLE (0x7)
	Constant THRES_ANT_DIV_DISABLED for sub-register SR_PDT_THRES in register RG_RX_CTRL. More...

#define	THRES_ANT_DIV_ENABLE (0x3)
	Constant THRES_ANT_DIV_ENABLE for sub-register SR_PDT_THRES in register RG_RX_CTRL. More...

#define	TIMESTAMPING_DISABLE (0)
	Constant TIMESTAMPING_DISABLE for sub-register SR_IRQ_2_EXT_EN in register RG_TRX_CTRL_1. More...

#define	TIMESTAMPING_ENABLE (1)
	Constant TIMESTAMPING_ENABLE for sub-register SR_IRQ_2_EXT_EN in register RG_TRX_CTRL_1. More...

#define	TRANSCEIVER_NAME "AT86RF231"

#define	TRX_IRQ_DELAY_US (9) /* TRX Parameter: tIRQ */

#define	TRX_OFF_TO_PLL_ON_TIME_US (110) /* TRX Parameter: tTR4 */

#define	TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES (35) /* TRX Parameter: tTR3 */

#define	TRX_SUPPORTED_CHANNELS (0x07FFF800)

#define	TX_AUTO_CRC_DISABLE (0)
	Constant TX_AUTO_CRC_ENABLE for sub-register TX_AUTO_CRC_ON in register RG_TRX_CTRL_1. More...

#define	TX_AUTO_CRC_ENABLE (1)
	Constant TX_AUTO_CRC_ENABLE for sub-register TX_AUTO_CRC_ON in register RG_TRX_CTRL_1. More...

#define	TX_PWR_TOLERANCE (0x80)
	Tolerance of the phyTransmitPower PIB attribute. More...

#define	UPLD_RES_FT_DISABLE (0)
	Constant UPLD_RES_FT_DISBALE for sub-register AACK_UPLD_RES_FT in register RG_XAH_CTRL_1. More...

#define	UPLD_RES_FT_ENABLE (1)
	Constant UPLD_RES_FT_DISBALE for sub-register AACK_UPLD_RES_FT in register RG_XAH_CTRL_1. More...

Typedefs
typedef enum tal_trx_status_tag	tal_trx_status_t
	Transceiver states. More...

typedef enum trx_cmd_tag	trx_cmd_t
	Transceiver commands. More...

typedef enum trx_irq_reason_tag	trx_irq_reason_t
	Transceiver interrupt reasons. More...

typedef enum trx_trac_status_tag	trx_trac_status_t
	Transceiver's trac status. More...

Enumerations
enum	tal_trx_status_tag { P_ON = (0), BUSY_RX = (1), BUSY_TX = (2), RX_ON = (6), TRX_OFF = (8), PLL_ON = (9), TRX_SLEEP = (15), BUSY_RX_AACK = (17), BUSY_TX_ARET = (18), RX_AACK_ON = (22), TX_ARET_ON = (25), RX_ON_NOCLK = (28), RX_AACK_ON_NOCLK = (29), BUSY_RX_AACK_NOCLK = (30), STATE_TRANSITION_IN_PROGRESS = (31), P_ON = (0x00), TRX_OFF = (0x08), PLL_ON = (0x09), TRX_SLEEP = (0x0F), RX_ON = (0x16), P_ON = (0x00), BUSY_RX = (0x01), BUSY_TX = (0x02), RX_ON = (0x06), TRX_OFF = (0x08), PLL_ON = (0x09), TRX_SLEEP = (0x0F), BUSY_RX_AACK = (0x11), BUSY_TX_ARET = (0x12), RX_AACK_ON = (0x16), TX_ARET_ON = (0x19), RX_ON_NOCLK = (0x1C), RX_AACK_ON_NOCLK = (0x1D), BUSY_RX_AACK_NOCLK = (0x1E), STATE_TRANSITION_IN_PROGRESS = (0x1F), P_ON = (0x00), BUSY_RX = (0x01), BUSY_TX = (0x02), RX_ON = (0x06), TRX_OFF = (0x08), PLL_ON = (0x09), TRX_SLEEP = (0x0F), BUSY_RX_AACK = (0x11), BUSY_TX_ARET = (0x12), RX_AACK_ON = (0x16), TX_ARET_ON = (0x19), RX_ON_NOCLK = (0x1C), RX_AACK_ON_NOCLK = (0x1D), BUSY_RX_AACK_NOCLK = (0x1E), STATE_TRANSITION_IN_PROGRESS = (0x1F), P_ON = (0x00), BUSY_RX = (0x01), BUSY_TX = (0x02), RX_ON = (0x06), TRX_OFF = (0x08), PLL_ON = (0x09), TRX_SLEEP = (0x0F), PREP_DEEP_SLEEP = (0x10), BUSY_RX_AACK = (0x11), BUSY_TX_ARET = (0x12), RX_AACK_ON = (0x16), TX_ARET_ON = (0x19), STATE_TRANSITION_IN_PROGRESS = (0x1F), TRX_DEEP_SLEEP = (0x20), P_ON = (0x00), BUSY_RX = (0x01), BUSY_TX = (0x02), RX_ON = (0x06), TRX_OFF = (0x08), PLL_ON = (0x09), TRX_SLEEP = (0x0F), BUSY_RX_AACK = (0x11), BUSY_TX_ARET = (0x12), RX_AACK_ON = (0x16), TX_ARET_ON = (0x19), STATE_TRANSITION_IN_PROGRESS = (0x1F) }
	Transceiver states. More...

enum	trx_cmd_tag { CMD_NOP = (0), CMD_TX_START = (2), CMD_FORCE_TRX_OFF = (3), CMD_FORCE_PLL_ON = (4), CMD_RX_ON = (6), CMD_TRX_OFF = (8), CMD_PLL_ON = (9), CMD_SLEEP = (15), CMD_RX_AACK_ON = (22), CMD_TX_ARET_ON = (25), CMD_NOP = (0x00), CMD_TX_START = (0x02), CMD_FORCE_TRX_OFF = (0x03), CMD_FORCE_PLL_ON = (0x04), CMD_RX_ON = (0x06), CMD_TRX_OFF = (0x08), CMD_PLL_ON = (0x09), CMD_RX_AACK_ON = (0x16), CMD_TX_ARET_ON = (0x19), CMD_SLEEP = (0x0F), CMD_NOP = (0x00), CMD_TX_START = (0x02), CMD_FORCE_TRX_OFF = (0x03), CMD_FORCE_PLL_ON = (0x04), CMD_RX_ON = (0x06), CMD_TRX_OFF = (0x08), CMD_PLL_ON = (0x09), CMD_RX_AACK_ON = (0x16), CMD_TX_ARET_ON = (0x19), CMD_SLEEP = (0x0F), CMD_NOP = (0x00), CMD_TX_START = (0x02), CMD_FORCE_TRX_OFF = (0x03), CMD_FORCE_PLL_ON = (0x04), CMD_RX_ON = (0x06), CMD_TRX_OFF = (0x08), CMD_PLL_ON = (0x09), CMD_PREP_DEEP_SLEEP = (0x10), CMD_RX_AACK_ON = (0x16), CMD_TX_ARET_ON = (0x19), CMD_SLEEP = (0x0F), CMD_DEEP_SLEEP = (0x20), CMD_NOP = (0x00), CMD_TX_START = (0x02), CMD_FORCE_TRX_OFF = (0x03), CMD_FORCE_PLL_ON = (0x04), CMD_RX_ON = (0x06), CMD_TRX_OFF = (0x08), CMD_PLL_ON = (0x09), CMD_RX_AACK_ON = (0x16), CMD_TX_ARET_ON = (0x19), CMD_SLEEP = (0x0F) }
	Transceiver commands. More...

enum	trx_irq_reason_tag { TRX_NO_IRQ = (0x00), TRX_IRQ_PLL_LOCK = (0x01), TRX_IRQ_PLL_UNLOCK = (0x02), TRX_IRQ_RX_START = (0x04), TRX_IRQ_TRX_END = (0x08), TRX_IRQ_CCA_ED_READY = (0x10), TRX_IRQ_AMI = (0x20), TRX_IRQ_TRX_UR = (0x40), TRX_IRQ_BAT_LOW = (0x80), TRX_IRQ_7_BAT_LOW = (0x80), TRX_IRQ_6_TRX_UR = (0x40), TRX_IRQ_5_AMI = (0x20), TRX_IRQ_4_CCA_ED_DONE = (0x10), TRX_IRQ_3_TRX_END = (0x08), TRX_IRQ_2_RX_START = (0x04), TRX_IRQ_1_PLL_UNLOCK = (0x02), TRX_IRQ_0_PLL_LOCK = (0x01), TRX_NO_IRQ = (0x00), TRX_IRQ_7_BAT_LOW = (0x80), TRX_IRQ_6_TRX_UR = (0x40), TRX_IRQ_5_AMI = (0x20), TRX_IRQ_4_CCA_ED_DONE = (0x10), TRX_IRQ_3_TRX_END = (0x08), TRX_IRQ_2_RX_START = (0x04), TRX_IRQ_1_PLL_UNLOCK = (0x02), TRX_IRQ_0_PLL_LOCK = (0x01), TRX_NO_IRQ = (0x00), TRX_IRQ_7_BAT_LOW = (0x80), TRX_IRQ_6_TRX_UR = (0x40), TRX_IRQ_5_AMI = (0x20), TRX_IRQ_4_CCA_ED_DONE = (0x10), TRX_IRQ_3_TRX_END = (0x08), TRX_IRQ_2_RX_START = (0x04), TRX_IRQ_1_PLL_UNLOCK = (0x02), TRX_IRQ_0_PLL_LOCK = (0x01), TRX_NO_IRQ = (0x00), TRX_IRQ_7_BAT_LOW = (0x80), TRX_IRQ_6_TRX_UR = (0x40), TRX_IRQ_5_AMI = (0x20), TRX_IRQ_4_CCA_ED_DONE = (0x10), TRX_IRQ_3_TRX_END = (0x08), TRX_IRQ_2_RX_START = (0x04), TRX_IRQ_1_PLL_UNLOCK = (0x02), TRX_IRQ_0_PLL_LOCK = (0x01), TRX_NO_IRQ = (0x00) }
	Transceiver interrupt reasons. More...

enum	trx_trac_status_tag { TRAC_SUCCESS = 0, TRAC_SUCCESS_DATA_PENDING = 1, TRAC_WAIT_FOR_ACK = 2, TRAC_CHANNEL_ACCESS_FAILURE = 3, TRAC_NO_ACK = 5, TRAC_INVALID = 7, TRAC_SUCCESS = (0), TRAC_SUCCESS_DATA_PENDING = (1), TRAC_SUCCESS_WAIT_FOR_ACK = (2), TRAC_CHANNEL_ACCESS_FAILURE = (3), TRAC_NO_ACK = (5), TRAC_INVALID = (7), TRAC_SUCCESS = (0x00), TRAC_SUCCESS_DATA_PENDING = (0x01), TRAC_SUCCESS_WAIT_FOR_ACK = (0x02), TRAC_CHANNEL_ACCESS_FAILURE = (0x03), TRAC_NO_ACK = (0x05), TRAC_INVALID = (0x07), TRAC_SUCCESS = (0), TRAC_SUCCESS_DATA_PENDING = (1), TRAC_SUCCESS_WAIT_FOR_ACK = (2), TRAC_CHANNEL_ACCESS_FAILURE = (3), TRAC_NO_ACK = (5), TRAC_INVALID = (7), TRAC_SUCCESS = (0), TRAC_SUCCESS_DATA_PENDING = (1), TRAC_SUCCESS_WAIT_FOR_ACK = (2), TRAC_CHANNEL_ACCESS_FAILURE = (3), TRAC_NO_ACK = (5), TRAC_INVALID = (7) }
	Transceiver's trac status. More...

#define AACK_ACK_TIME_12_SYMBOLS (0)

Constants.

Constant AACK_ACK_TIME_12_symbols for sub-register SR_AACK_ACK_TIME

#define AACK_ACK_TIME_2_SYMBOLS (1)

Constant AACK_ACK_TIME_2_symbols for sub-register SR_AACK_ACK_TIME.

#define ACK_DISABLE (1)

Constant ACK_DISABLE for sub-register AACK_DIS_ACK in register RG_CSMA_SEED_1.

#define ACK_ENABLE (0)

Constant ACK_ENABLE for sub-register AACK_DIS_ACK in register RG_CSMA_SEED_1.

#define AES_BASE_ADDR (0x80)

Register addresses.

Base address for Transceiver AES address space

Referenced by sal_aes_read(), sal_aes_restart(), sal_aes_setup(), and sal_aes_wrrd().

#define AES_DIR_DECRYPT (1)

AES core operation direction: Decryption (ECB)

Referenced by sal_aes_setup().

#define AES_DIR_ENCRYPT (0)

AES core operation direction: Encryption (ECB, CBC)

Referenced by compute_mic(), encrypt_pldmic(), PHY_EncryptReq(), sal_aes_restart(), sal_aes_setup(), and stb_ccm_secure().

#define AES_DONE (1)

AES core operation status: AES module finished.

#define AES_MODE_CBC (2)

Set CBC mode.

Referenced by compute_mic(), and sal_aes_setup().

#define AES_MODE_ECB (0)

Set ECB mode.

Referenced by compute_mic(), encrypt_pldmic(), PHY_EncryptReq(), sal_aes_setup(), and stb_ccm_secure().

#define AES_MODE_KEY (1)

Set key mode.

Referenced by sal_aes_restart(), and sal_aes_setup().

#define AES_NOT_DONE (0)

AES core operation status: AES module did not finish.

#define AES_REQUEST (1)

Initiate an AES operation.

Referenced by sal_aes_setup().

#define ALTRATE_1MBPS (2)

Constant ALTRATE_1Mbps for sub-register SR_OQPSK_DATA_RATE.

#define ALTRATE_250KBPS (0)

Constant ALTRATE_250kbps for sub-register SR_OQPSK_DATA_RATE.

#define ALTRATE_2MBPS (3)

Constant ALTRATE_2Mbps for sub-register SR_OQPSK_DATA_RATE.

#define ALTRATE_500KBPS (1)

Constant ALTRATE_500kbps for sub-register SR_OQPSK_DATA_RATE.

#define ANT_CTRL_0 (0)

Constant ANT_CTRL_0 for sub-register SR_ANT_CTRL in register RG_ANT_DIV.

Referenced by config_rpc_mode(), and per_mode_initiator_rx_cb().

#define ANT_CTRL_1 (1)

Constant ANT_CTRL_1 for sub-register SR_ANT_CTRL in register RG_ANT_DIV.

Referenced by config_rpc_mode(), init_state_init(), per_mode_initiator_rx_cb(), per_mode_receptor_rx_cb(), and trx_irq_handler_cb().

#define ANT_CTRL_2 (2)

Constant ANT_CTRL_2 for sub-register SR_ANT_CTRL in register RG_ANT_DIV.

Referenced by per_mode_initiator_rx_cb(), per_mode_receptor_rx_cb(), and trx_irq_handler_cb().

#define ANT_CTRL_3 (3)

Constant ANT_CTRL_3 for sub-register SR_ANT_CTRL in register RG_ANT_DIV.

#define ANT_DIV_DISABLE (0)

Constant ANT_DIV_disable for sub-register SR_ANT_DIV_EN.

#define ANT_DIV_ENABLE (1)

Constant ANT_DIV_enable for sub-register SR_ANT_DIV_EN.

Referenced by trx_config().

#define ANT_EXT_SW_DISABLE (0)

Constant ANT_EXT_SW_DISABLE for sub-register SR_ANT_EXT_SW_EN.

Referenced by set_trx_state().

#define ANT_EXT_SW_ENABLE (1)

Constant ANT_EXT_SW_ENABLE for sub-register SR_ANT_EXT_SW_EN.

Referenced by set_trx_state(), and trx_config().

#define ANT_SEL_ANTENNA_0 (0)

Constant ANT_SEL_antenna_0 for sub-register SR_ANT_SEL.

Referenced by trx_irq_handler_cb().

#define ANT_SEL_ANTENNA_1 (1)

Constant ANT_SEL_antenna_1 for sub-register SR_ANT_SEL.

#define AT86RF231_PART_NUM (3)

Constant RF231 for sub-register SR_PART_NUM.

Referenced by trx_init().

#define AT86RF231_VERSION_NUM (2)

Constant RF231 for sub-register SR_VERSION_NUM.

Referenced by trx_init().

#define BATMON_ABOVE_THRES (1)

Constant BATMON_ABOVE_THRES for sub-register SR_BATMON_OK.

Referenced by tfa_get_batmon_voltage().

#define BATMON_BELOW_THRES (0)

Constant BATMON_BELOW_THRES for sub-register SR_BATMON_OK.

Referenced by tfa_get_batmon_voltage().

#define BATMON_HIGH_RANGE (1)

Constant BATMON_HIGH_RANGE for sub-register BATMON_HR in register RG_BATMON.

Referenced by tfa_get_batmon_voltage().

#define BATMON_LOW_RANGE (0)

Constant BATMON_LOW_RANGE for sub-register BATMON_HR in register RG_BATMON.

Referenced by tfa_get_batmon_voltage().

#define CCA_DETECTION_DONE (1)

Constant CCA_calculation_done for sub-register SR_CCA_DONE.

Referenced by perform_cca_twice(), and tfa_cca_perform().

#define CCA_DETECTION_NOT_DONE (0)

Constant CCA_calculation_not_finished for sub-register SR_CCA_DONE.

#define CCA_DETECTION_TIME_SYM (8)

#define CCA_DURATION_SYM

Value:

(CCA_DETECTION_TIME_SYM + \

CCA_PROCESS_TIME_SYM)

CCA_PROCESS_TIME_SYM

#define CCA_PROCESS_TIME_SYM

Definition: avr2025_mac/source/tal/at86rf231/inc/at86rf231.h:92

CCA_DETECTION_TIME_SYM

#define CCA_DETECTION_TIME_SYM

Definition: avr2025_mac/source/tal/at86rf231/inc/at86rf231.h:91

Referenced by perform_cca_twice(), and tfa_cca_perform().

#define CCA_MODE_0 (0)

Constant CCA_Mode_0 for sub-register SR_CCA_MODE.

#define CCA_MODE_1 (1)

Constant CCA_Mode_1 for sub-register SR_CCA_MODE.

#define CCA_MODE_2 (2)

Constant CCA_Mode_2 for sub-register SR_CCA_MODE.

#define CCA_MODE_3 (3)

Constant CCA_Mode_3 for sub-register SR_CCA_MODE.

#define CCA_PRE_START_DURATION_US (20)

Referenced by perform_cca_twice().

#define CCA_PREPARATION_DURATION_US (50)

Referenced by csma_backoff_calculation(), and perform_cca_twice().

#define CCA_PROCESS_TIME_SYM (1)

#define CCA_START (1)

Constant CCA_START for sub-register CCA_REQUEST in register RG_PHY_CC_CCA.

Referenced by perform_cca_twice(), and tfa_cca_perform().

#define CCA_STATUS_CHANNEL_IS_BUSY (0)

Constant CCA_STATUS_channel_is_busy for sub-register SR_CCA_STATUS.

#define CCA_STATUS_CHANNEL_IS_IDLE (1)

Constant CCA_STATUS_channel_is_idle for sub-register SR_CCA_STATUS.

Referenced by perform_cca_twice(), and tfa_cca_perform().

#define CLKM_16MHZ (5)

Constant CLKM_16MHz for sub-register SR_CLKM_CTRL.

#define CLKM_1_16MHZ (7)

Constant CLKM_1_16MHz for sub-register SR_CLKM_CTRL.

#define CLKM_1_4MHZ (6)

Constant CLKM_1_4MHz for sub-register SR_CLKM_CTRL.

#define CLKM_1MHZ (1)

Constant CLKM_1MHz for sub-register SR_CLKM_CTRL.

Referenced by trx_config(), and trx_init().

#define CLKM_2MHZ (2)

Constant CLKM_2MHz for sub-register SR_CLKM_CTRL.

#define CLKM_4MHZ (3)

Constant CLKM_4MHz for sub-register SR_CLKM_CTRL.

#define CLKM_8MHZ (4)

Constant CLKM_8MHz for sub-register SR_CLKM_CTRL.

#define CLKM_NO_CLOCK (0)

Constant CLKM_no_clock for sub-register SR_CLKM_CTRL.

#define CLKM_SHA_DISABLE (0)

Constant CLKM_SHA_disable for sub-register SR_CLKM_SHA_SEL.

Referenced by trx_config().

#define CLKM_SHA_ENABLE (1)

Constant CLKM_SHA_enable for sub-register SR_CLKM_SHA_SEL.

#define CRC16_NOT_VALID (0)

Constant CRC16_not_valid for sub-register SR_RX_CRC_VALID.

Referenced by handle_received_frame_irq().

#define CRC16_VALID (1)

Constant CRC16_valid for sub-register SR_RX_CRC_VALID.

#define CSMA_PROCESSING_TIME_US (100)

#define FRAME_VERSION_0 (0)

Constant FRAME_VERSION_0 for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1.

#define FRAME_VERSION_01 (1)

Constant FRAME_VERSION_01 for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1.

Referenced by trx_config().

#define FRAME_VERSION_012 (2)

Constant FRAME_VERSION_012 for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1.

#define FRAME_VERSION_IGNORED (3)

Constant FRAME_VERSION_IGNORED for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1.

#define IRQ_MASK_MODE_OFF (0)

Constant IRQ_MASK_MODE_off for sub-register SR_IRQ_MASK_MODE.

#define IRQ_MASK_MODE_ON (1)

Constant IRQ_MASK_MODE_on for sub-register SR_IRQ_MASK_MODE.

Referenced by trx_config().

#define IRQ_POL_HIGH_ACTIVE_IRQ (0)

Constant IRQ_POL_high_active_IRQ for sub-register SR_IRQ_POLARITY.

#define IRQ_POL_LOW_ACTIVE_IRQ (1)

Constant IRQ_POL_low_active_IRQ for sub-register SR_IRQ_POLARITY.

#define IRQ_PROCESSING_DLY_US (32)

Referenced by send_frame(), and tx_done_handling().

#define OQPSK_SCRAM_DISABLE (0)

Constant OQPSK_SCRAM_DISABLE for sub-register OQPSK_SCRAM_EN in register RG_TRX_CTRL_2.

#define OQPSK_SCRAM_ENABLE (1)

Constant OQPSK_SCRAM_ENABLE for sub-register OQPSK_SCRAM_EN in register RG_TRX_CTRL_2.

#define P_ON_TO_CLKM_AVAILABLE_MAX_US

Value:

(1000) /* TRX Parameter: tTR1 max.

* value */

#define P_ON_TO_CLKM_AVAILABLE_TYP_US

Value:

(330) /* TRX Parameter: tTR1

* typical value */

Referenced by trx_init().

#define PA_BUF_LT_0_US (0)

Constant PA_BUF_LT_0s for sub-register SR_PA_BUF_LT.

#define PA_BUF_LT_2_US (1)

Constant PA_BUF_LT_2s for sub-register SR_PA_BUF_LT.

#define PA_BUF_LT_4_US (2)

Constant PA_BUF_LT_4s for sub-register SR_PA_BUF_LT.

#define PA_BUF_LT_6_US (3)

Constant PA_BUF_LT_6s for sub-register SR_PA_BUF_LT.

#define PA_EXT_DISABLE (0)

Constant PA_EXT_disable for sub-register SR_PA_EXT_EN.

Referenced by peer_search_initiator_init(), peer_search_receptor_init(), and set_trx_state().

#define PA_EXT_ENABLE (1)

Constant PA_EXT_enable for sub-register SR_PA_EXT_EN.

Referenced by per_mode_initiator_init(), per_mode_receptor_init(), set_trx_state(), and trx_config().

#define PA_LT_2_US (0)

Constant PA_LT_2s for sub-register SR_PA_LT.

#define PA_LT_4_US (1)

Constant PA_LT_4s for sub-register SR_PA_LT.

#define PA_LT_6_US (2)

Constant PA_LT_6s for sub-register SR_PA_LT.

#define PA_LT_8_US (3)

Constant PA_LT_8s for sub-register SR_PA_LT.

#define PAD_CLKM_2_MA (0)

Constant PAD_CLKM_2mA for sub-register SR_PAD_IO_CLKM.

Referenced by trx_config().

#define PAD_CLKM_4_MA (1)

Constant PAD_CLKM_4mA for sub-register SR_PAD_IO_CLKM.

#define PAD_CLKM_6_MA (2)

Constant PAD_CLKM_6mA for sub-register SR_PAD_IO_CLKM.

#define PAD_CLKM_8_MA (3)

Constant PAD_CLKM_8mA for sub-register SR_PAD_IO_CLKM.

#define PAD_IO_2_MA (0)

Constant PAD_IO_2mA for sub-register SR_PAD_IO.

#define PAD_IO_4_MA (1)

Constant PAD_IO_4mA for sub-register SR_PAD_IO.

#define PAD_IO_6_MA (2)

Constant PAD_IO_6mA for sub-register SR_PAD_IO.

#define PAD_IO_8_MA (3)

Constant PAD_IO_8mA for sub-register SR_PAD_IO.

#define PD_ACK_BIT_SET_DISABLE (0)

Constant PD_ACK_BIT_SET_DISABLE for sub-register AACK_SET_PD in register RG_CSMA_SEED_1.

#define PD_ACK_BIT_SET_ENABLE (1)

Constant PD_ACK_BIT_SET_ENABLE for sub-register AACK_SET_PD in register RG_CSMA_SEED_1.

Referenced by trx_config().

#define PRE_TX_DURATION_US (32)

Referenced by send_frame(), and send_frame_at_next_backoff_boundary().

#define PROM_MODE_DISABLE (0)

Constant PROM_MODE_DISABLE for sub-register AACK_PROM_MODE in register RG_XAH_CTRL_1.

#define PROM_MODE_ENABLE (1)

Constant PROM_MODE_ENABLE for sub-register AACK_PROM_MODE in register RG_XAH_CTRL_1.

#define RF231_RAM_SIZE (0x80)

RF231 FIFO size.

#define RG_AES_CTRL (0x03)

Offset for register AES_CTRL.

Referenced by sal_aes_restart(), sal_aes_setup(), and sal_aes_wrrd().

#define RG_AES_CTRL_MIRROR (0x94)

mirrored version of AES_CTRL, SRAM address

#define RG_AES_STATE_KEY_0 (0x04)

Offset for register AES_STATE_KEY_0.

Referenced by sal_aes_read(), sal_aes_setup(), and sal_aes_wrrd().

#define RG_AES_STATUS (0x02)

Offset for register AES_STATUS.

#define RG_ANT_DIV (0x0d)

Offset for register ANT_DIV.

#define RG_BATMON (0x11)

Offset for register BATMON.

#define RG_CCA_THRES (0x09)

Offset for register CCA_THRES.

#define RG_CSMA_BE (0x2f)

Offset for register CSMA_BE.

#define RG_CSMA_SEED_0 (0x2d)

Offset for register CSMA_SEED_0.

Referenced by set_trx_state(), and trx_config().

#define RG_CSMA_SEED_1 (0x2e)

Offset for register CSMA_SEED_1.

#define RG_FTN_CTRL (0x18)

Offset for register FTN_CTRL.

#define RG_IEEE_ADDR_0 (0x24)

Offset for register IEEE_ADDR_0.

Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().

#define RG_IEEE_ADDR_1 (0x25)

Offset for register IEEE_ADDR_1.

#define RG_IEEE_ADDR_2 (0x26)

Offset for register IEEE_ADDR_2.

#define RG_IEEE_ADDR_3 (0x27)

Offset for register IEEE_ADDR_3.

#define RG_IEEE_ADDR_4 (0x28)

Offset for register IEEE_ADDR_4.

#define RG_IEEE_ADDR_5 (0x29)

Offset for register IEEE_ADDR_5.

#define RG_IEEE_ADDR_6 (0x2a)

Offset for register IEEE_ADDR_6.

#define RG_IEEE_ADDR_7 (0x2b)

Offset for register IEEE_ADDR_7.

#define RG_IRQ_MASK (0x0e)

Offset for register IRQ_MASK.

Referenced by set_trx_state(), switch_pll_on(), trx_config(), and trx_init().

#define RG_IRQ_STATUS (0x0f)

Offset for register IRQ_STATUS.

Referenced by perform_cca_twice(), set_trx_state(), switch_pll_on(), tal_generate_rand_seed(), tfa_ed_sample(), tfa_get_batmon_voltage(), trx_irq_awake_handler_cb(), and trx_irq_handler_cb().

#define RG_MAN_ID_0 (0x1e)

Offset for register MAN_ID_0.

#define RG_MAN_ID_1 (0x1f)

Offset for register MAN_ID_1.

#define RG_PAN_ID_0 (0x22)

Offset for register PAN_ID_0.

Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().

#define RG_PAN_ID_1 (0x23)

Offset for register PAN_ID_1.

#define RG_PART_NUM (0x1c)

Offset for register PART_NUM.

Referenced by tfa_continuous_tx_start(), and trx_init().

#define RG_PHY_CC_CCA (0x08)

Offset for register PHY_CC_CCA.

#define RG_PHY_ED_LEVEL (0x07)

Offset for register PHY_ED_LEVEL.

Referenced by handle_received_frame_irq(), and tfa_ed_sample().

#define RG_PHY_RSSI (0x06)

Offset for register PHY_RSSI.

#define RG_PHY_TX_PWR (0x05)

Offset for register PHY_TX_PWR.

Referenced by set_default_tx_pwr(), tal_pib_set(), and write_all_tal_pib_to_trx().

#define RG_PLL_CF (0x1a)

Offset for register PLL_CF.

Referenced by switch_pll_on().

#define RG_PLL_DCU (0x1b)

Offset for register PLL_DCU.

#define RG_RX_CTRL (0x0a)

Offset for register RX_CTRL.

Referenced by tfa_continuous_tx_start().

#define RG_RX_SYN (0x15)

Offset for register RX_SYN.

#define RG_SFD_VALUE (0x0b)

Offset for register SFD_VALUE.

#define RG_SHORT_ADDR_0 (0x20)

Offset for register SHORT_ADDR_0.

Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().

#define RG_SHORT_ADDR_1 (0x21)

Offset for register SHORT_ADDR_1.

#define RG_TRX_CTRL_0 (0x03)

Offset for register TRX_CTRL_0.

#define RG_TRX_CTRL_1 (0x04)

Offset for register TRX_CTRL_1.

#define RG_TRX_CTRL_2 (0x0c)

Offset for register TRX_CTRL_2.

Referenced by config_per_test_parameters(), config_rpc_mode(), and tfa_continuous_tx_start().

#define RG_TRX_STATE (0x02)

Offset for register TRX_STATE.

Referenced by set_trx_state(), switch_pll_on(), tfa_continuous_tx_start(), and trx_init().

#define RG_TRX_STATUS (0x01)

Offset for register TRX_STATUS.

Referenced by set_trx_state().

#define RG_VERSION_NUM (0x1d)

Offset for register VERSION_NUM.

Referenced by trx_init().

#define RG_VREG_CTRL (0x10)

Offset for register VREG_CTRL.

#define RG_XAH_CTRL_0 (0x2c)

Offset for register XAH_CTRL_0.

#define RG_XAH_CTRL_1 (0x17)

Offset for register XAH_CTRL_1.

#define RG_XOSC_CTRL (0x12)

Offset for register XOSC_CTRL.

#define RSSI_BASE_VAL_DBM (-91)

Minimum RSSI sensitivity value in dBm, which is equivalent to the value 0 in sub register SR_RSSI.

Referenced by per_mode_initiator_ed_end_cb(), tal_get_rssi_base_val(), and tfa_pib_set().

#define RST_PULSE_WIDTH_US (10)

Referenced by trx_init(), and trx_reset().

#define RX_DISABLE (1)

Constant RX_DISABLE for sub-register RX_PDT_DIS.

Referenced by perform_cca_twice(), tfa_cca_perform(), and tfa_ed_sample().

#define RX_ENABLE (0)

Constant RX_ENABLE for sub-register RX_PDT_DIS.

Referenced by perform_cca_twice(), tal_generate_rand_seed(), tfa_cca_perform(), and tfa_ed_sample().

#define RX_SAFE_MODE_DISABLE (0)

Constant RX_SAFE_MODE_DISABLE for sub-register RX_SAFE_MODE in register RG_TRX_CTRL_2.

#define RX_SAFE_MODE_ENABLE (1)

Constant RX_SAFE_MODE_ENABLE for sub-register RX_SAFE_MODE in register RG_TRX_CTRL_2.

Referenced by trx_config().

#define SLEEP_TO_TRX_OFF_MAX_US

Value:

(1000) /* TRX Parameter: tTR2 max.

* value */

#define SLEEP_TO_TRX_OFF_TYP_US

Value:

(380) /* TRX Parameter: tTR2

* typical value */

Referenced by csma_backoff_calculation(), perform_cca_twice(), and trx_reset().

#define SPI_CMD_MODE_DEFAULT (0)

Constant SPI_CMD_MODE_default for sub-register SR_SPI_CMD_MODE.

#define SPI_CMD_MODE_MONITOR_IRQ_STATUS (3)

Constant SPI_CMD_MODE_monitor_IRQ_STATUS for sub-register SR_SPI_CMD_MODE.

#define SPI_CMD_MODE_MONITOR_PHY_RSSI (2)

Constant SPI_CMD_MODE_monitor_PHY_RSSI for sub-register SR_SPI_CMD_MODE.

#define SPI_CMD_MODE_MONITOR_TRX_STATUS (1)

Constant SPI_CMD_MODE_monitor_TRX_STATUS for sub-register SR_SPI_CMD_MODE.

#define SR_AACK_ACK_TIME 0x17, 0x04, 2

Subregister access.

Access parameters for sub-register AACK_ACK_TIME in register RG_XAH_CTRL_1

Referenced by apply_channel_page_configuration().

#define SR_AACK_DIS_ACK 0x2e, 0x10, 4

Access parameters for sub-register AACK_DIS_ACK in register RG_CSMA_SEED_1.

#define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5

Access parameters for sub-register AACK_FLTR_RES_FT in register RG_XAH_CTRL_1.

#define SR_AACK_FVN_MODE 0x2e, 0xc0, 6

Access parameters for sub-register AACK_FVN_MODE in register RG_CSMA_SEED_1.

Referenced by trx_config().

#define SR_AACK_I_AM_COORD 0x2e, 0x08, 3

Access parameters for sub-register AACK_I_AM_COORD in register RG_CSMA_SEED_1.

Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().

#define SR_AACK_PROM_MODE 0x17, 0x02, 1

Access parameters for sub-register AACK_PROM_MODE in register RG_XAH_CTRL_1.

Referenced by tal_get_curr_trx_config().

#define SR_AACK_SET_PD 0x2e, 0x20, 5

Access parameters for sub-register AACK_SET_PD in register RG_CSMA_SEED_1.

Referenced by trx_config().

#define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4

Access parameters for sub-register AACK_UPLD_RES_FT in register RG_XAH_CTRL_1.

#define SR_AES_DIR 0x03, 0x08, 3

Access parameters for sub-register AES_DIR in register RG_AES_CTRL.

Referenced by sal_aes_setup().

#define SR_AES_MODE 0x03, 0x70, 4

Access parameters for sub-register AES_MODE in register RG_AES_CTRL.

Referenced by sal_aes_restart(), and sal_aes_setup().

#define SR_AES_REQUEST 0x03, 0x80, 7

Access parameters for sub-register AES_REQUEST in register RG_AES_CTRL.

Referenced by sal_aes_setup().

#define SR_ANT_CTRL 0x0d, 0x03, 0

Access parameters for sub-register ANT_CTRL in register RG_ANT_DIV.

Referenced by tal_get_curr_trx_config(), trx_config(), and trx_irq_handler_cb().

#define SR_ANT_DIV_EN 0x0d, 0x08, 3

Access parameters for sub-register ANT_DIV_EN in register RG_ANT_DIV.

Referenced by tal_get_curr_trx_config(), and trx_config().

#define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2

Access parameters for sub-register ANT_EXT_SW_EN in register RG_ANT_DIV.

Referenced by set_trx_state(), and trx_config().

#define SR_ANT_SEL 0x0d, 0x80, 7

Access parameters for sub-register ANT_SEL in register RG_ANT_DIV.

Referenced by tal_get_curr_trx_config(), and trx_irq_handler_cb().

#define SR_AVDD_OK 0x10, 0x40, 6

Access parameters for sub-register AVDD_OK in register RG_VREG_CTRL.

#define SR_AVREG_EXT 0x10, 0x80, 7

Access parameters for sub-register AVREG_EXT in register RG_VREG_CTRL.

#define SR_BATMON_HR 0x11, 0x10, 4

Access parameters for sub-register BATMON_HR in register RG_BATMON.

Referenced by tfa_get_batmon_voltage().

#define SR_BATMON_OK 0x11, 0x20, 5

Access parameters for sub-register BATMON_OK in register RG_BATMON.

Referenced by tfa_get_batmon_voltage().

#define SR_BATMON_VTH 0x11, 0x0f, 0

Access parameters for sub-register BATMON_VTH in register RG_BATMON.

Referenced by tfa_get_batmon_voltage().

#define SR_CCA_DONE 0x01, 0x80, 7

Access parameters for sub-register CCA_DONE in register RG_TRX_STATUS.

Referenced by perform_cca_twice(), and tfa_cca_perform().

#define SR_CCA_ED_THRES 0x09, 0x0f, 0

Access parameters for sub-register CCA_ED_THRES in register RG_CCA_THRES.

Referenced by trx_config().

#define SR_CCA_MODE 0x08, 0x60, 5

Access parameters for sub-register CCA_MODE in register RG_PHY_CC_CCA.

Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().

#define SR_CCA_REQUEST 0x08, 0x80, 7

Access parameters for sub-register CCA_REQUEST in register RG_PHY_CC_CCA.

Referenced by perform_cca_twice(), and tfa_cca_perform().

#define SR_CCA_STATUS 0x01, 0x40, 6

Access parameters for sub-register CCA_STATUS in register RG_TRX_STATUS.

Referenced by perform_cca_twice(), and tfa_cca_perform().

#define SR_CHANNEL 0x08, 0x1f, 0

Access parameters for sub-register CHANNEL in register RG_PHY_CC_CCA.

Referenced by apply_channel_page_configuration(), tal_pib_set(), and write_all_tal_pib_to_trx().

#define SR_CLKM_CTRL 0x03, 0x07, 0

Access parameters for sub-register CLKM_CTRL in register RG_TRX_CTRL_0.

Referenced by trx_config(), and trx_init().

#define SR_CLKM_SHA_SEL 0x03, 0x08, 3

Access parameters for sub-register CLKM_SHA_SEL in register RG_TRX_CTRL_0.

Referenced by trx_config().

#define SR_CSMA_SEED_0 0x2d, 0xff, 0

Access parameters for sub-register CSMA_SEED_0 in register RG_CSMA_SEED_0.

#define SR_CSMA_SEED_1 0x2e, 0x07, 0

Access parameters for sub-register CSMA_SEED_1 in register RG_CSMA_SEED_1.

Referenced by set_trx_state(), and trx_config().

#define SR_DVDD_OK 0x10, 0x04, 2

Access parameters for sub-register DVDD_OK in register RG_VREG_CTRL.

#define SR_DVREG_EXT 0x10, 0x08, 3

Access parameters for sub-register DVREG_EXT in register RG_VREG_CTRL.

#define SR_ED_LEVEL 0x07, 0xff, 0

Access parameters for sub-register ED_LEVEL in register RG_PHY_ED_LEVEL.

#define SR_FTN_START 0x18, 0x80, 7

Access parameters for sub-register FTN_START in register RG_FTN_CTRL.

#define SR_IEEE_ADDR_0 0x24, 0xff, 0

Access parameters for sub-register IEEE_ADDR_0 in register RG_IEEE_ADDR_0.

#define SR_IEEE_ADDR_1 0x25, 0xff, 0

Access parameters for sub-register IEEE_ADDR_1 in register RG_IEEE_ADDR_1.

#define SR_IEEE_ADDR_2 0x26, 0xff, 0

Access parameters for sub-register IEEE_ADDR_2 in register RG_IEEE_ADDR_2.

#define SR_IEEE_ADDR_3 0x27, 0xff, 0

Access parameters for sub-register IEEE_ADDR_3 in register RG_IEEE_ADDR_3.

#define SR_IEEE_ADDR_4 0x28, 0xff, 0

Access parameters for sub-register IEEE_ADDR_4 in register RG_IEEE_ADDR_4.

#define SR_IEEE_ADDR_5 0x29, 0xff, 0

Access parameters for sub-register IEEE_ADDR_5 in register RG_IEEE_ADDR_5.

#define SR_IEEE_ADDR_6 0x2a, 0xff, 0

Access parameters for sub-register IEEE_ADDR_6 in register RG_IEEE_ADDR_6.

#define SR_IEEE_ADDR_7 0x2b, 0xff, 0

Access parameters for sub-register IEEE_ADDR_7 in register RG_IEEE_ADDR_7.

#define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0

Access parameters for sub-register IRQ_0_PLL_LOCK in register RG_IRQ_STATUS.

#define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1

Access parameters for sub-register IRQ_1_PLL_UNLOCK in register RG_IRQ_STATUS.

#define SR_IRQ_2_EXT_EN 0x04, 0x40, 6

Access parameters for sub-register IRQ_2_EXT_EN in register RG_TRX_CTRL_1.

Referenced by trx_config().

#define SR_IRQ_2_RX_START 0x0f, 0x04, 2

Access parameters for sub-register IRQ_2_RX_START in register RG_IRQ_STATUS.

#define SR_IRQ_3_TRX_END 0x0f, 0x08, 3

Access parameters for sub-register IRQ_3_TRX_END in register RG_IRQ_STATUS.

#define SR_IRQ_4_CCA_ED_READY 0x0f, 0x10, 4

Access parameters for sub-register IRQ_4_CCA_ED_READY in register RG_IRQ_STATUS.

#define SR_IRQ_5_AMI 0x0f, 0x20, 5

Access parameters for sub-register IRQ_5_AMI in register RG_IRQ_STATUS.

#define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6

Access parameters for sub-register IRQ_6_TRX_UR in register RG_IRQ_STATUS.

#define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7

Access parameters for sub-register IRQ_7_BAT_LOW in register RG_IRQ_STATUS.

#define SR_IRQ_MASK 0x0e, 0xff, 0

Access parameters for sub-register IRQ_MASK in register RG_IRQ_MASK.

Referenced by set_trx_state().

#define SR_IRQ_MASK_MODE 0x04, 0x02, 1

Access parameters for sub-register IRQ_MASK_MODE in register RG_TRX_CTRL_1.

Referenced by trx_config().

#define SR_IRQ_POLARITY 0x04, 0x01, 0

Access parameters for sub-register IRQ_POLARITY in register RG_TRX_CTRL_1.

#define SR_MAN_ID_0 0x1e, 0xff, 0

Access parameters for sub-register MAN_ID_0 in register RG_MAN_ID_0.

#define SR_MAN_ID_1 0x1f, 0xff, 0

Access parameters for sub-register MAN_ID_1 in register RG_MAN_ID_1.

#define SR_MAX_BE 0x2f, 0xf0, 4

Access parameters for sub-register MAX_BE in register RG_CSMA_BE.

Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().

#define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1

Access parameters for sub-register MAX_CSMA_RETRIES in register RG_XAH_CTRL_0.

Referenced by send_frame(), and write_all_tal_pib_to_trx().

#define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4

Access parameters for sub-register MAX_FRAME_RETRIES in register RG_XAH_CTRL_0.

Referenced by send_frame(), and write_all_tal_pib_to_trx().

#define SR_MIN_BE 0x2f, 0x0f, 0

Access parameters for sub-register MIN_BE in register RG_CSMA_BE.

Referenced by tal_pib_set(), and write_all_tal_pib_to_trx().

#define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0

Access parameters for sub-register OQPSK_DATA_RATE in register RG_TRX_CTRL_2.

Referenced by apply_channel_page_configuration().

#define SR_OQPSK_SCRAM_EN 0x0C, 0x20, 5

Access parameters for sub-register OQPSK_SCRAM_EN in register RG_TRX_CTRL_2.

#define SR_PA_BUF_LT 0x05, 0xc0, 6

Access parameters for sub-register PA_BUF_LT in register RG_PHY_TX_PWR.

#define SR_PA_EXT_EN 0x04, 0x80, 7

Access parameters for sub-register PA_EXT_EN in register RG_TRX_CTRL_1.

Referenced by per_mode_receptor_init(), set_trx_state(), and trx_config().

#define SR_PA_LT 0x05, 0x30, 4

Access parameters for sub-register PA_LT in register RG_PHY_TX_PWR.

#define SR_PAD_IO 0x03, 0xc0, 6

Access parameters for sub-register PAD_IO in register RG_TRX_CTRL_0.

#define SR_PAD_IO_CLKM 0x03, 0x30, 4

Access parameters for sub-register PAD_IO_CLKM in register RG_TRX_CTRL_0.

Referenced by trx_config().

#define SR_PAN_ID_0 0x22, 0xff, 0

Access parameters for sub-register PAN_ID_0 in register RG_PAN_ID_0.

#define SR_PAN_ID_1 0x23, 0xff, 0

Access parameters for sub-register PAN_ID_1 in register RG_PAN_ID_1.

#define SR_PART_NUM 0x1c, 0xff, 0

Access parameters for sub-register PART_NUM in register RG_PART_NUM.

#define SR_PDT_THRES 0x0a, 0x0f, 0

Access parameters for sub-register PDT_THRES in register RG_RX_CTRL.

Referenced by trx_config().

#define SR_PLL_CF_START 0x1a, 0x80, 7

Access parameters for sub-register PLL_CF_START in register RG_PLL_CF.

#define SR_PLL_DCU_START 0x1b, 0x80, 7

Access parameters for sub-register PLL_DCU_START in register RG_PLL_DCU.

#define SR_RND_VALUE 0x06, 0x60, 5

Access parameters for sub-register RND_VALUE in register RG_PHY_RSSI.

Referenced by tal_generate_rand_seed().

#define SR_RSSI 0x06, 0x1f, 0

Access parameters for sub-register RSSI in register RG_PHY_RSSI.

#define SR_RX_BL_CTRL 0x04, 0x10, 4

Access parameters for sub-register RX_BL_CTRL in register RG_TRX_CTRL_1.

#define SR_RX_CRC_VALID 0x06, 0x80, 7

Access parameters for sub-register RX_CRC_VALID in register RG_PHY_RSSI.

Referenced by handle_received_frame_irq().

#define SR_RX_PDT_DIS 0x15, 0x80, 7

Access parameters for sub-register RX_PDT_DIS in register RG_RX_SYN.

Referenced by perform_cca_twice(), tal_generate_rand_seed(), tfa_cca_perform(), and tfa_ed_sample().

#define SR_RX_PDT_LEVEL 0x15, 0x0f, 0

Access parameters for sub-register RX_PDT_LEVEL in register RG_RX_SYN.

Referenced by tfa_pib_set().

#define SR_RX_SAFE_MODE 0x0c, 0x80, 7

Access parameters for sub-register RX_SAFE_MODE in register RG_TRX_CTRL_2.

Referenced by trx_config().

#define SR_SFD_VALUE 0x0b, 0xff, 0

Access parameters for sub-register SFD_VALUE in register RG_SFD_VALUE.

#define SR_SHORT_ADDR_0 0x20, 0xff, 0

Access parameters for sub-register SHORT_ADDR_0 in register RG_SHORT_ADDR_0.

#define SR_SHORT_ADDR_1 0x21, 0xff, 0

Access parameters for sub-register SHORT_ADDR_1 in register RG_SHORT_ADDR_1.

#define SR_SLOTTED_OPERATION 0x2c, 0x01, 0

Access parameters for sub-register SLOTTED_OPERATION in register RG_XAH_CTRL_0.

#define SR_SPI_CMD_MODE 0x04, 0x0c, 2

Access parameters for sub-register SPI_CMD_MODE in register RG_TRX_CTRL_1.

#define SR_TRAC_STATUS 0x02, 0xe0, 5

Access parameters for sub-register TRAC_STATUS in register RG_TRX_STATE.

Referenced by handle_tx_end_irq().

#define SR_TRX_CMD 0x02, 0x1f, 0

Access parameters for sub-register TRX_CMD in register RG_TRX_STATE.

#define SR_TRX_STATUS 0x01, 0x1f, 0

Access parameters for sub-register TRX_STATUS in register RG_TRX_STATUS.

Referenced by set_trx_state(), switch_pll_on(), tal_get_trx_status(), trx_init(), and trx_reset().

#define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5

Access parameters for sub-register TX_AUTO_CRC_ON in register RG_TRX_CTRL_1.

Referenced by tfa_continuous_tx_start().

#define SR_TX_PWR 0x05, 0x0f, 0

Access parameters for sub-register TX_PWR in register RG_PHY_TX_PWR.

Referenced by tal_get_curr_trx_config(), tal_pib_set(), and write_all_tal_pib_to_trx().

#define SR_VERSION_NUM 0x1d, 0xff, 0

Access parameters for sub-register VERSION_NUM in register RG_VERSION_NUM.

#define SR_XTAL_MODE 0x12, 0xf0, 4

Access parameters for sub-register XTAL_MODE in register RG_XOSC_CTRL.

#define SR_XTAL_TRIM 0x12, 0x0f, 0

Access parameters for sub-register XTAL_TRIM in register RG_XOSC_CTRL.

#define T_OCT 32

Duration of an octet for 250kb/s OQPSK mode in us.

#define T_SYM 16

Duration of an symbol for 250kb/s OQPSK mode in us.

#define THRES_ANT_DIV_DISABLE (0x7)

Constant THRES_ANT_DIV_DISABLED for sub-register SR_PDT_THRES in register RG_RX_CTRL.

#define THRES_ANT_DIV_ENABLE (0x3)

Constant THRES_ANT_DIV_ENABLE for sub-register SR_PDT_THRES in register RG_RX_CTRL.

Referenced by trx_config().

#define TIMESTAMPING_DISABLE (0)

Constant TIMESTAMPING_DISABLE for sub-register SR_IRQ_2_EXT_EN in register RG_TRX_CTRL_1.

#define TIMESTAMPING_ENABLE (1)

Constant TIMESTAMPING_ENABLE for sub-register SR_IRQ_2_EXT_EN in register RG_TRX_CTRL_1.

Referenced by trx_config().

#define TRANSCEIVER_NAME "AT86RF231"

Referenced by get_board_details(), and get_node_info().

#define TRX_IRQ_DELAY_US (9) /* TRX Parameter: tIRQ */

Referenced by send_frame(), and tx_done_handling().

#define TRX_OFF_TO_PLL_ON_TIME_US (110) /* TRX Parameter: tTR4 */

Referenced by perform_cca_twice(), and switch_pll_on().

#define TRX_OFF_TO_SLEEP_TIME_CLKM_CYCLES (35) /* TRX Parameter: tTR3 */

Referenced by set_trx_state().

#define TRX_SUPPORTED_CHANNELS (0x07FFF800)

Referenced by apply_channel_page_configuration(), handle_incoming_msg(), init_tal_pib(), and tal_pib_set().

#define TX_AUTO_CRC_DISABLE (0)

Constant TX_AUTO_CRC_ENABLE for sub-register TX_AUTO_CRC_ON in register RG_TRX_CTRL_1.

Referenced by tfa_continuous_tx_start().

#define TX_AUTO_CRC_ENABLE (1)

Constant TX_AUTO_CRC_ENABLE for sub-register TX_AUTO_CRC_ON in register RG_TRX_CTRL_1.

#define TX_PWR_TOLERANCE (0x80)

Tolerance of the phyTransmitPower PIB attribute.

This is encoded into the two MSBits of the attribute, and is effectively read-only.

Referenced by limit_tx_pwr(), and set_default_tx_pwr().

#define UPLD_RES_FT_DISABLE (0)

Constant UPLD_RES_FT_DISBALE for sub-register AACK_UPLD_RES_FT in register RG_XAH_CTRL_1.

#define UPLD_RES_FT_ENABLE (1)

Constant UPLD_RES_FT_DISBALE for sub-register AACK_UPLD_RES_FT in register RG_XAH_CTRL_1.

typedef enum tal_trx_status_tag tal_trx_status_t

Transceiver states.

typedef enum trx_cmd_tag trx_cmd_t

Transceiver commands.

typedef enum trx_irq_reason_tag trx_irq_reason_t

Transceiver interrupt reasons.

typedef enum trx_trac_status_tag trx_trac_status_t

Transceiver's trac status.

enum tal_trx_status_tag

Transceiver states.

Enumerator
P_ON	Constant P_ON for sub-register SR_TRX_STATUS.
BUSY_RX	Constant BUSY_RX for sub-register SR_TRX_STATUS.
BUSY_TX	Constant BUSY_TX for sub-register SR_TRX_STATUS.
RX_ON	Constant RX_ON for sub-register SR_TRX_STATUS.
TRX_OFF	Constant TRX_OFF for sub-register SR_TRX_STATUS.
PLL_ON	Constant PLL_ON for sub-register SR_TRX_STATUS.
TRX_SLEEP	Constant SLEEP for sub-register SR_TRX_STATUS.
BUSY_RX_AACK	Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS.
BUSY_TX_ARET	Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS.
RX_AACK_ON	Constant RX_AACK_ON for sub-register SR_TRX_STATUS.
TX_ARET_ON	Constant TX_ARET_ON for sub-register SR_TRX_STATUS.
RX_ON_NOCLK	Constant RX_ON_NOCLK for sub-register SR_TRX_STATUS.
RX_AACK_ON_NOCLK	Constant RX_AACK_ON_NOCLK for sub-register SR_TRX_STATUS.
BUSY_RX_AACK_NOCLK	Constant BUSY_RX_AACK_NOCLK for sub-register SR_TRX_STATUS.
STATE_TRANSITION_IN_PROGRESS	Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS.
P_ON	Constant P_ON for sub-register SR_TRX_STATUS.
TRX_OFF	Constant TRX_OFF for sub-register SR_TRX_STATUS.
PLL_ON	Constant PLL_ON for sub-register SR_TRX_STATUS.
TRX_SLEEP	Constant TRX_SLEEP for sub-register SR_TRX_STATUS.
RX_ON	Constant RX_AACK_ON for sub-register SR_TRX_STATUS.
P_ON	Constant P_ON for sub-register SR_TRX_STATUS.
BUSY_RX	Constant BUSY_RX for sub-register SR_TRX_STATUS.
BUSY_TX	Constant BUSY_TX for sub-register SR_TRX_STATUS.
RX_ON	Constant RX_ON for sub-register SR_TRX_STATUS.
TRX_OFF	Constant TRX_OFF for sub-register SR_TRX_STATUS.
PLL_ON	Constant PLL_ON for sub-register SR_TRX_STATUS.
TRX_SLEEP	Constant TRX_SLEEP for sub-register SR_TRX_STATUS.
BUSY_RX_AACK	Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS.
BUSY_TX_ARET	Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS.
RX_AACK_ON	Constant RX_AACK_ON for sub-register SR_TRX_STATUS.
TX_ARET_ON	Constant TX_ARET_ON for sub-register SR_TRX_STATUS.
RX_ON_NOCLK	Constant RX_ON_NOCLK for sub-register SR_TRX_STATUS.
RX_AACK_ON_NOCLK	Constant RX_AACK_ON_NOCLK for sub-register SR_TRX_STATUS.
BUSY_RX_AACK_NOCLK	Constant BUSY_RX_AACK_NOCLK for sub-register SR_TRX_STATUS.
STATE_TRANSITION_IN_PROGRESS	Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS.
P_ON	Constant P_ON for sub-register SR_TRX_STATUS.
BUSY_RX	Constant BUSY_RX for sub-register SR_TRX_STATUS.
BUSY_TX	Constant BUSY_TX for sub-register SR_TRX_STATUS.
RX_ON	Constant RX_ON for sub-register SR_TRX_STATUS.
TRX_OFF	Constant TRX_OFF for sub-register SR_TRX_STATUS.
PLL_ON	Constant PLL_ON for sub-register SR_TRX_STATUS.
TRX_SLEEP	Constant TRX_SLEEP for sub-register SR_TRX_STATUS.
BUSY_RX_AACK	Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS.
BUSY_TX_ARET	Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS.
RX_AACK_ON	Constant RX_AACK_ON for sub-register SR_TRX_STATUS.
TX_ARET_ON	Constant TX_ARET_ON for sub-register SR_TRX_STATUS.
RX_ON_NOCLK	Constant RX_ON_NOCLK for sub-register SR_TRX_STATUS.
RX_AACK_ON_NOCLK	Constant RX_AACK_ON_NOCLK for sub-register SR_TRX_STATUS.
BUSY_RX_AACK_NOCLK	Constant BUSY_RX_AACK_NOCLK for sub-register SR_TRX_STATUS.
STATE_TRANSITION_IN_PROGRESS	Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS.
P_ON	Constant P_ON for sub-register SR_TRX_STATUS.
BUSY_RX	Constant BUSY_RX for sub-register SR_TRX_STATUS.
BUSY_TX	Constant BUSY_TX for sub-register SR_TRX_STATUS.
RX_ON	Constant RX_ON for sub-register SR_TRX_STATUS.
TRX_OFF	Constant TRX_OFF for sub-register SR_TRX_STATUS.
PLL_ON	Constant PLL_ON for sub-register SR_TRX_STATUS.
TRX_SLEEP	Constant TRX_SLEEP for sub-register SR_TRX_STATUS.
PREP_DEEP_SLEEP	Constant PREP_DEEP_SLEEP for sub-register SR_TRX_STATUS.
BUSY_RX_AACK	Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS.
BUSY_TX_ARET	Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS.
RX_AACK_ON	Constant RX_AACK_ON for sub-register SR_TRX_STATUS.
TX_ARET_ON	Constant TX_ARET_ON for sub-register SR_TRX_STATUS.
STATE_TRANSITION_IN_PROGRESS	Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS.
TRX_DEEP_SLEEP	Software implemented state.
P_ON	Constant P_ON for sub-register SR_TRX_STATUS.
BUSY_RX	Constant BUSY_RX for sub-register SR_TRX_STATUS.
BUSY_TX	Constant BUSY_TX for sub-register SR_TRX_STATUS.
RX_ON	Constant RX_ON for sub-register SR_TRX_STATUS.
TRX_OFF	Constant TRX_OFF for sub-register SR_TRX_STATUS.
PLL_ON	Constant PLL_ON for sub-register SR_TRX_STATUS.
TRX_SLEEP	Constant TRX_SLEEP for sub-register SR_TRX_STATUS.
BUSY_RX_AACK	Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS.
BUSY_TX_ARET	Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS.
RX_AACK_ON	Constant RX_AACK_ON for sub-register SR_TRX_STATUS.
TX_ARET_ON	Constant TX_ARET_ON for sub-register SR_TRX_STATUS.
STATE_TRANSITION_IN_PROGRESS	Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS.

enum trx_cmd_tag

Transceiver commands.

Enumerator
CMD_NOP	Constant CMD_NOP for sub-register SR_TRX_CMD.
CMD_TX_START	Constant CMD_TX_START for sub-register SR_TRX_CMD.
CMD_FORCE_TRX_OFF	Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD.
CMD_FORCE_PLL_ON	Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD.
CMD_RX_ON	Constant CMD_RX_ON for sub-register SR_TRX_CMD.
CMD_TRX_OFF	Constant CMD_TRX_OFF for sub-register SR_TRX_CMD.
CMD_PLL_ON	Constant CMD_PLL_ON for sub-register SR_TRX_CMD.
CMD_SLEEP	Software implemented command.
CMD_RX_AACK_ON	Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD.
CMD_TX_ARET_ON	Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD.
CMD_NOP	Constant CMD_NOP for sub-register SR_TRX_CMD.
CMD_TX_START	Constant CMD_TX_START for sub-register SR_TRX_CMD.
CMD_FORCE_TRX_OFF	Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD.
CMD_FORCE_PLL_ON	Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD.
CMD_RX_ON	Constant CMD_RX_ON for sub-register SR_TRX_CMD.
CMD_TRX_OFF	Constant CMD_TRX_OFF for sub-register SR_TRX_CMD.
CMD_PLL_ON	Constant CMD_PLL_ON for sub-register SR_TRX_CMD.
CMD_RX_AACK_ON	Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD.
CMD_TX_ARET_ON	Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD.
CMD_SLEEP	Software implemented command.
CMD_NOP	Constant CMD_NOP for sub-register SR_TRX_CMD.
CMD_TX_START	Constant CMD_TX_START for sub-register SR_TRX_CMD.
CMD_FORCE_TRX_OFF	Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD.
CMD_FORCE_PLL_ON	Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD.
CMD_RX_ON	Constant CMD_RX_ON for sub-register SR_TRX_CMD.
CMD_TRX_OFF	Constant CMD_TRX_OFF for sub-register SR_TRX_CMD.
CMD_PLL_ON	Constant CMD_PLL_ON for sub-register SR_TRX_CMD.
CMD_RX_AACK_ON	Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD.
CMD_TX_ARET_ON	Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD.
CMD_SLEEP	Software implemented command.
CMD_NOP	Constant CMD_NOP for sub-register SR_TRX_CMD.
CMD_TX_START	Constant CMD_TX_START for sub-register SR_TRX_CMD.
CMD_FORCE_TRX_OFF	Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD.
CMD_FORCE_PLL_ON	Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD.
CMD_RX_ON	Constant CMD_RX_ON for sub-register SR_TRX_CMD.
CMD_TRX_OFF	Constant CMD_TRX_OFF for sub-register SR_TRX_CMD.
CMD_PLL_ON	Constant CMD_PLL_ON for sub-register SR_TRX_CMD.
CMD_PREP_DEEP_SLEEP	Constant CMD_PREP_DEEP_SLEEP for sub-register SR_TRX_CMD.
CMD_RX_AACK_ON	Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD.
CMD_TX_ARET_ON	Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD.
CMD_SLEEP	Software implemented command.
CMD_DEEP_SLEEP	Software implemented command.
CMD_NOP	Constant CMD_NOP for sub-register SR_TRX_CMD.
CMD_TX_START	Constant CMD_TX_START for sub-register SR_TRX_CMD.
CMD_FORCE_TRX_OFF	Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD.
CMD_FORCE_PLL_ON	Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD.
CMD_RX_ON	Constant CMD_RX_ON for sub-register SR_TRX_CMD.
CMD_TRX_OFF	Constant CMD_TRX_OFF for sub-register SR_TRX_CMD.
CMD_PLL_ON	Constant CMD_PLL_ON for sub-register SR_TRX_CMD.
CMD_RX_AACK_ON	Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD.
CMD_TX_ARET_ON	Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD.
CMD_SLEEP	Software implemented command.

enum trx_irq_reason_tag

Transceiver interrupt reasons.

Enumerator
TRX_NO_IRQ	No interrupt is indicated by IRQ_STATUS register.
TRX_IRQ_PLL_LOCK	PLL goes to lock-state.
TRX_IRQ_PLL_UNLOCK	Signals an unlocked PLL.
TRX_IRQ_RX_START	Signals begin of a receiving frame.
TRX_IRQ_TRX_END	Signals end of frames (transmit and receive)
TRX_IRQ_CCA_ED_READY	Multi-functional interrupt: AWAKE_END: Indicates that the radio transceiver reached TRX_OFF state after P_ON, RESET, or SLEEP states. CCA_ED_READY: Signals the end of a CCA or ED measurement.
TRX_IRQ_AMI	Signals an address match.
TRX_IRQ_TRX_UR	Signals a FIFO underrun.
TRX_IRQ_BAT_LOW	Signals low battery.
TRX_IRQ_7_BAT_LOW	Constant TRX_IRQ_7_BAT_LOW for sub-register SR_IRQ_7_BAT_LOW.
TRX_IRQ_6_TRX_UR	Constant TRX_IRQ_6_TRX_UR for sub-register SR_IRQ_6_TRX_UR.
TRX_IRQ_5_AMI	Constant TRX_IRQ_5_AMI for sub-register SR_IRQ_5_AMI.
TRX_IRQ_4_CCA_ED_DONE	Constant TRX_IRQ_4_CCA_ED_DONE for sub-register SR_IRQ_4_CCA_ED_DONE.
TRX_IRQ_3_TRX_END	Constant TRX_IRQ_3_TRX_END for sub-register SR_IRQ_3_TRX_END.
TRX_IRQ_2_RX_START	Constant TRX_IRQ_2_RX_START for sub-register SR_IRQ_2_RX_START.
TRX_IRQ_1_PLL_UNLOCK	Constant TRX_IRQ_1_PLL_UNLOCK for sub-register SR_IRQ_1_PLL_UNLOCK.
TRX_IRQ_0_PLL_LOCK	Constant TRX_IRQ_0_PLL_LOCK for sub-register SR_IRQ_0_PLL_LOCK.
TRX_NO_IRQ	No interrupt is indicated by IRQ_STATUS register.
TRX_IRQ_7_BAT_LOW	Constant TRX_IRQ_7_BAT_LOW for sub-register SR_IRQ_7_BAT_LOW.
TRX_IRQ_6_TRX_UR	Constant TRX_IRQ_6_TRX_UR for sub-register SR_IRQ_6_TRX_UR.
TRX_IRQ_5_AMI	Constant TRX_IRQ_5_AMI for sub-register SR_IRQ_5_AMI.
TRX_IRQ_4_CCA_ED_DONE	Constant TRX_IRQ_4_CCA_ED_DONE for sub-register SR_IRQ_4_CCA_ED_DONE.
TRX_IRQ_3_TRX_END	Constant TRX_IRQ_3_TRX_END for sub-register SR_IRQ_3_TRX_END.
TRX_IRQ_2_RX_START	Constant TRX_IRQ_2_RX_START for sub-register SR_IRQ_2_RX_START.
TRX_IRQ_1_PLL_UNLOCK	Constant TRX_IRQ_1_PLL_UNLOCK for sub-register SR_IRQ_1_PLL_UNLOCK.
TRX_IRQ_0_PLL_LOCK	Constant TRX_IRQ_0_PLL_LOCK for sub-register SR_IRQ_0_PLL_LOCK.
TRX_NO_IRQ	No interrupt is indicated by IRQ_STATUS register.
TRX_IRQ_7_BAT_LOW	Constant TRX_IRQ_7_BAT_LOW for sub-register SR_IRQ_7_BAT_LOW.
TRX_IRQ_6_TRX_UR	Constant TRX_IRQ_6_TRX_UR for sub-register SR_IRQ_6_TRX_UR.
TRX_IRQ_5_AMI	Constant TRX_IRQ_5_AMI for sub-register SR_IRQ_5_AMI.
TRX_IRQ_4_CCA_ED_DONE	Constant TRX_IRQ_4_CCA_ED_DONE for sub-register SR_IRQ_4_CCA_ED_DONE.
TRX_IRQ_3_TRX_END	Constant TRX_IRQ_3_TRX_END for sub-register SR_IRQ_3_TRX_END.
TRX_IRQ_2_RX_START	Constant TRX_IRQ_2_RX_START for sub-register SR_IRQ_2_RX_START.
TRX_IRQ_1_PLL_UNLOCK	Constant TRX_IRQ_1_PLL_UNLOCK for sub-register SR_IRQ_1_PLL_UNLOCK.
TRX_IRQ_0_PLL_LOCK	Constant TRX_IRQ_0_PLL_LOCK for sub-register SR_IRQ_0_PLL_LOCK.
TRX_NO_IRQ	No interrupt is indicated by IRQ_STATUS register.
TRX_IRQ_7_BAT_LOW	Constant TRX_IRQ_7_BAT_LOW for sub-register SR_IRQ_7_BAT_LOW.
TRX_IRQ_6_TRX_UR	Constant TRX_IRQ_6_TRX_UR for sub-register SR_IRQ_6_TRX_UR.
TRX_IRQ_5_AMI	Constant TRX_IRQ_5_AMI for sub-register SR_IRQ_5_AMI.
TRX_IRQ_4_CCA_ED_DONE	Constant TRX_IRQ_4_CCA_ED_DONE for sub-register SR_IRQ_4_CCA_ED_DONE.
TRX_IRQ_3_TRX_END	Constant TRX_IRQ_3_TRX_END for sub-register SR_IRQ_3_TRX_END.
TRX_IRQ_2_RX_START	Constant TRX_IRQ_2_RX_START for sub-register SR_IRQ_2_RX_START.
TRX_IRQ_1_PLL_UNLOCK	Constant TRX_IRQ_1_PLL_UNLOCK for sub-register SR_IRQ_1_PLL_UNLOCK.
TRX_IRQ_0_PLL_LOCK	Constant TRX_IRQ_0_PLL_LOCK for sub-register SR_IRQ_0_PLL_LOCK.
TRX_NO_IRQ	No interrupt is indicated by IRQ_STATUS register.

enum trx_trac_status_tag

Transceiver's trac status.

Enumerator
TRAC_SUCCESS
TRAC_SUCCESS_DATA_PENDING
TRAC_WAIT_FOR_ACK
TRAC_CHANNEL_ACCESS_FAILURE
TRAC_NO_ACK
TRAC_INVALID
TRAC_SUCCESS	Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS.
TRAC_SUCCESS_DATA_PENDING	Constant TRAC_SUCCESS_DATA_PENDING for sub-register SR_TRAC_STATUS.
TRAC_SUCCESS_WAIT_FOR_ACK	Constant TRAC_SUCCESS_WAIT_FOR_ACK for sub-register SR_TRAC_STATUS.
TRAC_CHANNEL_ACCESS_FAILURE	Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register SR_TRAC_STATUS.
TRAC_NO_ACK	Constant TRAC_NO_ACK for sub-register SR_TRAC_STATUS.
TRAC_INVALID	Constant TRAC_INVALID for sub-register SR_TRAC_STATUS.
TRAC_SUCCESS	Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS.
TRAC_SUCCESS_DATA_PENDING	Constant TRAC_SUCCESS_DATA_PENDING for sub-register SR_TRAC_STATUS.
TRAC_SUCCESS_WAIT_FOR_ACK	Constant TRAC_SUCCESS_WAIT_FOR_ACK for sub-register SR_TRAC_STATUS.
TRAC_CHANNEL_ACCESS_FAILURE	Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register SR_TRAC_STATUS.
TRAC_NO_ACK	Constant TRAC_NO_ACK for sub-register SR_TRAC_STATUS.
TRAC_INVALID	Constant TRAC_INVALID for sub-register SR_TRAC_STATUS.
TRAC_SUCCESS	Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS.
TRAC_SUCCESS_DATA_PENDING	Constant TRAC_SUCCESS_DATA_PENDING for sub-register SR_TRAC_STATUS.
TRAC_SUCCESS_WAIT_FOR_ACK	Constant TRAC_SUCCESS_WAIT_FOR_ACK for sub-register SR_TRAC_STATUS.
TRAC_CHANNEL_ACCESS_FAILURE	Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register SR_TRAC_STATUS.
TRAC_NO_ACK	Constant TRAC_NO_ACK for sub-register SR_TRAC_STATUS.
TRAC_INVALID	Constant TRAC_INVALID for sub-register SR_TRAC_STATUS.
TRAC_SUCCESS	Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS.
TRAC_SUCCESS_DATA_PENDING	Constant TRAC_SUCCESS_DATA_PENDING for sub-register SR_TRAC_STATUS.
TRAC_SUCCESS_WAIT_FOR_ACK	Constant TRAC_SUCCESS_WAIT_FOR_ACK for sub-register SR_TRAC_STATUS.
TRAC_CHANNEL_ACCESS_FAILURE	Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register SR_TRAC_STATUS.
TRAC_NO_ACK	Constant TRAC_NO_ACK for sub-register SR_TRAC_STATUS.
TRAC_INVALID	Constant TRAC_INVALID for sub-register SR_TRAC_STATUS.

Microchip® Advanced Software Framework

Macros

Typedefs

Enumerations