Chip-specific system clock management functions.
Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
#include <board.h>#include <compiler.h>#include <dfll.h>#include <osc.h>#include <pll.h>#include <genclk.h>Macros | |
| #define | CONFIG_HCACHE_ENABLE 1 |
| #define | CONFIG_SYSCLK_CPU_DIV 0 |
| Configuration symbol for dividing the CPU clock frequency by \(2^{CONFIG\_SYSCLK\_CPU\_DIV}\). More... | |
| #define | CONFIG_SYSCLK_INIT_CPUMASK |
| Configuration symbol for the CPU clocks enabled at power-on after the sysclock module has been initialized. More... | |
| #define | CONFIG_SYSCLK_INIT_HSBMASK |
| Configuration symbol for the HSB clocks enabled at power-on after the sysclock module has been initialized. More... | |
| #define | CONFIG_SYSCLK_INIT_PBAMASK |
| Configuration symbol for the PBA clocks enabled at power-on after the sysclock module has been initialized. More... | |
| #define | CONFIG_SYSCLK_INIT_PBBMASK |
| Configuration symbol for the PBB clocks enabled at power-on after the sysclock module has been initialized. More... | |
| #define | CONFIG_SYSCLK_INIT_PBCMASK |
| Configuration symbol for the PBC clocks enabled at power-on after the sysclock module has been initialized. More... | |
| #define | CONFIG_SYSCLK_INIT_PBDMASK |
| Configuration symbol for the PBD clocks enabled at power-on after the sysclock module has been initialized. More... | |
| #define | CONFIG_SYSCLK_PBA_DIV 0 |
| Configuration symbol for dividing the PBA clock frequency by \(2^{CONFIG\_SYSCLK\_PBA\_DIV}\). More... | |
| #define | CONFIG_SYSCLK_PBB_DIV 0 |
| Configuration symbol for dividing the PBB clock frequency by \(2^{CONFIG\_SYSCLK\_PBB\_DIV}\). More... | |
| #define | CONFIG_SYSCLK_PBC_DIV 0 |
| Configuration symbol for dividing the PBC clock frequency by \(2^{CONFIG\_SYSCLK\_PBC\_DIV}\). More... | |
| #define | CONFIG_SYSCLK_PBD_DIV 0 |
| Configuration symbol for dividing the PBD clock frequency by \(2^{CONFIG\_SYSCLK\_PBD\_DIV}\). More... | |
| #define | CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RCSYS |
| #define | CONFIG_USBCLK_DIV |
| Configuration symbol for the USB generic clock divider setting. More... | |
| #define | CONFIG_USBCLK_SOURCE |
| Configuration symbol for the USB generic clock source. More... | |
| #define | USBCLK_STARTUP_TIMEOUT (OSC0_STARTUP_TIMEOUT*(1000000/OSC_RCSYS_NOMINAL_HZ)) |
| Number of us to wait for USB clock to start. More... | |
System clock source | |
| #define | SYSCLK_SRC_RCSYS 0 |
| System RC oscillator. More... | |
| #define | SYSCLK_SRC_OSC0 1 |
| Oscillator 0. More... | |
| #define | SYSCLK_SRC_PLL0 2 |
| Phase Locked Loop 0. More... | |
| #define | SYSCLK_SRC_DFLL 3 |
| Digital Frequency Locked Loop. More... | |
| #define | SYSCLK_SRC_RC80M 4 |
| 80 MHz RC oscillator More... | |
| #define | SYSCLK_SRC_RCFAST 5 |
| 4-8-12 MHz RC oscillator More... | |
| #define | SYSCLK_SRC_RC1M 6 |
| 1 MHz RC oscillator More... | |
USB Clock Sources | |
| #define | USBCLK_SRC_OSC0 GENCLK_SRC_OSC0 |
| Use OSC0. More... | |
| #define | USBCLK_SRC_PLL0 GENCLK_SRC_PLL0 |
| Use PLL0. More... | |
| #define | USBCLK_SRC_DFLL GENCLK_SRC_DFLL |
| Use DFLL. More... | |
| #define | USBCLK_SRC_GCLKIN0 GENCLK_SRC_GCLKIN0 |
| Use GCLKIN0. More... | |
Bus index of maskable module clocks | |
| #define | PM_CLK_GRP_CPU 0 |
| #define | PM_CLK_GRP_HSB 1 |
| #define | PM_CLK_GRP_PBA 2 |
| #define | PM_CLK_GRP_PBB 3 |
| #define | PM_CLK_GRP_PBC 4 |
| #define | PM_CLK_GRP_PBD 5 |
Clocks derived from the CPU clock | |
| #define | SYSCLK_OCD 0 |
| On-Chip Debug system. More... | |
Clocks derived from the HSB clock | |
| #define | SYSCLK_PDCA_HSB 0 |
| PDCA memory interface. More... | |
| #define | SYSCLK_HFLASHC_DATA 1 |
| Flash data interface. More... | |
| #define | SYSCLK_HRAMC1_DATA 2 |
| HRAMC data interface. More... | |
| #define | SYSCLK_USBC_DATA 3 |
| USBC DMA and FIFO interface. More... | |
| #define | SYSCLK_CRCCU_DATA 4 |
| CRCCU data interface. More... | |
| #define | SYSCLK_PBA_BRIDGE 5 |
| HSB<->PBA bridge. More... | |
| #define | SYSCLK_PBB_BRIDGE 6 |
| HSB<->PBB bridge. More... | |
| #define | SYSCLK_PBC_BRIDGE 7 |
| HSB<->PBC bridge. More... | |
| #define | SYSCLK_PBD_BRIDGE 8 |
| HSB<->PBD bridge. More... | |
| #define | SYSCLK_AESA_HSB 9 |
| Advanced Encryption Standard. More... | |
Clocks derived from the PBA clock | |
| #define | SYSCLK_IISC 0 |
| IISC Controller. More... | |
| #define | SYSCLK_SPI 1 |
| SPI Controller. More... | |
| #define | SYSCLK_TC0 2 |
| Timer/Counter 0. More... | |
| #define | SYSCLK_TC1 3 |
| Timer/Counter 1. More... | |
| #define | SYSCLK_TWIM0 4 |
| TWI Master 0. More... | |
| #define | SYSCLK_TWIS0 5 |
| TWI Slave 0. More... | |
| #define | SYSCLK_TWIM1 6 |
| TWI Master 1. More... | |
| #define | SYSCLK_TWIS1 7 |
| TWI Slave 1. More... | |
| #define | SYSCLK_USART0 8 |
| USART 0. More... | |
| #define | SYSCLK_USART1 9 |
| USART 1. More... | |
| #define | SYSCLK_USART2 10 |
| USART 2. More... | |
| #define | SYSCLK_USART3 11 |
| USART 3. More... | |
| #define | SYSCLK_ADCIFE 12 |
| A/D Converter. More... | |
| #define | SYSCLK_DACC 13 |
| D/A Converter. More... | |
| #define | SYSCLK_ACIFC 14 |
| Analog Comparator. More... | |
| #define | SYSCLK_GLOC 15 |
| Glue Logic Controller. More... | |
| #define | SYSCLK_ABDACB 16 |
| ABDACB Controller. More... | |
| #define | SYSCLK_TRNG 17 |
| TRNG Controller. More... | |
| #define | SYSCLK_PARC 18 |
| PARC Controller. More... | |
| #define | SYSCLK_CATB 19 |
| Capacitive Touch. More... | |
| #define | SYSCLK_TWIM2 21 |
| TWI Master 2. More... | |
| #define | SYSCLK_TWIM3 22 |
| TWI Master 3. More... | |
| #define | SYSCLK_LCDCA 23 |
| LCD Controller. More... | |
Clocks derived from the PBB clock | |
| #define | SYSCLK_HFLASHC_REGS 0 |
| Flash Controller registers. More... | |
| #define | SYSCLK_HRAMC1_REGS 1 |
| HRAMC Controller registers. More... | |
| #define | SYSCLK_HMATRIX 2 |
| HSB Matrix configuration. More... | |
| #define | SYSCLK_PDCA_PB 3 |
| PDCA peripheral bus interface. More... | |
| #define | SYSCLK_CRCCU_REGS 4 |
| CRCCU registers. More... | |
| #define | SYSCLK_USBC_REGS 5 |
| USBC registers. More... | |
| #define | SYSCLK_PEVC 6 |
| PEVC Controller. More... | |
Clocks derived from the PBC clock | |
| #define | SYSCLK_PM 0 |
| PM configuration. More... | |
| #define | SYSCLK_CHIPID 1 |
| CHIPID Controller. More... | |
| #define | SYSCLK_SCIF 2 |
| System Control Interface. More... | |
| #define | SYSCLK_FREQM 3 |
| Frequency Meter. More... | |
| #define | SYSCLK_GPIO 4 |
| General-Purpose I/O. More... | |
Clocks derived from the PBD clock | |
| #define | SYSCLK_BPM 0 |
| BPM configuration. More... | |
| #define | SYSCLK_BSCIF 1 |
| BSCIF configuration. More... | |
| #define | SYSCLK_AST 2 |
| Asynchronous Timer. More... | |
| #define | SYSCLK_WDT 3 |
| Watchdog Timer. More... | |
| #define | SYSCLK_EIC 4 |
| External Interrupt Controller. More... | |
| #define | SYSCLK_PICOUART 5 |
| PICOUART. More... | |
Divided clock mask derived from the PBA clock | |
| #define | PBA_DIVMASK_TIMER_CLOCK2 (1u << 0) |
| TIMER_CLOCK2 mask. More... | |
| #define | PBA_DIVMASK_TIMER_CLOCK3 (1u << 2) |
| TIMER_CLOCK3 mask. More... | |
| #define | PBA_DIVMASK_CLK_USART (1u << 2) |
| CLK_USART/DIV mask. More... | |
| #define | PBA_DIVMASK_TIMER_CLOCK4 (1u << 4) |
| TIMER_CLOCK4 mask. More... | |
| #define | PBA_DIVMASK_TIMER_CLOCK5 (1u << 6) |
| TIMER_CLOCK5 mask. More... | |
| #define | PBA_DIVMASK_Msk (0x7Fu << 0) |
| Bitfield mask. More... | |
Functions | |
| void | sysclk_disable_usb (void) |
| Disable the USB generic clock. More... | |
| void | sysclk_enable_usb (void) |
| Enable the USB generic clock. More... | |
| void | sysclk_priv_disable_module (uint32_t bus_id, uint32_t module_index) |
| Disable a maskable module clock. More... | |
| void | sysclk_priv_enable_module (uint32_t bus_id, uint32_t module_index) |
| Enable a maskable module clock. More... | |
Querying the system clock and its derived clocks | |
The following functions may be used to query the current frequency of the system clock and the CPU and bus clocks derived from it. sysclk_get_main_hz() and sysclk_get_cpu_hz() can be assumed to be available on all platforms, although some platforms may define additional accessors for various chip-internal bus clocks. These are usually not intended to be queried directly by generic code. | |
| static uint32_t | sysclk_get_main_hz (void) |
| Return the current rate in Hz of the main system clock. More... | |
| static uint32_t | sysclk_get_cpu_hz (void) |
| Return the current rate in Hz of the CPU clock. More... | |
| static uint32_t | sysclk_get_hsb_hz (void) |
| Return the current rate in Hz of the High-Speed Bus clock. More... | |
| static uint32_t | sysclk_get_pba_hz (void) |
| Return the current rate in Hz of the Peripheral Bus A clock. More... | |
| static uint32_t | sysclk_get_pbb_hz (void) |
| Return the current rate in Hz of the Peripheral Bus B clock. More... | |
| static uint32_t | sysclk_get_pbc_hz (void) |
| Return the current rate in Hz of the Peripheral Bus C clock. More... | |
| static uint32_t | sysclk_get_pbd_hz (void) |
| Return the current rate in Hz of the Peripheral Bus D clock. More... | |
| uint32_t | sysclk_get_peripheral_bus_hz (const volatile void *module) |
| Retrieves the current rate in Hz of the Peripheral Bus clock attached to the specified peripheral. More... | |
Enabling and disabling synchronous clocks | |
| static void | sysclk_enable_cpu_module (uint32_t module_index) |
| Enable a module clock derived from the CPU clock. More... | |
| static void | sysclk_disable_cpu_module (uint32_t module_index) |
| Disable a module clock derived from the CPU clock. More... | |
| static void | sysclk_enable_hsb_module (uint32_t module_index) |
| Enable a module clock derived from the HSB clock. More... | |
| static void | sysclk_disable_hsb_module (uint32_t module_index) |
| Disable a module clock derived from the HSB clock. More... | |
| void | sysclk_enable_pba_module (uint32_t module_index) |
| Enable a module clock derived from the PBA clock. More... | |
| void | sysclk_disable_pba_module (uint32_t module_index) |
| Disable a module clock derived from the PBA clock. More... | |
| void | sysclk_enable_pbb_module (uint32_t module_index) |
| Enable a module clock derived from the PBB clock. More... | |
| void | sysclk_disable_pbb_module (uint32_t module_index) |
| Disable a module clock derived from the PBB clock. More... | |
| static void | sysclk_enable_pbc_module (uint32_t module_index) |
| Enable a module clock derived from the PBC clock. More... | |
| static void | sysclk_disable_pbc_module (uint32_t module_index) |
| Disable a module clock derived from the PBC clock. More... | |
| static void | sysclk_enable_pbd_module (uint32_t module_index) |
| Enable a module clock derived from the PBD clock. More... | |
| static void | sysclk_disable_pbd_module (uint32_t module_index) |
| Disable a module clock derived from the PBD clock. More... | |
| static void | sysclk_enable_pba_divmask (uint32_t mask) |
| Enable divided clock mask derived from the PBA clock. More... | |
| static void | sysclk_disable_pba_divmask (uint32_t mask) |
| Disable divided clock mask derived from the PBA clock. More... | |
| void | sysclk_enable_peripheral_clock (const volatile void *module) |
| Enable a peripheral's clock from its base address. More... | |
| void | sysclk_disable_peripheral_clock (const volatile void *module) |
| Disable a peripheral's clock from its base address. More... | |
System Clock Source and Prescaler configuration | |
| void | sysclk_set_prescalers (uint32_t cpu_shift, uint32_t pba_shift, uint32_t pbb_shift, uint32_t pbc_shift, uint32_t pbd_shift) |
| Set system clock prescaler configuration. More... | |
| void | sysclk_set_source (uint32_t src) |
| Change the source of the main system clock. More... | |
System Clock Initialization | |
| void | sysclk_init (void) |
| Initialize the synchronous clock system. More... | |
1.8.5