ATPL230 Physical layer.
Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
Data Structures | |
| struct | atpl230_t |
| struct | atpl230ChnCfg_t |
| struct | xPhyMsgRx_t |
| struct | xPhyMsgTx_t |
| struct | xPhyMsgTxResult_t |
Macros | |
| #define | AES_128_KEY_SIZE 16 |
| AES 128 Key size. More... | |
| #define | ATPL230_VALID_CFG_KEY 0xBA |
| Valid chip configuration key. More... | |
| #define | ATPLCOUPXXX_NUM 9 |
| Coupling Boards Identifiers. More... | |
| #define | ID_TC_PHY_TX_OFFSET_SYM ID_TC0 |
| #define | MODE_EF10 0 |
| 10 MHz More... | |
| #define | MODE_EF20 1 |
| 20 MHz More... | |
| #define | MODE_EF40 2 |
| 40 MHz More... | |
| #define | MODE_NUM_EF 3 |
| Emitter Frecuencies Modes. More... | |
| #define | PHY_MAX_PPDU_SIZE 512 |
| Maximum physical pdu size. More... | |
| #define | PHY_NUM_CHANNELS 8 |
| Configuration Identifiers. More... | |
| #define | PHY_NUM_RX_BUFFERS 4 |
| Number of reception buffers. More... | |
| #define | PHY_NUM_TX_BUFFERS 4 |
| Number of transmission buffers. More... | |
| #define | TC_PHY_TX_OFFSET_SYM TC0 |
| #define | TC_PHY_TX_OFFSET_SYM_CHN 0 |
| #define | TC_PHY_TX_OFFSET_SYM_Handler TC0_Handler |
| #define | TC_PHY_TX_OFFSET_SYM_IRQn TC0_IRQn |
Coupling Board Definitions | |
| #define | ATPLCOUP000_v1 0x01 |
| #define | ATPLCOUP000_v2 0x02 |
| #define | ATPLCOUP001_v1 0x11 |
| #define | ATPLCOUP002_v1 0x21 |
| #define | ATPLCOUP002_v2 0x22 |
| #define | ATPLCOUP003_v1 0x31 |
| #define | ATPLCOUP004_v1 0x41 |
| #define | ATPLCOUP005_v1 0x51 |
| #define | ATPLCOUP006_v1 0x61 |
Phy layer reset Types | |
| #define | PHY_RESET_HARD_TYPE 0 |
| #define | PHY_RESET_SOFT_TYPE 1 |
Identifier for channel Configuration | |
| #define | PHY_ID_TX_CHN1 0x000150C7 |
| #define | PHY_ID_TX_CHN2 0x00026A44 |
| #define | PHY_ID_TX_CHN3 0x000383C1 |
| #define | PHY_ID_TX_CHN4 0x00049D3D |
| #define | PHY_ID_TX_CHN5 0x0005B6BA |
| #define | PHY_ID_TX_CHN6 0x0006D036 |
| #define | PHY_ID_TX_CHN7 0x0007E9B3 |
| #define | PHY_ID_TX_CHN8 0x00090330 |
Commands to access configuration parameters | |
| #define | PHY_CMD_CFG_READ 0 |
| Read operation. More... | |
| #define | PHY_CMD_CFG_WRITE 1 |
| Write operation. More... | |
| #define | PHY_CMD_CFG_AND 2 |
| AND operation. More... | |
| #define | PHY_CMD_CFG_OR 3 |
| OR operation. More... | |
| #define | PHY_CMD_CFG_XOR 4 |
| XOR operation. More... | |
Impedance states | |
| #define | HI_STATE 0 |
| High Impedance. More... | |
| #define | LO_STATE 1 |
| Low Impedance. More... | |
| #define | VLO_STATE 2 |
| Very Low Impedance. More... | |
| #define | LO_STATE_PK 3 |
| Low Impedance + Peak Cut On. More... | |
Header Type | |
| #define | PHY_HT_GENERIC 0 |
| Header type: GENERIC PACKET. More... | |
| #define | PHY_HT_PROMOTION 1 |
| Header type: PROMOTION PACKET. More... | |
| #define | PHY_HT_BEACON 2 |
| Header type: BEACON PACKET. More... | |
Protocol values | |
| #define | PROTOCOL_DBPSK 0x00 |
| Modulation scheme of the payload: Differential BPSK. More... | |
| #define | PROTOCOL_DQPSK 0x01 |
| Modulation scheme of the payload: Differential QPSK. More... | |
| #define | PROTOCOL_D8PSK 0x02 |
| Modulation scheme of the payload: Differential 8PSK. More... | |
| #define | PROTOCOL_DBPSK_VTB 0x04 |
| Modulation scheme of the payload: Differential BPSK with Convolutional Coding. More... | |
| #define | PROTOCOL_DQPSK_VTB 0x05 |
| Modulation scheme of the payload: Differential QPSK with Convolutional Coding. More... | |
| #define | PROTOCOL_D8PSK_VTB 0x06 |
| Modulation scheme of the payload: Differential 8PSK with Convolutional Coding. More... | |
| #define | PROTOCOL_DBPSK_ROBO 0x0C |
| Modulation scheme of the payload: Differential BPSK with ROBO Mode. More... | |
| #define | PROTOCOL_DQPSK_ROBO 0x0D |
| Modulation scheme of the payload: Differential QPSK with ROBO Mode. More... | |
Emitter Driver Mode | |
| #define | INTERNAL_DRV_MODE 1 |
| INTERNAL DRIVER. More... | |
| #define | EXTERNAL_DRV_MODE 2 |
| EXTERNAL DRIVER. More... | |
Driver Identification | |
| #define | DRIVER_1 1 |
| DRIVER 1. More... | |
| #define | DRIVER_2 2 |
| DRIVER 2. More... | |
| #define | DRIVER_1_2 3 |
| DRIVER 1 + 2. More... | |
Driver Polarity | |
| #define | DRV_POL_TX_0_RX_1 0 |
| 0 in emission and 1 in reception More... | |
| #define | DRV_POL_TX_1_RX_0 1 |
| 1 in emission and 0 in reception More... | |
Mode values | |
| #define | MODE_TYPE_A 0x00 |
| TYPE A FRAME. More... | |
| #define | MODE_TYPE_B 0x02 |
| TYPE B FRAME. More... | |
| #define | MODE_TYPE_BC 0x03 |
| TYPE BACKWARDS COMPATIBILTY FRAME. More... | |
| #define | MODE_NOISE 0xFE |
| Noise. More... | |
| #define | MODE_TEST 0xFF |
| Test. More... | |
TX scheduling mode values | |
| #define | PHY_TX_SCHEDULING_MODE_ABSOLUTE 0 |
| Absolute TX scheduling mode (absolute TX time specified) More... | |
| #define | PHY_TX_SCHEDULING_MODE_RELATIVE 1 |
| Relative TX scheduling mode (delay for TX time specified) More... | |
TX Result values | |
| #define | PHY_TX_RESULT_PROCESS ATPL230_TXRXBUF_RESULT_INPROCESS |
| Transmission result: already in process. More... | |
| #define | PHY_TX_RESULT_SUCCESS ATPL230_TXRXBUF_RESULT_SUCCESSFUL |
| Transmission result: end successfully. More... | |
| #define | PHY_TX_RESULT_INV_LENGTH ATPL230_TXRXBUF_RESULT_WRONG_LEN |
| Transmission result: invalid length error. More... | |
| #define | PHY_TX_RESULT_BUSY_CH ATPL230_TXRXBUF_RESULT_BUSY_CHANNEL |
| Transmission result: busy channel error. More... | |
| #define | PHY_TX_RESULT_BUSY_TX ATPL230_TXRXBUF_RESULT_PREV_TX_INPROCESS |
| Transmission result: busy transmission error. More... | |
| #define | PHY_TX_RESULT_BUSY_RX ATPL230_TXRXBUF_RESULT_RX_INPROCESS |
| Transmission result: busy reception error. More... | |
| #define | PHY_TX_RESULT_INV_SCHEME ATPL230_TXRXBUF_RESULT_INVALID_SCHEME |
| Transmission result: invalid scheme error. More... | |
| #define | PHY_TX_RESULT_TIMEOUT ATPL230_TXRXBUF_RESULT_TIMEOUT |
| Transmission result: timeout error. More... | |
| #define | PHY_TX_RESULT_INV_BUFFER 8 |
| Transmission result: invalid buffer identifier error. More... | |
| #define | PHY_TX_RESULT_INV_PRIME_MODE 9 |
| Transmission result: invalid Prime Mode error. More... | |
Configuration errors | |
| #define | PHY_CFG_SUCCESS 0 |
| Set configuration result: success. More... | |
| #define | PHY_CFG_INVALID_INPUT 1 |
| Set configuration result: invalid input error or read only. More... | |
| #define | PHY_CFG_READ_ONLY 2 |
| Set configuration result: read only. More... | |
| #define | PHY_CFG_INVALID_CHANNEL 3 |
| Set configuration result: invalid channel. More... | |
| #define | PHY_CFG_GEN_ERR_INVALID_AES_ENABLE 4 |
| Set configuration result: AES not available. More... | |
Configuration Parameters | |
| #define | PHY_ID_INFO_PRODUCT 0x0100 |
| Product identifier. More... | |
| #define | PHY_ID_INFO_MODEL 0x010A |
| Model identifier. More... | |
| #define | PHY_ID_INFO_VERSION 0x010C |
| Version identifier. More... | |
| #define | PHY_ID_RX_BUFFER_ID 0x0111 |
| Buffer identifier of received message. More... | |
| #define | PHY_ID_RX_QR_MODE_ID 0x0112 |
| Flag to enable / disable Rx Quality Report Mode. More... | |
| #define | PHY_ID_RX_INFO_SCHEME 0x0113 |
| Modulation Scheme of last received message. More... | |
| #define | PHY_ID_RX_INFO_HEADER_RCV 0x0114 |
| Flag to indicate if header has already been received. More... | |
| #define | PHY_ID_RX_INFO_MODE 0x0115 |
| Payload length in OFDM symbols. More... | |
| #define | PHY_ID_TX_BUFFER_ID 0x0117 |
| Buffer identifier of transmitted message. More... | |
| #define | PHY_ID_TX_INFO_LEVEL 0x0118 |
| Level parameter of last transmitted message. More... | |
| #define | PHY_ID_TX_INFO_SCHEME 0x0119 |
| Modulation scheme of last transmitted message. More... | |
| #define | PHY_ID_TX_QR_MODE_ID 0x011A |
| Flag to enable / disable Tx Quality Report Mode. More... | |
| #define | PHY_ID_TX_INFO_MODE 0x011B |
| Mode PRIME v1.3, PRIME v1.4 or PRIME v1.4 backward compatible. More... | |
| #define | PHY_ID_TX_INFO_DISABLE_RX 0x011C |
| Flag to enable / disable reception at transmission start. More... | |
| #define | PHY_ID_RX_PAYLOAD_LEN 0x011E |
| RX Payload length in bytes. More... | |
| #define | PHY_ID_RX_PAYLOAD_LEN_SYM 0x0120 |
| RX Payload length in OFDM symbols. More... | |
| #define | PHY_ID_TX_PAYLOAD_LEN_SYM 0x0122 |
| TX Payload length in OFDM symbols. More... | |
| #define | PHY_ID_TX_INFO_TDELAY 0x0128 |
| Delay for transmission in 10's of us. More... | |
| #define | PHY_ID_STATS_TX_TOTAL 0x012C |
| Transmitted correctly messages count. More... | |
| #define | PHY_ID_STATS_TX_TOTAL_BYTES 0x0130 |
| Transmitted bytes count. More... | |
| #define | PHY_ID_STATS_TX_TOTAL_ERRORS 0x0134 |
| Transmission errors count. More... | |
| #define | PHY_ID_STATS_TX_BAD_BUSY_TX 0x0138 |
| Already in transmission. More... | |
| #define | PHY_ID_STATS_TX_BAD_BUSY_CHANNEL 0x013C |
| Transmission failure owing to busy channel. More... | |
| #define | PHY_ID_STATS_TX_BAD_LEN 0x0140 |
| Bad len in message (too short - too long) More... | |
| #define | PHY_ID_STATS_TX_BAD_FORMAT 0x0144 |
| Message to transmit in bad format. More... | |
| #define | PHY_ID_STATS_TX_TIMEOUT 0x0148 |
| Timeout error in transmission. More... | |
| #define | PHY_ID_STATS_RX_TOTAL 0x014C |
| Received correctly messages count. More... | |
| #define | PHY_ID_STATS_RX_TOTAL_BYTES 0x0150 |
| Received bytes count. More... | |
| #define | PHY_ID_STATS_RX_TOTAL_ERRORS 0x0154 |
| Reception errors count. More... | |
| #define | PHY_ID_STATS_RX_BAD_LEN 0x0158 |
| Bad len in message (too short - too long) More... | |
| #define | PHY_ID_STATS_RX_BAD_CRC 0x015C |
| Bad CRC in received message. More... | |
| #define | PHY_ID_TX_ATT_GLOBAL 0x0200 |
| Global attenuation. More... | |
| #define | PHY_ID_TX1_ATT_CHIRP_HIGHZ 0x0202 |
| Channel_1 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX1_ATT_SIGNAL_HIGHZ 0x0203 |
| Channel_1 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX1_ATT_CHIRP_LOWZ 0x0204 |
| Channel_1 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX1_ATT_SIGNAL_LOWZ 0x0205 |
| Channel_1 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX1_ATT_CHIRP_VLOWZ 0x0206 |
| Channel_1 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX1_ATT_SIGNAL_VLOWZ 0x0207 |
| Channel_1 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX1_LOAD_THRESHOLD1 0x0208 |
| Channel_1 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX1_LOAD_THRESHOLD2 0x020A |
| Channel_1 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX1_LOAD_THRESHOLD3 0x020C |
| Channel_1 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX1_LOAD_THRESHOLD4 0x020E |
| Channel_1 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX2_ATT_CHIRP_HIGHZ 0x0210 |
| Channel_2 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX2_ATT_SIGNAL_HIGHZ 0x0211 |
| Channel_2 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX2_ATT_CHIRP_LOWZ 0x0212 |
| Channel_2 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX2_ATT_SIGNAL_LOWZ 0x0213 |
| Channel_2 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX2_ATT_CHIRP_VLOWZ 0x0214 |
| Channel_2 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX2_ATT_SIGNAL_VLOWZ 0x0215 |
| Channel_2 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX2_LOAD_THRESHOLD1 0x0216 |
| Channel_2 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX2_LOAD_THRESHOLD2 0x0218 |
| Channel_2 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX2_LOAD_THRESHOLD3 0x021A |
| Channel_2 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX2_LOAD_THRESHOLD4 0x021C |
| Channel_2 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX3_ATT_CHIRP_HIGHZ 0x021E |
| Channel_3 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX3_ATT_SIGNAL_HIGHZ 0x021F |
| Channel_3 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX3_ATT_CHIRP_LOWZ 0x0220 |
| Channel_3 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX3_ATT_SIGNAL_LOWZ 0x0221 |
| Channel_3 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX3_ATT_CHIRP_VLOWZ 0x0222 |
| Channel_3 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX3_ATT_SIGNAL_VLOWZ 0x0223 |
| Channel_3 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX3_LOAD_THRESHOLD1 0x0224 |
| Channel_3 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX3_LOAD_THRESHOLD2 0x0226 |
| Channel_3 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX3_LOAD_THRESHOLD3 0x0228 |
| Channel_3 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX3_LOAD_THRESHOLD4 0x022A |
| Channel_3 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX4_ATT_CHIRP_HIGHZ 0x022C |
| Channel_4 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX4_ATT_SIGNAL_HIGHZ 0x022D |
| Channel_4 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX4_ATT_CHIRP_LOWZ 0x022E |
| Channel_4 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX4_ATT_SIGNAL_LOWZ 0x022F |
| Channel_4 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX4_ATT_CHIRP_VLOWZ 0x0230 |
| Channel_4 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX4_ATT_SIGNAL_VLOWZ 0x0231 |
| Channel_4 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX4_LOAD_THRESHOLD1 0x0232 |
| Channel_4 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX4_LOAD_THRESHOLD2 0x0234 |
| Channel_4 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX4_LOAD_THRESHOLD3 0x0236 |
| Channel_4 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX4_LOAD_THRESHOLD4 0x0238 |
| Channel_4 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX5_ATT_CHIRP_HIGHZ 0x023A |
| Channel_5 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX5_ATT_SIGNAL_HIGHZ 0x023B |
| Channel_5 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX5_ATT_CHIRP_LOWZ 0x023C |
| Channel_5 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX5_ATT_SIGNAL_LOWZ 0x023D |
| Channel_5 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX5_ATT_CHIRP_VLOWZ 0x023E |
| Channel_5 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX5_ATT_SIGNAL_VLOWZ 0x023F |
| Channel_5 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX5_LOAD_THRESHOLD1 0x0240 |
| Channel_5 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX5_LOAD_THRESHOLD2 0x0242 |
| Channel_5 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX5_LOAD_THRESHOLD3 0x0244 |
| Channel_5 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX5_LOAD_THRESHOLD4 0x0246 |
| Channel_5 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX6_ATT_CHIRP_HIGHZ 0x0248 |
| Channel_6 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX6_ATT_SIGNAL_HIGHZ 0x0249 |
| Channel_6 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX6_ATT_CHIRP_LOWZ 0x024A |
| Channel_6 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX6_ATT_SIGNAL_LOWZ 0x024B |
| Channel_6 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX6_ATT_CHIRP_VLOWZ 0x024C |
| Channel_6 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX6_ATT_SIGNAL_VLOWZ 0x024D |
| Channel_6 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX6_LOAD_THRESHOLD1 0x024E |
| Channel_6 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX6_LOAD_THRESHOLD2 0x0250 |
| Channel_6 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX6_LOAD_THRESHOLD3 0x0252 |
| Channel_6 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX6_LOAD_THRESHOLD4 0x0254 |
| Channel_6 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX7_ATT_CHIRP_HIGHZ 0x0256 |
| Channel_7 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX7_ATT_SIGNAL_HIGHZ 0x0257 |
| Channel_7 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX7_ATT_CHIRP_LOWZ 0x0258 |
| Channel_7 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX7_ATT_SIGNAL_LOWZ 0x0259 |
| Channel_7 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX7_ATT_CHIRP_VLOWZ 0x025A |
| Channel_7 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX7_ATT_SIGNAL_VLOWZ 0x025B |
| Channel_7 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX7_LOAD_THRESHOLD1 0x025C |
| Channel_7 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX7_LOAD_THRESHOLD2 0x025E |
| Channel_7 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX7_LOAD_THRESHOLD3 0x0260 |
| Channel_7 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX7_LOAD_THRESHOLD4 0x0262 |
| Channel_7 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX8_ATT_CHIRP_HIGHZ 0x0264 |
| Channel_8 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX8_ATT_SIGNAL_HIGHZ 0x0265 |
| Channel_8 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX8_ATT_CHIRP_LOWZ 0x0266 |
| Channel_8 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX8_ATT_SIGNAL_LOWZ 0x0267 |
| Channel_8 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX8_ATT_CHIRP_VLOWZ 0x0268 |
| Channel_8 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX8_ATT_SIGNAL_VLOWZ 0x0269 |
| Channel_8 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX8_LOAD_THRESHOLD1 0x026A |
| Channel_8 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX8_LOAD_THRESHOLD2 0x026C |
| Channel_8 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX8_LOAD_THRESHOLD3 0x026E |
| Channel_8 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX8_LOAD_THRESHOLD4 0x0270 |
| Channel_8 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_CFG_DRIVER1_MODE 0x0400 |
| Flag to indicate if driver 1 is extern driver (1) or intern driver (0) More... | |
| #define | PHY_ID_CFG_DRIVER2_MODE 0x0401 |
| Flag to indicate if driver 2 is extern driver (1) or intern driver (0) More... | |
| #define | PHY_ID_CFG_TXRX1_POLARITY 0x0402 |
| Flag to indicate if txrx1 polarity is high or low active. More... | |
| #define | PHY_ID_CFG_TXRX2_POLARITY 0x0403 |
| Flag to indicate if txrx2 polarity is high or low active. More... | |
| #define | PHY_ID_CFG_AUTODETECT_BRANCH 0x0404 |
| Flag to enable branch auto detection. More... | |
| #define | PHY_ID_CFG_IMPEDANCE 0x0405 |
| When branch auto detection disabled, indicate impedance to use. More... | |
| #define | PHY_ID_CFG_HIGH_Z_DRIVER 0x0406 |
| Select driver for high impedance. More... | |
| #define | PHY_ID_CFG_LOW_Z_DRIVER 0x0407 |
| Select driver for high impedance. More... | |
| #define | PHY_ID_CFG_VLOW_Z_DRIVER 0x0408 |
| Select driver for high impedance. More... | |
| #define | PHY_ID_CFG_AGC0_KRSSI_OFFSET 0x0409 |
| Offset for received signal strength (rssi) according to AGC 0 configuration. More... | |
| #define | PHY_ID_CFG_AGC1_KRSSI_OFFSET 0x040A |
| Offset for received signal strength (rssi) according to AGC 1 configuration. More... | |
| #define | PHY_ID_CFG_AGC2_KRSSI_OFFSET 0x040B |
| Offset for received signal strength (rssi) according to AGC 2 configuration. More... | |
| #define | PHY_ID_CFG_AGC3_KRSSI_OFFSET 0x040C |
| Offset for received signal strength (rssi) according to AGC 3 configuration. More... | |
| #define | PHY_ID_CFG_N1_DELAY 0x040D |
| N1 Delay. More... | |
| #define | PHY_ID_CFG_P1_DELAY 0x040E |
| P1 Delay. More... | |
| #define | PHY_ID_CFG_N2_DELAY 0x040F |
| N2 delay. More... | |
| #define | PHY_ID_CFG_P2_DELAY 0x0410 |
| P2 delay. More... | |
| #define | PHY_ID_CFG_EMIT1_ACTIVE 0x0411 |
| Emit 1 Active. More... | |
| #define | PHY_ID_CFG_EMIT2_ACTIVE 0x0412 |
| Emit 2 Active. More... | |
| #define | PHY_ID_CFG_EMIT3_ACTIVE 0x0413 |
| Emit 3 Active. More... | |
| #define | PHY_ID_CFG_EMIT4_ACTIVE 0x0414 |
| Emit 4 Active. More... | |
| #define | PHY_ID_CFG_TXRX_CHANNEL 0x0415 |
| Transmission/Reception Channel. More... | |
| #define | PHY_ID_CFG_COUPLING_BOARD 0x0416 |
| Coupling board in use. More... | |
| #define | PHY_ID_CFG_PRIME_MODE 0x0417 |
| PRIME mode (see mode values in atpl230.h) More... | |
| #define | PHY_ID_CFG_TIME_BEFORE_TX_HIGHZ 0x0418 |
| Time in 10's of us for HIMP pin before transmission with high impedance. More... | |
| #define | PHY_ID_CFG_TIME_BEFORE_TX_LOWZ 0x041A |
| Time in 10's of us for TXRX pin before transmission with low impedance. More... | |
| #define | PHY_ID_CFG_TIME_AFTER_TX_HIGHZ 0x041C |
| Time (unit depends on platform) for HIMP pin after transmission with high impedance. More... | |
| #define | PHY_ID_CFG_TIME_AFTER_TX_LOWZ 0x041E |
| Time (unit depends on platform) for TXRX pin after transmission with low impedance. More... | |
| #define | PHY_ID_CFG_RX_CORR_THRESHOLD 0x0420 |
| Threshold for autocorrelation filter. More... | |
| #define | PHY_ID_CFG_ENABLE_VLOW_PK 0x0422 |
| Flag to enable Peak Cut On in case of low impedance. More... | |
Macros | |
| #define | ATPL230_REG_PARAM(val) (val & 0xF000) |
| #define | ATPL230_CFG_PARAM(val) (val & 0xF400) |
| #define | ATPL230_ATT_PARAM(val) (val & 0xF200) |
| #define | ATPL230_PARAM(val) (val & 0xF100) |
| #define | ATPL230_REG_PARAM_MSK 0xF000 |
| #define | ATPL230_CFG_PARAM_MSK 0x0400 |
| #define | ATPL230_ATT_PARAM_MSK 0x0200 |
| #define | ATPL230_PARAM_MSK 0x0100 |
| #define | ATPL230_GET_HEADER_TYPE(val) ((val >> 4) & 0x03) |
| #define | ATPL230_GET_SFR_BCH_ERR(val) (val & ATPL230_SFR_BCH_ERR_Msk) |
| #define | ATPL230_GET_SFR_ERR_PYL(val) (val & ATPL230_SFR_ERR_PYL_Msk) |
| #define | ATPL230_GET_SFR_CD(val) (val & ATPL230_SFR_CD_Msk) |
| #define | ATPL230_GET_SFR_UMD(val) (val & ATPL230_SFR_UMD_Msk) |
| #define | ATPL230_GET_TXINT_TX0(val) (val & ATPL230_TXRXBUF_TX_INT_TX0_Msk) |
| #define | ATPL230_GET_TXINT_TX1(val) (val & ATPL230_TXRXBUF_TX_INT_TX1_Msk) |
| #define | ATPL230_GET_TXINT_TX2(val) (val & ATPL230_TXRXBUF_TX_INT_TX2_Msk) |
| #define | ATPL230_GET_TXINT_TX3(val) (val & ATPL230_TXRXBUF_TX_INT_TX3_Msk) |
| #define | ATPL230_GET_RXINT_PRX0(val) (val & ATPL230_TXRXBUF_RX_INT_PRX0_Msk) |
| #define | ATPL230_GET_RXINT_PRX1(val) (val & ATPL230_TXRXBUF_RX_INT_PRX1_Msk) |
| #define | ATPL230_GET_RXINT_PRX2(val) (val & ATPL230_TXRXBUF_RX_INT_PRX2_Msk) |
| #define | ATPL230_GET_RXINT_PRX3(val) (val & ATPL230_TXRXBUF_RX_INT_PRX3_Msk) |
| #define | ATPL230_GET_RXINT_HRX0(val) (val & ATPL230_TXRXBUF_RX_INT_HRX0_Msk) |
| #define | ATPL230_GET_RXINT_HRX1(val) (val & ATPL230_TXRXBUF_RX_INT_HRX1_Msk) |
| #define | ATPL230_GET_RXINT_HRX2(val) (val & ATPL230_TXRXBUF_RX_INT_HRX2_Msk) |
| #define | ATPL230_GET_RXINT_HRX3(val) (val & ATPL230_TXRXBUF_RX_INT_HRX3_Msk) |
| #define | ATPL230_GET_TX_RESULT_TX0(val) ((val & ATPL230_TXRXBUF_RESULT_TX0_Msk)>>ATPL230_TXRXBUF_RESULT_TX0_Pos) |
| #define | ATPL230_GET_TX_RESULT_TX1(val) ((val & ATPL230_TXRXBUF_RESULT_TX1_Msk)>>ATPL230_TXRXBUF_RESULT_TX1_Pos) |
| #define | ATPL230_GET_TX_RESULT_TX2(val) ((val & ATPL230_TXRXBUF_RESULT_TX2_Msk)>>ATPL230_TXRXBUF_RESULT_TX2_Pos) |
| #define | ATPL230_GET_TX_RESULT_TX3(val) ((val & ATPL230_TXRXBUF_RESULT_TX3_Msk)>>ATPL230_TXRXBUF_RESULT_TX3_Pos) |
| #define | ATPL230_GET_ROBO_MODE_RX(id, val) (val >> (id<<1)) & ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX0_Msk; |
| #define | ATPL230_GET_NOISE_RESULT(val) ((val & ATPL230_TXRXBUF_NOISECONF_ETN_Msk)>>ATPL230_TXRXBUF_NOISECONF_ETN_Pos) |
| #define | ATPL230_GET_NOISE_NS(val) (val & ATPL230_TXRXBUF_NOISECONF_NS_Msk) |
Serialization Addons | |
| #define | DISABLE_SERIAL 0 |
| #define | SERIAL_IF_ENABLE 0x1 |
| #define | SNIFFER_IF_ENABLE 0x2 |
Enumerations | |
CRC types | |
| enum | VCRCTypes { CRC_TYPE_8 = 0, CRC_TYPE_16 = 1, CRC_TYPE_24 = 2, CRC_TYPE_32 = 3 } |
Functions | |
| static void | phy_carrier_detect_buff_disable (uint8_t idBuf) |
| Disable carrier detect in specific buffer. More... | |
| static void | phy_carrier_detect_buff_enable (uint8_t idBuf) |
| Enable carrier detect in specific buffer. More... | |
| static void | phy_carrier_detect_disable (void) |
| Disable Carrier Detect. More... | |
| static void | phy_carrier_detect_enable (void) |
| Enable Carrier Detect. More... | |
| static void | phy_clear_global_interrupt (void) |
| Clear global interruption. More... | |
| static void | phy_clear_sfr_err (void) |
| Clear PHY SFR -1. More... | |
| static void | phy_force_tx_buff_disable (uint8_t idBuf) |
| Disable forced transmission in specific buffer. More... | |
| static void | phy_force_tx_buff_enable (uint8_t idBuf) |
| Enable forced transmission in specific buffer. More... | |
| static uint8_t | phy_get_carrier_detect (void) |
| Get Carrier Detect. More... | |
| static uint8_t | phy_get_mac_en (void) |
| Get MAC coproc. More... | |
| static uint8_t | phy_get_sfr_err (void) |
| Get PHY SFR -1 flag. More... | |
| static void | phy_mac_crc_disable (void) |
| Disable MAC CRC processing. More... | |
| static void | phy_mac_crc_enable (void) |
| Enable MAC CRC processing. More... | |
| static void | phy_reception_buff_disable (uint8_t idBuf) |
| Disable reception in specific buffer. More... | |
| static void | phy_reception_buff_enable (uint8_t idBuf) |
| Enable reception in specific buffer. More... | |
| static void | phy_transmission_buff_disable (uint8_t idBuf) |
| Disable transmission in specific buffer. More... | |
| static uint8_t | phy_transmission_buff_is_enable (uint8_t idBuf) |
| Get status of specific buffer. More... | |
ATPL230 Physical Layer Interface | |
| void | phy_init (uint8_t uc_ifaceEnable) |
| Create PHY tasks, queues and semaphores Initialize physical parameters and configure ATPL230 device. More... | |
| uint8_t | phy_get_cfg_param (uint16_t us_id, void *p_val, uint16_t uc_len) |
| Get PHY layer parameter. More... | |
| uint8_t | phy_set_cfg_param (uint16_t us_id, void *p_val, uint16_t uc_len) |
| Set PHY layer parameter. More... | |
| uint8_t | phy_cmd_cfg_param (uint16_t us_id, uint8_t uc_cmd, uint8_t uc_mask) |
| Set PHY layer parameter. More... | |
| uint8_t | phy_tx_frame (xPhyMsgTx_t *px_msg) |
| Write the transmitted data with ATPL230 device. More... | |
| void | phy_rx_frame_cb (xPhyMsgRx_t *px_msg) |
| Read the received data with ATPL230 device. More... | |
| void | phy_tx_frame_result_cb (xPhyMsgTxResult_t *px_tx_result) |
| Task to process TX PLC. More... | |
| void | phy_reset (uint8_t uc_reset_type) |
| Reset PHY layer including pplc service and serial ifaces Initialize physical parameters and configure ATPL230 device. More... | |
1.8.5