This module provides configuration and utils for the PLC PHY layer interface.
Modules | |
| PLC PHY Serial Interface | |
| This module provides configuration and utils to serialize the PLC PHY layer. | |
| PLC PHY Sniffer | |
| This module provides configuration and utils for the sniffer in the PLC PHY layer. | |
Data Structures | |
| struct | atpl230_t |
| struct | atpl230ChnCfg_t |
| struct | xPhyMsgRx_t |
| struct | xPhyMsgTx_t |
| struct | xPhyMsgTxResult_t |
Functions | |
| static uint32_t | _get_crc (uint8_t uc_crc_type, uint8_t *puc_buf, uint16_t us_len, uint8_t uc_header_type) |
| Get CRC value from the buffer content. More... | |
| static void | _init_IIR_filter (void) |
| Filter IIR initialization. More... | |
| static void | _init_phy_layer (uint8_t uc_rst_type) |
| PHY init layer. More... | |
| static void | _phy_rx_task (void) |
| Task to process RX PLC. More... | |
| static void | _phy_tx_result_task (void) |
| Task to process TX PLC. More... | |
| static void | _reset_rx_flag_interrupt (uint8_t uc_buf_idx) |
| Reset reception interrupt. More... | |
| static void | _store_filter_sec (uint8_t *puc_fir_data, uint8_t uc_cmd, uint8_t uc_num_rows, uint8_t uc_way_mode, uint8_t uc_start_mem_byte, uint8_t uc_inv_mode) |
| Store Filter secuence. More... | |
| static void | _upd_sna_crc (uint8_t *puc_sna) |
| Update CRC of SNA. More... | |
| static uint8_t | _update_channel (uint8_t uc_channel) |
| Update channel in atpl230 device. More... | |
| static void | _update_emit1_mode (uint8_t uc_emode) |
| Update emit 1 mode in atpl230 device. More... | |
| static void | _update_emit2_mode (uint8_t uc_emode) |
| Update emit 2 mode in atpl230 device. More... | |
| static void | _update_txrx1_polarity (uint8_t uc_pol) |
| Update polarity of TXRX 1 in atpl230 device. More... | |
| static void | _update_txrx2_polarity (uint8_t uc_pol) |
| Update polarity of TXRX 2 in atpl230 device. More... | |
| void | Dummy_serial_if_init (void) |
| Dummy Phy Tester Tool Serialization Addon. More... | |
| void | Dummy_sniffer_if_init (uint8_t uc_enable_led) |
| Dummy Phy Sniffer Serialization Addon. More... | |
| static void | phy_carrier_detect_buff_disable (uint8_t idBuf) |
| Disable carrier detect in specific buffer. More... | |
| static void | phy_carrier_detect_buff_enable (uint8_t idBuf) |
| Enable carrier detect in specific buffer. More... | |
| static void | phy_carrier_detect_disable (void) |
| Disable Carrier Detect. More... | |
| static void | phy_carrier_detect_enable (void) |
| Enable Carrier Detect. More... | |
| static void | phy_clear_global_interrupt (void) |
| Clear global interruption. More... | |
| static void | phy_clear_sfr_err (void) |
| Clear PHY SFR -1. More... | |
| static void | phy_force_tx_buff_disable (uint8_t idBuf) |
| Disable forced transmission in specific buffer. More... | |
| static void | phy_force_tx_buff_enable (uint8_t idBuf) |
| Enable forced transmission in specific buffer. More... | |
| static uint8_t | phy_get_carrier_detect (void) |
| Get Carrier Detect. More... | |
| static uint8_t | phy_get_mac_en (void) |
| Get MAC coproc. More... | |
| static uint8_t | phy_get_sfr_err (void) |
| Get PHY SFR -1 flag. More... | |
| void | phy_handler (void) |
| PHY interrupt management. More... | |
| static void | phy_mac_crc_disable (void) |
| Disable MAC CRC processing. More... | |
| static void | phy_mac_crc_enable (void) |
| Enable MAC CRC processing. More... | |
| static void | phy_reception_buff_disable (uint8_t idBuf) |
| Disable reception in specific buffer. More... | |
| static void | phy_reception_buff_enable (uint8_t idBuf) |
| Enable reception in specific buffer. More... | |
| static void | phy_transmission_buff_disable (uint8_t idBuf) |
| Disable transmission in specific buffer. More... | |
| static uint8_t | phy_transmission_buff_is_enable (uint8_t idBuf) |
| Get status of specific buffer. More... | |
Coupling Board Definitions | |
| #define | ATPLCOUP000_v1 0x01 |
| #define | ATPLCOUP000_v2 0x02 |
| #define | ATPLCOUP001_v1 0x11 |
| #define | ATPLCOUP002_v1 0x21 |
| #define | ATPLCOUP002_v2 0x22 |
| #define | ATPLCOUP003_v1 0x31 |
| #define | ATPLCOUP004_v1 0x41 |
| #define | ATPLCOUP005_v1 0x51 |
| #define | ATPLCOUP006_v1 0x61 |
Phy layer reset Types | |
| #define | PHY_RESET_HARD_TYPE 0 |
| #define | PHY_RESET_SOFT_TYPE 1 |
Identifier for channel Configuration | |
| #define | PHY_ID_TX_CHN1 0x000150C7 |
| #define | PHY_ID_TX_CHN2 0x00026A44 |
| #define | PHY_ID_TX_CHN3 0x000383C1 |
| #define | PHY_ID_TX_CHN4 0x00049D3D |
| #define | PHY_ID_TX_CHN5 0x0005B6BA |
| #define | PHY_ID_TX_CHN6 0x0006D036 |
| #define | PHY_ID_TX_CHN7 0x0007E9B3 |
| #define | PHY_ID_TX_CHN8 0x00090330 |
Commands to access configuration parameters | |
| #define | PHY_CMD_CFG_READ 0 |
| Read operation. More... | |
| #define | PHY_CMD_CFG_WRITE 1 |
| Write operation. More... | |
| #define | PHY_CMD_CFG_AND 2 |
| AND operation. More... | |
| #define | PHY_CMD_CFG_OR 3 |
| OR operation. More... | |
| #define | PHY_CMD_CFG_XOR 4 |
| XOR operation. More... | |
Impedance states | |
| #define | HI_STATE 0 |
| High Impedance. More... | |
| #define | LO_STATE 1 |
| Low Impedance. More... | |
| #define | VLO_STATE 2 |
| Very Low Impedance. More... | |
| #define | LO_STATE_PK 3 |
| Low Impedance + Peak Cut On. More... | |
Header Type | |
| #define | PHY_HT_GENERIC 0 |
| Header type: GENERIC PACKET. More... | |
| #define | PHY_HT_PROMOTION 1 |
| Header type: PROMOTION PACKET. More... | |
| #define | PHY_HT_BEACON 2 |
| Header type: BEACON PACKET. More... | |
CRC types | |
| enum | VCRCTypes { CRC_TYPE_8 = 0, CRC_TYPE_16 = 1, CRC_TYPE_24 = 2, CRC_TYPE_32 = 3 } |
Protocol values | |
| #define | PROTOCOL_DBPSK 0x00 |
| Modulation scheme of the payload: Differential BPSK. More... | |
| #define | PROTOCOL_DQPSK 0x01 |
| Modulation scheme of the payload: Differential QPSK. More... | |
| #define | PROTOCOL_D8PSK 0x02 |
| Modulation scheme of the payload: Differential 8PSK. More... | |
| #define | PROTOCOL_DBPSK_VTB 0x04 |
| Modulation scheme of the payload: Differential BPSK with Convolutional Coding. More... | |
| #define | PROTOCOL_DQPSK_VTB 0x05 |
| Modulation scheme of the payload: Differential QPSK with Convolutional Coding. More... | |
| #define | PROTOCOL_D8PSK_VTB 0x06 |
| Modulation scheme of the payload: Differential 8PSK with Convolutional Coding. More... | |
| #define | PROTOCOL_DBPSK_ROBO 0x0C |
| Modulation scheme of the payload: Differential BPSK with ROBO Mode. More... | |
| #define | PROTOCOL_DQPSK_ROBO 0x0D |
| Modulation scheme of the payload: Differential QPSK with ROBO Mode. More... | |
Emitter Driver Mode | |
| #define | INTERNAL_DRV_MODE 1 |
| INTERNAL DRIVER. More... | |
| #define | EXTERNAL_DRV_MODE 2 |
| EXTERNAL DRIVER. More... | |
Driver Identification | |
| #define | DRIVER_1 1 |
| DRIVER 1. More... | |
| #define | DRIVER_2 2 |
| DRIVER 2. More... | |
| #define | DRIVER_1_2 3 |
| DRIVER 1 + 2. More... | |
Driver Polarity | |
| #define | DRV_POL_TX_0_RX_1 0 |
| 0 in emission and 1 in reception More... | |
| #define | DRV_POL_TX_1_RX_0 1 |
| 1 in emission and 0 in reception More... | |
Mode values | |
| #define | MODE_TYPE_A 0x00 |
| TYPE A FRAME. More... | |
| #define | MODE_TYPE_B 0x02 |
| TYPE B FRAME. More... | |
| #define | MODE_TYPE_BC 0x03 |
| TYPE BACKWARDS COMPATIBILTY FRAME. More... | |
| #define | MODE_NOISE 0xFE |
| Noise. More... | |
| #define | MODE_TEST 0xFF |
| Test. More... | |
TX scheduling mode values | |
| #define | PHY_TX_SCHEDULING_MODE_ABSOLUTE 0 |
| Absolute TX scheduling mode (absolute TX time specified) More... | |
| #define | PHY_TX_SCHEDULING_MODE_RELATIVE 1 |
| Relative TX scheduling mode (delay for TX time specified) More... | |
Configuration errors | |
| #define | PHY_CFG_SUCCESS 0 |
| Set configuration result: success. More... | |
| #define | PHY_CFG_INVALID_INPUT 1 |
| Set configuration result: invalid input error or read only. More... | |
| #define | PHY_CFG_READ_ONLY 2 |
| Set configuration result: read only. More... | |
| #define | PHY_CFG_INVALID_CHANNEL 3 |
| Set configuration result: invalid channel. More... | |
| #define | PHY_CFG_GEN_ERR_INVALID_AES_ENABLE 4 |
| Set configuration result: AES not available. More... | |
Configuration Parameters | |
| #define | PHY_ID_INFO_PRODUCT 0x0100 |
| Product identifier. More... | |
| #define | PHY_ID_INFO_MODEL 0x010A |
| Model identifier. More... | |
| #define | PHY_ID_INFO_VERSION 0x010C |
| Version identifier. More... | |
| #define | PHY_ID_RX_BUFFER_ID 0x0111 |
| Buffer identifier of received message. More... | |
| #define | PHY_ID_RX_QR_MODE_ID 0x0112 |
| Flag to enable / disable Rx Quality Report Mode. More... | |
| #define | PHY_ID_RX_INFO_SCHEME 0x0113 |
| Modulation Scheme of last received message. More... | |
| #define | PHY_ID_RX_INFO_HEADER_RCV 0x0114 |
| Flag to indicate if header has already been received. More... | |
| #define | PHY_ID_RX_INFO_MODE 0x0115 |
| Payload length in OFDM symbols. More... | |
| #define | PHY_ID_TX_BUFFER_ID 0x0117 |
| Buffer identifier of transmitted message. More... | |
| #define | PHY_ID_TX_INFO_LEVEL 0x0118 |
| Level parameter of last transmitted message. More... | |
| #define | PHY_ID_TX_INFO_SCHEME 0x0119 |
| Modulation scheme of last transmitted message. More... | |
| #define | PHY_ID_TX_QR_MODE_ID 0x011A |
| Flag to enable / disable Tx Quality Report Mode. More... | |
| #define | PHY_ID_TX_INFO_MODE 0x011B |
| Mode PRIME v1.3, PRIME v1.4 or PRIME v1.4 backward compatible. More... | |
| #define | PHY_ID_TX_INFO_DISABLE_RX 0x011C |
| Flag to enable / disable reception at transmission start. More... | |
| #define | PHY_ID_RX_PAYLOAD_LEN 0x011E |
| RX Payload length in bytes. More... | |
| #define | PHY_ID_RX_PAYLOAD_LEN_SYM 0x0120 |
| RX Payload length in OFDM symbols. More... | |
| #define | PHY_ID_TX_PAYLOAD_LEN_SYM 0x0122 |
| TX Payload length in OFDM symbols. More... | |
| #define | PHY_ID_TX_INFO_TDELAY 0x0128 |
| Delay for transmission in 10's of us. More... | |
| #define | PHY_ID_STATS_TX_TOTAL 0x012C |
| Transmitted correctly messages count. More... | |
| #define | PHY_ID_STATS_TX_TOTAL_BYTES 0x0130 |
| Transmitted bytes count. More... | |
| #define | PHY_ID_STATS_TX_TOTAL_ERRORS 0x0134 |
| Transmission errors count. More... | |
| #define | PHY_ID_STATS_TX_BAD_BUSY_TX 0x0138 |
| Already in transmission. More... | |
| #define | PHY_ID_STATS_TX_BAD_BUSY_CHANNEL 0x013C |
| Transmission failure owing to busy channel. More... | |
| #define | PHY_ID_STATS_TX_BAD_LEN 0x0140 |
| Bad len in message (too short - too long) More... | |
| #define | PHY_ID_STATS_TX_BAD_FORMAT 0x0144 |
| Message to transmit in bad format. More... | |
| #define | PHY_ID_STATS_TX_TIMEOUT 0x0148 |
| Timeout error in transmission. More... | |
| #define | PHY_ID_STATS_RX_TOTAL 0x014C |
| Received correctly messages count. More... | |
| #define | PHY_ID_STATS_RX_TOTAL_BYTES 0x0150 |
| Received bytes count. More... | |
| #define | PHY_ID_STATS_RX_TOTAL_ERRORS 0x0154 |
| Reception errors count. More... | |
| #define | PHY_ID_STATS_RX_BAD_LEN 0x0158 |
| Bad len in message (too short - too long) More... | |
| #define | PHY_ID_STATS_RX_BAD_CRC 0x015C |
| Bad CRC in received message. More... | |
| #define | PHY_ID_TX_ATT_GLOBAL 0x0200 |
| Global attenuation. More... | |
| #define | PHY_ID_TX1_ATT_CHIRP_HIGHZ 0x0202 |
| Channel_1 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX1_ATT_SIGNAL_HIGHZ 0x0203 |
| Channel_1 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX1_ATT_CHIRP_LOWZ 0x0204 |
| Channel_1 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX1_ATT_SIGNAL_LOWZ 0x0205 |
| Channel_1 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX1_ATT_CHIRP_VLOWZ 0x0206 |
| Channel_1 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX1_ATT_SIGNAL_VLOWZ 0x0207 |
| Channel_1 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX1_LOAD_THRESHOLD1 0x0208 |
| Channel_1 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX1_LOAD_THRESHOLD2 0x020A |
| Channel_1 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX1_LOAD_THRESHOLD3 0x020C |
| Channel_1 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX1_LOAD_THRESHOLD4 0x020E |
| Channel_1 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX2_ATT_CHIRP_HIGHZ 0x0210 |
| Channel_2 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX2_ATT_SIGNAL_HIGHZ 0x0211 |
| Channel_2 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX2_ATT_CHIRP_LOWZ 0x0212 |
| Channel_2 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX2_ATT_SIGNAL_LOWZ 0x0213 |
| Channel_2 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX2_ATT_CHIRP_VLOWZ 0x0214 |
| Channel_2 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX2_ATT_SIGNAL_VLOWZ 0x0215 |
| Channel_2 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX2_LOAD_THRESHOLD1 0x0216 |
| Channel_2 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX2_LOAD_THRESHOLD2 0x0218 |
| Channel_2 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX2_LOAD_THRESHOLD3 0x021A |
| Channel_2 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX2_LOAD_THRESHOLD4 0x021C |
| Channel_2 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX3_ATT_CHIRP_HIGHZ 0x021E |
| Channel_3 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX3_ATT_SIGNAL_HIGHZ 0x021F |
| Channel_3 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX3_ATT_CHIRP_LOWZ 0x0220 |
| Channel_3 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX3_ATT_SIGNAL_LOWZ 0x0221 |
| Channel_3 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX3_ATT_CHIRP_VLOWZ 0x0222 |
| Channel_3 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX3_ATT_SIGNAL_VLOWZ 0x0223 |
| Channel_3 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX3_LOAD_THRESHOLD1 0x0224 |
| Channel_3 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX3_LOAD_THRESHOLD2 0x0226 |
| Channel_3 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX3_LOAD_THRESHOLD3 0x0228 |
| Channel_3 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX3_LOAD_THRESHOLD4 0x022A |
| Channel_3 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX4_ATT_CHIRP_HIGHZ 0x022C |
| Channel_4 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX4_ATT_SIGNAL_HIGHZ 0x022D |
| Channel_4 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX4_ATT_CHIRP_LOWZ 0x022E |
| Channel_4 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX4_ATT_SIGNAL_LOWZ 0x022F |
| Channel_4 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX4_ATT_CHIRP_VLOWZ 0x0230 |
| Channel_4 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX4_ATT_SIGNAL_VLOWZ 0x0231 |
| Channel_4 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX4_LOAD_THRESHOLD1 0x0232 |
| Channel_4 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX4_LOAD_THRESHOLD2 0x0234 |
| Channel_4 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX4_LOAD_THRESHOLD3 0x0236 |
| Channel_4 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX4_LOAD_THRESHOLD4 0x0238 |
| Channel_4 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX5_ATT_CHIRP_HIGHZ 0x023A |
| Channel_5 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX5_ATT_SIGNAL_HIGHZ 0x023B |
| Channel_5 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX5_ATT_CHIRP_LOWZ 0x023C |
| Channel_5 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX5_ATT_SIGNAL_LOWZ 0x023D |
| Channel_5 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX5_ATT_CHIRP_VLOWZ 0x023E |
| Channel_5 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX5_ATT_SIGNAL_VLOWZ 0x023F |
| Channel_5 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX5_LOAD_THRESHOLD1 0x0240 |
| Channel_5 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX5_LOAD_THRESHOLD2 0x0242 |
| Channel_5 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX5_LOAD_THRESHOLD3 0x0244 |
| Channel_5 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX5_LOAD_THRESHOLD4 0x0246 |
| Channel_5 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX6_ATT_CHIRP_HIGHZ 0x0248 |
| Channel_6 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX6_ATT_SIGNAL_HIGHZ 0x0249 |
| Channel_6 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX6_ATT_CHIRP_LOWZ 0x024A |
| Channel_6 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX6_ATT_SIGNAL_LOWZ 0x024B |
| Channel_6 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX6_ATT_CHIRP_VLOWZ 0x024C |
| Channel_6 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX6_ATT_SIGNAL_VLOWZ 0x024D |
| Channel_6 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX6_LOAD_THRESHOLD1 0x024E |
| Channel_6 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX6_LOAD_THRESHOLD2 0x0250 |
| Channel_6 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX6_LOAD_THRESHOLD3 0x0252 |
| Channel_6 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX6_LOAD_THRESHOLD4 0x0254 |
| Channel_6 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX7_ATT_CHIRP_HIGHZ 0x0256 |
| Channel_7 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX7_ATT_SIGNAL_HIGHZ 0x0257 |
| Channel_7 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX7_ATT_CHIRP_LOWZ 0x0258 |
| Channel_7 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX7_ATT_SIGNAL_LOWZ 0x0259 |
| Channel_7 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX7_ATT_CHIRP_VLOWZ 0x025A |
| Channel_7 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX7_ATT_SIGNAL_VLOWZ 0x025B |
| Channel_7 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX7_LOAD_THRESHOLD1 0x025C |
| Channel_7 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX7_LOAD_THRESHOLD2 0x025E |
| Channel_7 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX7_LOAD_THRESHOLD3 0x0260 |
| Channel_7 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX7_LOAD_THRESHOLD4 0x0262 |
| Channel_7 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX8_ATT_CHIRP_HIGHZ 0x0264 |
| Channel_8 Attenuation chirp in High impedance. More... | |
| #define | PHY_ID_TX8_ATT_SIGNAL_HIGHZ 0x0265 |
| Channel_8 Attenuation signal in High impedance. More... | |
| #define | PHY_ID_TX8_ATT_CHIRP_LOWZ 0x0266 |
| Channel_8 Attenuation chirp in low impedance. More... | |
| #define | PHY_ID_TX8_ATT_SIGNAL_LOWZ 0x0267 |
| Channel_8 Attenuation signal in low impedance. More... | |
| #define | PHY_ID_TX8_ATT_CHIRP_VLOWZ 0x0268 |
| Channel_8 Attenuation chirp in very low impedance. More... | |
| #define | PHY_ID_TX8_ATT_SIGNAL_VLOWZ 0x0269 |
| Channel_8 Attenuation signal in very low impedance. More... | |
| #define | PHY_ID_TX8_LOAD_THRESHOLD1 0x026A |
| Channel_8 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX8_LOAD_THRESHOLD2 0x026C |
| Channel_8 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX8_LOAD_THRESHOLD3 0x026E |
| Channel_8 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_TX8_LOAD_THRESHOLD4 0x0270 |
| Channel_8 Threshold for RMS calculated to detect load type. More... | |
| #define | PHY_ID_CFG_DRIVER1_MODE 0x0400 |
| Flag to indicate if driver 1 is extern driver (1) or intern driver (0) More... | |
| #define | PHY_ID_CFG_DRIVER2_MODE 0x0401 |
| Flag to indicate if driver 2 is extern driver (1) or intern driver (0) More... | |
| #define | PHY_ID_CFG_TXRX1_POLARITY 0x0402 |
| Flag to indicate if txrx1 polarity is high or low active. More... | |
| #define | PHY_ID_CFG_TXRX2_POLARITY 0x0403 |
| Flag to indicate if txrx2 polarity is high or low active. More... | |
| #define | PHY_ID_CFG_AUTODETECT_BRANCH 0x0404 |
| Flag to enable branch auto detection. More... | |
| #define | PHY_ID_CFG_IMPEDANCE 0x0405 |
| When branch auto detection disabled, indicate impedance to use. More... | |
| #define | PHY_ID_CFG_HIGH_Z_DRIVER 0x0406 |
| Select driver for high impedance. More... | |
| #define | PHY_ID_CFG_LOW_Z_DRIVER 0x0407 |
| Select driver for high impedance. More... | |
| #define | PHY_ID_CFG_VLOW_Z_DRIVER 0x0408 |
| Select driver for high impedance. More... | |
| #define | PHY_ID_CFG_AGC0_KRSSI_OFFSET 0x0409 |
| Offset for received signal strength (rssi) according to AGC 0 configuration. More... | |
| #define | PHY_ID_CFG_AGC1_KRSSI_OFFSET 0x040A |
| Offset for received signal strength (rssi) according to AGC 1 configuration. More... | |
| #define | PHY_ID_CFG_AGC2_KRSSI_OFFSET 0x040B |
| Offset for received signal strength (rssi) according to AGC 2 configuration. More... | |
| #define | PHY_ID_CFG_AGC3_KRSSI_OFFSET 0x040C |
| Offset for received signal strength (rssi) according to AGC 3 configuration. More... | |
| #define | PHY_ID_CFG_N1_DELAY 0x040D |
| N1 Delay. More... | |
| #define | PHY_ID_CFG_P1_DELAY 0x040E |
| P1 Delay. More... | |
| #define | PHY_ID_CFG_N2_DELAY 0x040F |
| N2 delay. More... | |
| #define | PHY_ID_CFG_P2_DELAY 0x0410 |
| P2 delay. More... | |
| #define | PHY_ID_CFG_EMIT1_ACTIVE 0x0411 |
| Emit 1 Active. More... | |
| #define | PHY_ID_CFG_EMIT2_ACTIVE 0x0412 |
| Emit 2 Active. More... | |
| #define | PHY_ID_CFG_EMIT3_ACTIVE 0x0413 |
| Emit 3 Active. More... | |
| #define | PHY_ID_CFG_EMIT4_ACTIVE 0x0414 |
| Emit 4 Active. More... | |
| #define | PHY_ID_CFG_TXRX_CHANNEL 0x0415 |
| Transmission/Reception Channel. More... | |
| #define | PHY_ID_CFG_COUPLING_BOARD 0x0416 |
| Coupling board in use. More... | |
| #define | PHY_ID_CFG_PRIME_MODE 0x0417 |
| PRIME mode (see mode values in atpl230.h) More... | |
| #define | PHY_ID_CFG_TIME_BEFORE_TX_HIGHZ 0x0418 |
| Time in 10's of us for HIMP pin before transmission with high impedance. More... | |
| #define | PHY_ID_CFG_TIME_BEFORE_TX_LOWZ 0x041A |
| Time in 10's of us for TXRX pin before transmission with low impedance. More... | |
| #define | PHY_ID_CFG_TIME_AFTER_TX_HIGHZ 0x041C |
| Time (unit depends on platform) for HIMP pin after transmission with high impedance. More... | |
| #define | PHY_ID_CFG_TIME_AFTER_TX_LOWZ 0x041E |
| Time (unit depends on platform) for TXRX pin after transmission with low impedance. More... | |
| #define | PHY_ID_CFG_RX_CORR_THRESHOLD 0x0420 |
| Threshold for autocorrelation filter. More... | |
| #define | PHY_ID_CFG_ENABLE_VLOW_PK 0x0422 |
| Flag to enable Peak Cut On in case of low impedance. More... | |
Serialization Addons | |
| #define | DISABLE_SERIAL 0 |
| #define | SERIAL_IF_ENABLE 0x1 |
| #define | SNIFFER_IF_ENABLE 0x2 |
ATPL230 Physical Layer Interface | |
| void | phy_tx_frame_result_cb (xPhyMsgTxResult_t *px_tx_result) |
| Task to process TX PLC. More... | |
| uint8_t | phy_get_cfg_param (uint16_t us_id, void *p_val, uint16_t uc_len) |
| Get PHY layer parameter. More... | |
| uint8_t | phy_set_cfg_param (uint16_t us_id, void *p_val, uint16_t uc_len) |
| Set PHY layer parameter. More... | |
| uint8_t | phy_cmd_cfg_param (uint16_t us_id, uint8_t uc_cmd, uint8_t uc_mask) |
| Set PHY layer parameter. More... | |
| uint8_t | phy_tx_frame (xPhyMsgTx_t *px_msg) |
| Write the transmitted data with ATPL230 device. More... | |
| void | phy_rx_frame_cb (xPhyMsgRx_t *px_msg) |
| Read the received data with ATPL230 device. More... | |
| void | phy_init (uint8_t uc_ifaceEnable) |
| Create PHY tasks, queues and semaphores Initialize physical parameters and configure ATPL230 device. More... | |
| void | phy_reset (uint8_t uc_reset_type) |
| Reset PHY layer including pplc service and serial ifaces Initialize physical parameters and configure ATPL230 device. More... | |
Mapped address for a phy special control register | |
| #define | REG_ATPL230_PHY_SFR (0xFE2A) |
System configuration | |
| #define | REG_ATPL230_SYS_CONFIG (0xFE2C) |
Mapped address to peak_cut and emit_gain in transmission | |
| #define | REG_ATPL230_TXRXBUF_PEAK_CUT_GAIN_TX0 (0xFE38) |
| #define | REG_ATPL230_TXRXBUF_PEAK_CUT_GAIN_TX1 (0xFE39) |
| #define | REG_ATPL230_TXRXBUF_PEAK_CUT_GAIN_TX2 (0xFE3A) |
| #define | REG_ATPL230_TXRXBUF_PEAK_CUT_GAIN_TX3 (0xFE3B) |
| #define | REG_ATPL230_TXRXBUF_EMIT_GAIN_TX0 (0xFE3C) |
| #define | REG_ATPL230_TXRXBUF_EMIT_GAIN_TX1 (0xFE3D) |
| #define | REG_ATPL230_TXRXBUF_EMIT_GAIN_TX2 (0xFE3E) |
| #define | REG_ATPL230_TXRXBUF_EMIT_GAIN_TX3 (0xFE3F) |
Mapped addresses to keep the time reference from the last received beacon | |
| #define | REG_ATPL230_VHIGH_TIMER_BEACON_REF (0xFE47) |
| #define | REG_ATPL230_HIGH_TIMER_BEACON_REF (0xFE48) |
| #define | REG_ATPL230_MED_TIMER_BEACON_REF (0xFE49) |
| #define | REG_ATPL230_LOW_TIMER_BEACON_REF (0xFE4A) |
Filter Configuration | |
| #define | REG_ATPL230_FILTER_MIN_HIGH (0xFE53) |
| #define | REG_ATPL230_FILTER_MIN_MED (0xFE54) |
| #define | REG_ATPL230_FILTER_MIN_LOW (0xFE55) |
| #define | REG_ATPL230_TX_DELAY_SAMPLES (0xFE57) |
RSSI correction factors for AGC 1 and 2 | |
| #define | REG_ATPL230_AGC0_KRSSI (0xFE5C) |
| #define | REG_ATPL230_AGC1_KRSSI (0xFE5D) |
RSSI correction factors for AGC 3 and 4 | |
| #define | REG_ATPL230_AGC2_KRSSI (0xFE5F) |
| #define | REG_ATPL230_AGC3_KRSSI (0xFE60) |
Mapped addresses for the SNA | |
| #define | REG_ATPL230_SNA0 (0xFE62) |
| #define | REG_ATPL230_SNA1 (0xFE63) |
| #define | REG_ATPL230_SNA2 (0xFE64) |
| #define | REG_ATPL230_SNA3 (0xFE65) |
| #define | REG_ATPL230_SNA4 (0xFE66) |
| #define | REG_ATPL230_SNA5 (0xFE67) |
Mapped address for the physicial layer configuration | |
| #define | REG_ATPL230_PHY_CONFIG (0xFE68) |
Mapped addresses for emitter | |
| #define | REG_ATPL230_EMIT_CONFIG (0xFE8F) |
| #define | REG_ATPL230_AFE_CTL (0xFE90) |
Mapped addresses to configure the emitter | |
| #define | REG_ATPL230_N1_DELAY (0xFE9F) |
| #define | REG_ATPL230_P1_DELAY (0xFEA0) |
| #define | REG_ATPL230_N2_DELAY (0xFEA1) |
| #define | REG_ATPL230_P2_DELAY (0xFEA2) |
| #define | REG_ATPL230_EMIT1_ACTIVE (0xFEA3) |
| #define | REG_ATPL230_EMIT2_ACTIVE (0xFEA4) |
| #define | REG_ATPL230_EMIT3_ACTIVE (0xFEA5) |
| #define | REG_ATPL230_EMIT4_ACTIVE (0xFEA6) |
Mapped address for direct input buffer to FFT | |
| #define | REG_ATPL230_FFT_MODE (0xFEB0) |
Mapped address for hardware version | |
| #define | REG_ATPL230_VERSION (0xFEFF) |
Mapped addresses for emission time | |
| #define | REG_ATPL230_TXRXBUF_EMITIME1_TX0 (0xFD00) |
| #define | REG_ATPL230_TXRXBUF_EMITIME2_TX0 (0xFD01) |
| #define | REG_ATPL230_TXRXBUF_EMITIME3_TX0 (0xFD02) |
| #define | REG_ATPL230_TXRXBUF_EMITIME4_TX0 (0xFD03) |
| #define | REG_ATPL230_TXRXBUF_EMITIME1_TX1 (0xFD04) |
| #define | REG_ATPL230_TXRXBUF_EMITIME2_TX1 (0xFD05) |
| #define | REG_ATPL230_TXRXBUF_EMITIME3_TX1 (0xFD06) |
| #define | REG_ATPL230_TXRXBUF_EMITIME4_TX1 (0xFD07) |
| #define | REG_ATPL230_TXRXBUF_EMITIME1_TX2 (0xFD08) |
| #define | REG_ATPL230_TXRXBUF_EMITIME2_TX2 (0xFD09) |
| #define | REG_ATPL230_TXRXBUF_EMITIME3_TX2 (0xFD0A) |
| #define | REG_ATPL230_TXRXBUF_EMITIME4_TX2 (0xFD0B) |
| #define | REG_ATPL230_TXRXBUF_EMITIME1_TX3 (0xFD0C) |
| #define | REG_ATPL230_TXRXBUF_EMITIME2_TX3 (0xFD0D) |
| #define | REG_ATPL230_TXRXBUF_EMITIME3_TX3 (0xFD0E) |
| #define | REG_ATPL230_TXRXBUF_EMITIME4_TX3 (0xFD0F) |
Mapped addresses for time to commute HIMP after transmission | |
| #define | REG_ATPL230_TXRXBUF_TXRX_TA1_TX0 (0xFD10) |
| #define | REG_ATPL230_TXRXBUF_TXRX_TA2_TX0 (0xFD11) |
| #define | REG_ATPL230_TXRXBUF_TXRX_TA1_TX1 (0xFD12) |
| #define | REG_ATPL230_TXRXBUF_TXRX_TA2_TX1 (0xFD13) |
| #define | REG_ATPL230_TXRXBUF_TXRX_TA1_TX2 (0xFD14) |
| #define | REG_ATPL230_TXRXBUF_TXRX_TA2_TX2 (0xFD15) |
| #define | REG_ATPL230_TXRXBUF_TXRX_TA1_TX3 (0xFD16) |
| #define | REG_ATPL230_TXRXBUF_TXRX_TA2_TX3 (0xFD17) |
Mapped addresses for time to commute HIMP before transmission | |
| #define | REG_ATPL230_TXRXBUF_TXRX_TB1_TX0 (0xFD18) |
| #define | REG_ATPL230_TXRXBUF_TXRX_TB2_TX0 (0xFD19) |
| #define | REG_ATPL230_TXRXBUF_TXRX_TB1_TX1 (0xFD1A) |
| #define | REG_ATPL230_TXRXBUF_TXRX_TB2_TX1 (0xFD1B) |
| #define | REG_ATPL230_TXRXBUF_TXRX_TB1_TX2 (0xFD1C) |
| #define | REG_ATPL230_TXRXBUF_TXRX_TB2_TX2 (0xFD1D) |
| #define | REG_ATPL230_TXRXBUF_TXRX_TB1_TX3 (0xFD1E) |
| #define | REG_ATPL230_TXRXBUF_TXRX_TB2_TX3 (0xFD1F) |
Mapped addresses for global amplitude | |
| #define | REG_ATPL230_TXRXBUF_GLOBAL_AMP_TX0 (0xFD20) |
| #define | REG_ATPL230_TXRXBUF_GLOBAL_AMP_TX1 (0xFD21) |
| #define | REG_ATPL230_TXRXBUF_GLOBAL_AMP_TX2 (0xFD22) |
| #define | REG_ATPL230_TXRXBUF_GLOBAL_AMP_TX3 (0xFD23) |
Mapped addresses for signal amplitude | |
| #define | REG_ATPL230_TXRXBUF_SIGNAL_AMP_TX0 (0xFD24) |
| #define | REG_ATPL230_TXRXBUF_SIGNAL_AMP_TX1 (0xFD25) |
| #define | REG_ATPL230_TXRXBUF_SIGNAL_AMP_TX2 (0xFD26) |
| #define | REG_ATPL230_TXRXBUF_SIGNAL_AMP_TX3 (0xFD27) |
Mapped addresses for chirp amplitude | |
| #define | REG_ATPL230_TXRXBUF_CHIRP_AMP_TX0 (0xFD28) |
| #define | REG_ATPL230_TXRXBUF_CHIRP_AMP_TX1 (0xFD29) |
| #define | REG_ATPL230_TXRXBUF_CHIRP_AMP_TX2 (0xFD2A) |
| #define | REG_ATPL230_TXRXBUF_CHIRP_AMP_TX3 (0xFD2B) |
Mapped addresses for transmission timeout value | |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT1_TX0 (0xFD2C) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT2_TX0 (0xFD2D) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT3_TX0 (0xFD2E) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT4_TX0 (0xFD2F) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT1_TX1 (0xFD30) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT2_TX1 (0xFD31) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT3_TX1 (0xFD32) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT4_TX1 (0xFD33) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT1_TX2 (0xFD34) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT2_TX2 (0xFD35) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT3_TX2 (0xFD36) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT4_TX2 (0xFD37) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT1_TX3 (0xFD38) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT2_TX3 (0xFD39) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT3_TX3 (0xFD3A) |
| #define | REG_ATPL230_TXRXBUF_TIMEOUT4_TX3 (0xFD3B) |
Mapped addresses for transmission configuration | |
| #define | REG_ATPL230_TXRXBUF_TXCONF_TX0 (0xFD3C) |
| #define | REG_ATPL230_TXRXBUF_TXCONF_TX1 (0xFD3D) |
| #define | REG_ATPL230_TXRXBUF_TXCONF_TX2 (0xFD3E) |
| #define | REG_ATPL230_TXRXBUF_TXCONF_TX3 (0xFD3F) |
Mapped addresses for initial address for every transmission buffer | |
| #define | REG_ATPL230_TXRXBUF_INITAD1_TX0 (0xFD40) |
| #define | REG_ATPL230_TXRXBUF_INITAD2_TX0 (0xFD41) |
| #define | REG_ATPL230_TXRXBUF_INITAD1_TX1 (0xFD42) |
| #define | REG_ATPL230_TXRXBUF_INITAD2_TX1 (0xFD43) |
| #define | REG_ATPL230_TXRXBUF_INITAD1_TX2 (0xFD44) |
| #define | REG_ATPL230_TXRXBUF_INITAD2_TX2 (0xFD45) |
| #define | REG_ATPL230_TXRXBUF_INITAD1_TX3 (0xFD46) |
| #define | REG_ATPL230_TXRXBUF_INITAD2_TX3 (0xFD47) |
Mapped addresses for RMS calculation after transmission | |
| #define | REG_ATPL230_TXRXBUF_RMSCALC1_TX0 (0xFD48) |
| #define | REG_ATPL230_TXRXBUF_RMSCALC2_TX0 (0xFD49) |
| #define | REG_ATPL230_TXRXBUF_RMSCALC1_TX1 (0xFD4A) |
| #define | REG_ATPL230_TXRXBUF_RMSCALC2_TX1 (0xFD4B) |
| #define | REG_ATPL230_TXRXBUF_RMSCALC1_TX2 (0xFD4C) |
| #define | REG_ATPL230_TXRXBUF_RMSCALC2_TX2 (0xFD4D) |
| #define | REG_ATPL230_TXRXBUF_RMSCALC1_TX3 (0xFD4E) |
| #define | REG_ATPL230_TXRXBUF_RMSCALC2_TX3 (0xFD4F) |
Mapped addresses for transmission result | |
| #define | REG_ATPL230_TXRXBUF_RESULT_TX10 (0xFD50) |
| #define | REG_ATPL230_TXRXBUF_RESULT_TX32 (0xFD51) |
Mapped addresses for transmission interrupt flags to read and to erase | |
| #define | REG_ATPL230_TXRXBUF_TX_INT (0xFD52) |
Mapped addresses for Viterbi soft Bit Error Rate value | |
| #define | REG_ATPL230_TXRXBUF_BERSOFT_RX0 (0xFD53) |
| #define | REG_ATPL230_TXRXBUF_BERSOFT_RX1 (0xFD54) |
| #define | REG_ATPL230_TXRXBUF_BERSOFT_RX2 (0xFD55) |
| #define | REG_ATPL230_TXRXBUF_BERSOFT_RX3 (0xFD56) |
Mapped addresses for Viterbi soft Bit Error Rate average value | |
| #define | REG_ATPL230_TXRXBUF_BERSOFT_AVG_RX0 (0xFD57) |
| #define | REG_ATPL230_TXRXBUF_BERSOFT_AVG_RX1 (0xFD58) |
| #define | REG_ATPL230_TXRXBUF_BERSOFT_AVG_RX2 (0xFD59) |
| #define | REG_ATPL230_TXRXBUF_BERSOFT_AVG_RX3 (0xFD5A) |
Mapped addresses for Viterbi soft Bit Error Rate maximum value | |
| #define | REG_ATPL230_TXRXBUF_BERSOFT_MAX_RX0 (0xFD5B) |
| #define | REG_ATPL230_TXRXBUF_BERSOFT_MAX_RX1 (0xFD5C) |
| #define | REG_ATPL230_TXRXBUF_BERSOFT_MAX_RX2 (0xFD5D) |
| #define | REG_ATPL230_TXRXBUF_BERSOFT_MAX_RX3 (0xFD5E) |
| #define | REG_ATPL230_TXRXBUF_BERHARD_RX0 (0xFD5F) |
| Mapped addresses for Viterbi hard Bit Error Rate value. More... | |
| #define | REG_ATPL230_TXRXBUF_BERHARD_RX1 (0xFD60) |
| #define | REG_ATPL230_TXRXBUF_BERHARD_RX2 (0xFD61) |
| #define | REG_ATPL230_TXRXBUF_BERHARD_RX3 (0xFD62) |
Mapped addresses for Viterbi hard Bit Error Rate average value | |
| #define | REG_ATPL230_TXRXBUF_BERHARD_AVG_RX0 (0xFD63) |
| #define | REG_ATPL230_TXRXBUF_BERHARD_AVG_RX1 (0xFD64) |
| #define | REG_ATPL230_TXRXBUF_BERHARD_AVG_RX2 (0xFD65) |
| #define | REG_ATPL230_TXRXBUF_BERHARD_AVG_RX3 (0xFD66) |
Mapped addresses for Viterbi hard Bit Error Rate maximum value | |
| #define | REG_ATPL230_TXRXBUF_BERHARD_MAX_RX0 (0xFD67) |
| #define | REG_ATPL230_TXRXBUF_BERHARD_MAX_RX1 (0xFD68) |
| #define | REG_ATPL230_TXRXBUF_BERHARD_MAX_RX2 (0xFD69) |
| #define | REG_ATPL230_TXRXBUF_BERHARD_MAX_RX3 (0xFD6A) |
Mapped addresses for RSSI minimum value | |
| #define | REG_ATPL230_TXRXBUF_RSSIMIN_RX0 (0xFD6B) |
| #define | REG_ATPL230_TXRXBUF_RSSIMIN_RX1 (0xFD6C) |
| #define | REG_ATPL230_TXRXBUF_RSSIMIN_RX2 (0xFD6D) |
| #define | REG_ATPL230_TXRXBUF_RSSIMIN_RX3 (0xFD6E) |
Mapped addresses for RSSI average value | |
| #define | REG_ATPL230_TXRXBUF_RSSIAVG_RX0 (0xFD6F) |
| #define | REG_ATPL230_TXRXBUF_RSSIAVG_RX1 (0xFD70) |
| #define | REG_ATPL230_TXRXBUF_RSSIAVG_RX2 (0xFD71) |
| #define | REG_ATPL230_TXRXBUF_RSSIAVG_RX3 (0xFD72) |
Mapped addresses for RSSI maximum value | |
| #define | REG_ATPL230_TXRXBUF_RSSIMAX_RX0 (0xFD73) |
| #define | REG_ATPL230_TXRXBUF_RSSIMAX_RX1 (0xFD74) |
| #define | REG_ATPL230_TXRXBUF_RSSIMAX_RX2 (0xFD75) |
| #define | REG_ATPL230_TXRXBUF_RSSIMAX_RX3 (0xFD76) |
Mapped addresses for CINR minimum value | |
| #define | REG_ATPL230_TXRXBUF_CINRMIN_RX0 (0xFD77) |
| #define | REG_ATPL230_TXRXBUF_CINRMIN_RX1 (0xFD78) |
| #define | REG_ATPL230_TXRXBUF_CINRMIN_RX2 (0xFD79) |
| #define | REG_ATPL230_TXRXBUF_CINRMIN_RX3 (0xFD7A) |
Mapped addresses for CINR average value | |
| #define | REG_ATPL230_TXRXBUF_CINRAVG_RX0 (0xFD7B) |
| #define | REG_ATPL230_TXRXBUF_CINRAVG_RX1 (0xFD7C) |
| #define | REG_ATPL230_TXRXBUF_CINRAVG_RX2 (0xFD7D) |
| #define | REG_ATPL230_TXRXBUF_CINRAVG_RX3 (0xFD7E) |
Mapped addresses for CINR maximum value | |
| #define | REG_ATPL230_TXRXBUF_CINRMAX_RX0 (0xFD7F) |
| #define | REG_ATPL230_TXRXBUF_CINRMAX_RX1 (0xFD80) |
| #define | REG_ATPL230_TXRXBUF_CINRMAX_RX2 (0xFD81) |
| #define | REG_ATPL230_TXRXBUF_CINRMAX_RX3 (0xFD82) |
Mapped addresses for reception time for every buffer | |
| #define | REG_ATPL230_TXRXBUF_RECTIME1_RX0 (0xFD83) |
| #define | REG_ATPL230_TXRXBUF_RECTIME2_RX0 (0xFD84) |
| #define | REG_ATPL230_TXRXBUF_RECTIME3_RX0 (0xFD85) |
| #define | REG_ATPL230_TXRXBUF_RECTIME4_RX0 (0xFD86) |
| #define | REG_ATPL230_TXRXBUF_RECTIME1_RX1 (0xFD87) |
| #define | REG_ATPL230_TXRXBUF_RECTIME2_RX1 (0xFD88) |
| #define | REG_ATPL230_TXRXBUF_RECTIME3_RX1 (0xFD89) |
| #define | REG_ATPL230_TXRXBUF_RECTIME4_RX1 (0xFD8A) |
| #define | REG_ATPL230_TXRXBUF_RECTIME1_RX2 (0xFD8B) |
| #define | REG_ATPL230_TXRXBUF_RECTIME2_RX2 (0xFD8C) |
| #define | REG_ATPL230_TXRXBUF_RECTIME3_RX2 (0xFD8D) |
| #define | REG_ATPL230_TXRXBUF_RECTIME4_RX2 (0xFD8E) |
| #define | REG_ATPL230_TXRXBUF_RECTIME1_RX3 (0xFD8F) |
| #define | REG_ATPL230_TXRXBUF_RECTIME2_RX3 (0xFD90) |
| #define | REG_ATPL230_TXRXBUF_RECTIME3_RX3 (0xFD91) |
| #define | REG_ATPL230_TXRXBUF_RECTIME4_RX3 (0xFD92) |
Mapped addresses for last zero cross time | |
| #define | REG_ATPL230_TXRXBUF_ZCT1_RX0 (0xFD93) |
| #define | REG_ATPL230_TXRXBUF_ZCT2_RX0 (0xFD94) |
| #define | REG_ATPL230_TXRXBUF_ZCT3_RX0 (0xFD95) |
| #define | REG_ATPL230_TXRXBUF_ZCT4_RX0 (0xFD96) |
| #define | REG_ATPL230_TXRXBUF_ZCT1_RX1 (0xFD97) |
| #define | REG_ATPL230_TXRXBUF_ZCT2_RX1 (0xFD98) |
| #define | REG_ATPL230_TXRXBUF_ZCT3_RX1 (0xFD99) |
| #define | REG_ATPL230_TXRXBUF_ZCT4_RX1 (0xFD9A) |
| #define | REG_ATPL230_TXRXBUF_ZCT1_RX2 (0xFD9B) |
| #define | REG_ATPL230_TXRXBUF_ZCT2_RX2 (0xFD9C) |
| #define | REG_ATPL230_TXRXBUF_ZCT3_RX2 (0xFD9D) |
| #define | REG_ATPL230_TXRXBUF_ZCT4_RX2 (0xFD9E) |
| #define | REG_ATPL230_TXRXBUF_ZCT1_RX3 (0xFD9F) |
| #define | REG_ATPL230_TXRXBUF_ZCT2_RX3 (0xFDA0) |
| #define | REG_ATPL230_TXRXBUF_ZCT3_RX3 (0xFDA1) |
| #define | REG_ATPL230_TXRXBUF_ZCT4_RX3 (0xFDA2) |
Mapped addresses for Error Vector Magnitude from header | |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADER1_RX0 (0xFDA3) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADER2_RX0 (0xFDA4) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADER1_RX1 (0xFDA5) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADER2_RX1 (0xFDA6) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADER1_RX2 (0xFDA7) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADER2_RX2 (0xFDA8) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADER1_RX3 (0xFDA9) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADER2_RX3 (0xFDAA) |
Mapped addresses for Error Vector Magnitude from payload | |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLOAD1_RX0 (0xFDAB) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLOAD2_RX0 (0xFDAC) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLOAD1_RX1 (0xFDAD) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLOAD2_RX1 (0xFDAE) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLOAD1_RX2 (0xFDAF) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLOAD2_RX2 (0xFDB0) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLOAD1_RX3 (0xFDB1) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLOAD2_RX3 (0xFDB2) |
Mapped addresses for accumulated Error Vector Magnitude from header | |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM1_RX0 (0xFDB3) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM2_RX0 (0xFDB4) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM3_RX0 (0xFDB5) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM4_RX0 (0xFDB6) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM1_RX1 (0xFDB7) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM2_RX1 (0xFDB8) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM3_RX1 (0xFDB9) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM4_RX1 (0xFDBA) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM1_RX2 (0xFDBB) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM2_RX2 (0xFDBC) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM3_RX2 (0xFDBD) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM4_RX2 (0xFDBE) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM1_RX3 (0xFDBF) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM2_RX3 (0xFDC0) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM3_RX3 (0xFDC1) |
| #define | REG_ATPL230_TXRXBUF_EVM_HEADACUM4_RX3 (0xFDC2) |
Mapped addresses for accumulated Error Vector Magnitude from payload | |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM1_RX0 (0xFDC3) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM2_RX0 (0xFDC4) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM3_RX0 (0xFDC5) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM4_RX0 (0xFDC6) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM1_RX1 (0xFDC7) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM2_RX1 (0xFDC8) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM3_RX1 (0xFDC9) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM4_RX1 (0xFDCA) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM1_RX2 (0xFDCB) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM2_RX2 (0xFDCC) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM3_RX2 (0xFDCD) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM4_RX2 (0xFDCE) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM1_RX3 (0xFDCF) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM2_RX3 (0xFDD0) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM3_RX3 (0xFDD1) |
| #define | REG_ATPL230_TXRXBUF_EVM_PAYLACUM4_RX3 (0xFDD2) |
Mapped addresses for reception buffer selection | |
| #define | REG_ATPL230_TXRXBUF_SELECT_BUFF_RX (0xFDD3) |
Mapped addresses for reception interrupt flags to read | |
| #define | REG_ATPL230_TXRXBUF_RX_INT (0xFDD4) |
Mapped addresses for reception configuration | |
| #define | REG_ATPL230_TXRXBUF_RXCONF (0xFDD5) |
Mapped addresses for initial address for every reception buffer | |
| #define | REG_ATPL230_TXRXBUF_INITAD1_RX0 (0xFDD6) |
| #define | REG_ATPL230_TXRXBUF_INITAD2_RX0 (0xFDD7) |
| #define | REG_ATPL230_TXRXBUF_INITAD1_RX1 (0xFDD8) |
| #define | REG_ATPL230_TXRXBUF_INITAD2_RX1 (0xFDD9) |
| #define | REG_ATPL230_TXRXBUF_INITAD1_RX2 (0xFDDA) |
| #define | REG_ATPL230_TXRXBUF_INITAD2_RX2 (0xFDDB) |
| #define | REG_ATPL230_TXRXBUF_INITAD1_RX3 (0xFDDC) |
| #define | REG_ATPL230_TXRXBUF_INITAD2_RX3 (0xFDDD) |
Mapped addresses for busy channel statistics | |
| #define | REG_ATPL230_TXRXBUF_CDONSTA1 (0xFDDE) |
| #define | REG_ATPL230_TXRXBUF_CDONSTA2 (0xFDDF) |
| #define | REG_ATPL230_TXRXBUF_CDONSTA3 (0xFDE0) |
| #define | REG_ATPL230_TXRXBUF_CDONSTA4 (0xFDE1) |
Mapped addresses for free channel statistics | |
| #define | REG_ATPL230_TXRXBUF_CDOFFSTA1 (0xFDE2) |
| #define | REG_ATPL230_TXRXBUF_CDOFFSTA2 (0xFDE3) |
| #define | REG_ATPL230_TXRXBUF_CDOFFSTA3 (0xFDE4) |
| #define | REG_ATPL230_TXRXBUF_CDOFFSTA4 (0xFDE5) |
Mapped addresses for number of AGCs activated in reception | |
| #define | REG_ATPL230_NUM_AGCS_RX0 (0xFDE6) |
| #define | REG_ATPL230_NUM_AGCS_RX1 (0xFDE7) |
| #define | REG_ATPL230_NUM_AGCS_RX2 (0xFDE8) |
| #define | REG_ATPL230_NUM_AGCS_RX3 (0xFDE9) |
Mapped addresses for robo mode tx/rx | |
| #define | REG_ATPL230_TXRXBUF_TXCONF_ROBO_CTL (0xFDF2) |
| #define | REG_ATPL230_TXRXBUF_RXCONF_INFO_ROBO_MODE (0xFDF3) |
Mapped addresses for noise mode | |
| #define | REG_ATPL230_TXRXBUF_RECTIME_NOISE1 (0xFDF4) |
| #define | REG_ATPL230_TXRXBUF_RECTIME_NOISE2 (0xFDF5) |
| #define | REG_ATPL230_TXRXBUF_RECTIME_NOISE3 (0xFDF6) |
| #define | REG_ATPL230_TXRXBUF_RECTIME_NOISE4 (0xFDF7) |
| #define | REG_ATPL230_TXRXBUF_INITREG_ATPL230_NOISE1 (0xFDF8) |
| #define | REG_ATPL230_TXRXBUF_INITREG_ATPL230_NOISE2 (0xFDF9) |
| #define | REG_ATPL230_TXRXBUF_NOISECONF (0xFDFA) |
Mapped addresses for selection transmision branch | |
| #define | REG_ATPL230_TXRXBUF_TXCONF_SELBRANCH (0xFDFB) |
Mapped addresses for RSSI in noise reception | |
| #define | REG_ATPL230_TXRXBUF_RSSIMIN_NOISE (0xFDFC) |
| #define | REG_ATPL230_TXRXBUF_RSSIAVG_NOISE (0xFDFD) |
| #define | REG_ATPL230_TXRXBUF_RSSIMAX_NOISE (0xFDFE) |
Mapped addresses for number of AGCs activated in noise reception | |
| #define | REG_ATPL230_NUM_AGCS_NOISE (0xFDFF) |
ATPL230 MAC CRC processing | |
| #define | ATPL230_MAC_EN (0x1u) |
| #define | ATPL230_MAC_EN_Pos 0 |
| #define | ATPL230_MAC_EN_Msk (ATPL230_MAC_EN << ATPL230_MAC_EN_Pos) |
Special Function Register | |
| #define | ATPL230_SFR_PHY_INT (0x1u) |
| #define | ATPL230_SFR_PHY_INT_Pos 0 |
| #define | ATPL230_SFR_PHY_INT_Msk (ATPL230_SFR_PHY_INT << ATPL230_SFR_PHY_INT_Pos) |
| (ATPL230) Physical Layer interruption More... | |
| #define | ATPL230_SFR_UMD (0x1u) |
| #define | ATPL230_SFR_UMD_Pos 5 |
| #define | ATPL230_SFR_UMD_Msk (ATPL230_SFR_UMD << ATPL230_SFR_UMD_Pos) |
| (ATPL230) Unsupported Modulation Scheme flag More... | |
| #define | ATPL230_SFR_ERR_PYL (0x1u) |
| #define | ATPL230_SFR_ERR_PYL_Pos 4 |
| #define | ATPL230_SFR_ERR_PYL_Msk (ATPL230_SFR_ERR_PYL << ATPL230_SFR_ERR_PYL_Pos) |
| (ATPL230) Unsupported Modulation Scheme flag More... | |
| #define | ATPL230_SFR_CD (0x1u) |
| #define | ATPL230_SFR_CD_Pos 6 |
| #define | ATPL230_SFR_CD_Msk (ATPL230_SFR_CD << ATPL230_SFR_CD_Pos) |
| (ATPL230) Carrier Detect flag More... | |
| #define | ATPL230_SFR_BCH_ERR (0x1u) |
| #define | ATPL230_SFR_BCH_ERR_Pos 7 |
| #define | ATPL230_SFR_BCH_ERR_Msk (ATPL230_SFR_BCH_ERR << ATPL230_SFR_BCH_ERR_Pos) |
| (ATPL230) Busy Channel Error Flag More... | |
FFT Test Mode Register | |
| #define | ATPL230_FFT_MODE_EN (0x1u) |
| #define | ATPL230_FFT_MODE_EN_Pos 0 |
| #define | ATPL230_FFT_MODE_EN_Msk (ATPL230_FFT_MODE_EN << ATPL230_FFT_MODE_EN_Pos) |
| (ATPL230) Enabled/disabled fft test mode More... | |
| #define | ATPL230_FFT_MODE_CONT (0x1u) |
| #define | ATPL230_FFT_MODE_CONT_Pos 1 |
| #define | ATPL230_FFT_MODE_CONT_Msk (ATPL230_FFT_MODE_CONT << ATPL230_FFT_MODE_CONT_Pos) |
| (ATPL230) Enabled/disabled fft test mode More... | |
TXRXBUF_TX_INT : TX Interrupts Register | |
| #define | ATPL230_TXRXBUF_TX_INT_TX0_Msk (1u) |
| (ATPL230) Notice Interrupt Transmission Buffer 0 More... | |
| #define | ATPL230_TXRXBUF_TX_INT_TX1_Msk (2u) |
| (ATPL230) Notice Interrupt Transmission Buffer 1 More... | |
| #define | ATPL230_TXRXBUF_TX_INT_TX2_Msk (4u) |
| (ATPL230) Notice Interrupt Transmission Buffer 2 More... | |
| #define | ATPL230_TXRXBUF_TX_INT_TX3_Msk (8u) |
| (ATPL230) Notice Interrupt Transmission Buffer 3 More... | |
| #define | ATPL230_TXRXBUF_TX_INT_N_Msk (16u) |
| (ATPL230) Notice Interrupt Noise Buffer More... | |
TXRXBUF_RX_INT : RX Interrupts Register | |
| #define | ATPL230_TXRXBUF_RX_INT_HRX0_Msk (1u) |
| (ATPL230) Notice Header Interrupt Reception Buffer 0 More... | |
| #define | ATPL230_TXRXBUF_RX_INT_HRX1_Msk (2u) |
| (ATPL230) Notice Header Interrupt Reception Buffer 1 More... | |
| #define | ATPL230_TXRXBUF_RX_INT_HRX2_Msk (4u) |
| (ATPL230) Notice Header Interrupt Reception Buffer 2 More... | |
| #define | ATPL230_TXRXBUF_RX_INT_HRX3_Msk (8u) |
| (ATPL230) Notice Header Interrupt Reception Buffer 3 More... | |
| #define | ATPL230_TXRXBUF_RX_INT_PRX0_Msk (16u) |
| (ATPL230) Notice Payload Interrupt Reception Buffer 0 More... | |
| #define | ATPL230_TXRXBUF_RX_INT_PRX1_Msk (32u) |
| (ATPL230) Notice Payload Interrupt Reception Buffer 1 More... | |
| #define | ATPL230_TXRXBUF_RX_INT_PRX2_Msk (64u) |
| (ATPL230) Notice Payload Interrupt Reception Buffer 2 More... | |
| #define | ATPL230_TXRXBUF_RX_INT_PRX3_Msk (128u) |
| (ATPL230) Notice Payload Interrupt Reception Buffer 3 More... | |
TXRXBUF_RESULT_TX : TX Result Register | |
| #define | ATPL230_TXRXBUF_RESULT_TX0 (0x7u) |
| #define | ATPL230_TXRXBUF_RESULT_TX0_Pos 8 |
| #define | ATPL230_TXRXBUF_RESULT_TX0_Msk (ATPL230_TXRXBUF_RESULT_TX0 << ATPL230_TXRXBUF_RESULT_TX0_Pos) |
| (ATPL230) Transmission result in buffer 0 More... | |
| #define | ATPL230_TXRXBUF_RESULT_TX1 (0x7u) |
| #define | ATPL230_TXRXBUF_RESULT_TX1_Pos 12 |
| #define | ATPL230_TXRXBUF_RESULT_TX1_Msk (ATPL230_TXRXBUF_RESULT_TX1 << ATPL230_TXRXBUF_RESULT_TX1_Pos) |
| (ATPL230) Transmission result in buffer 1 More... | |
| #define | ATPL230_TXRXBUF_RESULT_TX2 (0x7u) |
| #define | ATPL230_TXRXBUF_RESULT_TX2_Pos 0 |
| #define | ATPL230_TXRXBUF_RESULT_TX2_Msk (ATPL230_TXRXBUF_RESULT_TX2 << ATPL230_TXRXBUF_RESULT_TX2_Pos) |
| (ATPL230) Transmission result in buffer 2 More... | |
| #define | ATPL230_TXRXBUF_RESULT_TX3 (0x7u) |
| #define | ATPL230_TXRXBUF_RESULT_TX3_Pos 4 |
| #define | ATPL230_TXRXBUF_RESULT_TX3_Msk (ATPL230_TXRXBUF_RESULT_TX3 << ATPL230_TXRXBUF_RESULT_TX3_Pos) |
| (ATPL230) Transmission result in buffer 3 More... | |
Values of TXRXBUF_RESULT_TX register | |
| #define | ATPL230_TXRXBUF_RESULT_INPROCESS 0 |
| #define | ATPL230_TXRXBUF_RESULT_SUCCESSFUL 1 |
| #define | ATPL230_TXRXBUF_RESULT_WRONG_LEN 2 |
| #define | ATPL230_TXRXBUF_RESULT_BUSY_CHANNEL 3 |
| #define | ATPL230_TXRXBUF_RESULT_PREV_TX_INPROCESS 4 |
| #define | ATPL230_TXRXBUF_RESULT_RX_INPROCESS 5 |
| #define | ATPL230_TXRXBUF_RESULT_INVALID_SCHEME 6 |
| #define | ATPL230_TXRXBUF_RESULT_TIMEOUT 7 |
TXRXBUF_NOISECONF : Noise Configuration Register | |
| #define | ATPL230_TXRXBUF_NOISECONF_ETN (0x7u) |
| #define | ATPL230_TXRXBUF_NOISECONF_ETN_Pos 5 |
| #define | ATPL230_TXRXBUF_NOISECONF_ETN_Msk (ATPL230_TXRXBUF_NOISECONF_ETN << ATPL230_TXRXBUF_NOISECONF_ETN_Pos) |
| (ATPL230) Noise Error Type More... | |
| #define | ATPL230_TXRXBUF_NOISECONF_EBN (0x1u) |
| #define | ATPL230_TXRXBUF_NOISECONF_EBN_Pos 4 |
| #define | ATPL230_TXRXBUF_NOISECONF_EBN_Msk (ATPL230_TXRXBUF_NOISECONF_EBN << ATPL230_TXRXBUF_NOISECONF_EBN_Pos) |
| (ATPL230) Enable Noise Buffer More... | |
| #define | ATPL230_TXRXBUF_NOISECONF_FTN (0x1u) |
| #define | ATPL230_TXRXBUF_NOISECONF_FTN_Pos 3 |
| #define | ATPL230_TXRXBUF_NOISECONF_FTN_Msk (ATPL230_TXRXBUF_NOISECONF_FTN << ATPL230_TXRXBUF_NOISECONF_FTN_Pos) |
| (ATPL230) Capture Noise Forced More... | |
| #define | ATPL230_TXRXBUF_NOISECONF_NS (0x7u) |
| #define | ATPL230_TXRXBUF_NOISECONF_NS_Pos 0 |
| #define | ATPL230_TXRXBUF_NOISECONF_NS_Msk (ATPL230_TXRXBUF_NOISECONF_NS << ATPL230_TXRXBUF_NOISECONF_NS_Pos) |
| (ATPL230) Number of symbols wanted More... | |
Values of TXRXBUF_NOISECONF ETN | |
| #define | ATPL230_NOISE_CAPTURE_IN_PROCESS 0 |
| #define | ATPL230_NOISE_CAPTURE_SUCCESS 1 |
| #define | ATPL230_NOISE_START_TX 2 |
| #define | ATPL230_NOISE_START_RX 3 |
| #define | ATPL230_NOISE_BCHN_PREV_TX 4 |
| #define | ATPL230_NOISE_BCHN_PREV_RX 5 |
| #define | ATPL230_NOISE_AGCS_VARIATION 6 |
| #define AES_128_KEY_SIZE 16 |
AES 128 Key size.
| #define ATPL230_ATT_PARAM | ( | val | ) | (val & 0xF200) |
Referenced by phy_get_cfg_param(), and phy_set_cfg_param().
| #define ATPL230_ATT_PARAM_MSK 0x0200 |
Referenced by phy_get_cfg_param(), and phy_set_cfg_param().
| #define ATPL230_CFG_PARAM | ( | val | ) | (val & 0xF400) |
Referenced by phy_get_cfg_param(), and phy_set_cfg_param().
| #define ATPL230_CFG_PARAM_MSK 0x0400 |
Referenced by phy_get_cfg_param(), and phy_set_cfg_param().
| #define ATPL230_COPYMSG "Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries." |
| #define ATPL230_FFT_MODE_CONT (0x1u) |
| #define ATPL230_FFT_MODE_CONT_Msk (ATPL230_FFT_MODE_CONT << ATPL230_FFT_MODE_CONT_Pos) |
(ATPL230) Enabled/disabled fft test mode
Referenced by phy_tx_frame().
| #define ATPL230_FFT_MODE_CONT_Pos 1 |
| #define ATPL230_FFT_MODE_EN (0x1u) |
| #define ATPL230_FFT_MODE_EN_Msk (ATPL230_FFT_MODE_EN << ATPL230_FFT_MODE_EN_Pos) |
(ATPL230) Enabled/disabled fft test mode
Referenced by phy_tx_frame().
| #define ATPL230_FFT_MODE_EN_Pos 0 |
| #define ATPL230_GET_HEADER_TYPE | ( | val | ) | ((val >> 4) & 0x03) |
Referenced by pal_data_request_ex(), phy_rx_frame_cb(), and phy_tx_frame().
| #define ATPL230_GET_NOISE_NS | ( | val | ) | (val & ATPL230_TXRXBUF_NOISECONF_NS_Msk) |
Referenced by phy_rx_frame_cb().
| #define ATPL230_GET_NOISE_RESULT | ( | val | ) | ((val & ATPL230_TXRXBUF_NOISECONF_ETN_Msk)>>ATPL230_TXRXBUF_NOISECONF_ETN_Pos) |
Referenced by phy_rx_frame_cb().
| #define ATPL230_GET_ROBO_MODE_RX | ( | id, | |
| val | |||
| ) | (val >> (id<<1)) & ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX0_Msk; |
Referenced by phy_rx_frame_cb().
| #define ATPL230_GET_RXINT_HRX0 | ( | val | ) | (val & ATPL230_TXRXBUF_RX_INT_HRX0_Msk) |
Referenced by _phy_rx_task().
| #define ATPL230_GET_RXINT_HRX1 | ( | val | ) | (val & ATPL230_TXRXBUF_RX_INT_HRX1_Msk) |
| #define ATPL230_GET_RXINT_HRX2 | ( | val | ) | (val & ATPL230_TXRXBUF_RX_INT_HRX2_Msk) |
| #define ATPL230_GET_RXINT_HRX3 | ( | val | ) | (val & ATPL230_TXRXBUF_RX_INT_HRX3_Msk) |
| #define ATPL230_GET_RXINT_PRX0 | ( | val | ) | (val & ATPL230_TXRXBUF_RX_INT_PRX0_Msk) |
Referenced by _phy_rx_task().
| #define ATPL230_GET_RXINT_PRX1 | ( | val | ) | (val & ATPL230_TXRXBUF_RX_INT_PRX1_Msk) |
| #define ATPL230_GET_RXINT_PRX2 | ( | val | ) | (val & ATPL230_TXRXBUF_RX_INT_PRX2_Msk) |
| #define ATPL230_GET_RXINT_PRX3 | ( | val | ) | (val & ATPL230_TXRXBUF_RX_INT_PRX3_Msk) |
| #define ATPL230_GET_SFR_BCH_ERR | ( | val | ) | (val & ATPL230_SFR_BCH_ERR_Msk) |
| #define ATPL230_GET_SFR_CD | ( | val | ) | (val & ATPL230_SFR_CD_Msk) |
| #define ATPL230_GET_SFR_ERR_PYL | ( | val | ) | (val & ATPL230_SFR_ERR_PYL_Msk) |
| #define ATPL230_GET_SFR_UMD | ( | val | ) | (val & ATPL230_SFR_UMD_Msk) |
| #define ATPL230_GET_TX_RESULT_TX0 | ( | val | ) | ((val & ATPL230_TXRXBUF_RESULT_TX0_Msk)>>ATPL230_TXRXBUF_RESULT_TX0_Pos) |
Referenced by phy_tx_frame_result_cb().
| #define ATPL230_GET_TX_RESULT_TX1 | ( | val | ) | ((val & ATPL230_TXRXBUF_RESULT_TX1_Msk)>>ATPL230_TXRXBUF_RESULT_TX1_Pos) |
Referenced by phy_tx_frame_result_cb().
| #define ATPL230_GET_TX_RESULT_TX2 | ( | val | ) | ((val & ATPL230_TXRXBUF_RESULT_TX2_Msk)>>ATPL230_TXRXBUF_RESULT_TX2_Pos) |
Referenced by phy_tx_frame_result_cb().
| #define ATPL230_GET_TX_RESULT_TX3 | ( | val | ) | ((val & ATPL230_TXRXBUF_RESULT_TX3_Msk)>>ATPL230_TXRXBUF_RESULT_TX3_Pos) |
Referenced by phy_tx_frame_result_cb().
| #define ATPL230_GET_TXINT_TX0 | ( | val | ) | (val & ATPL230_TXRXBUF_TX_INT_TX0_Msk) |
Referenced by _phy_tx_result_task().
| #define ATPL230_GET_TXINT_TX1 | ( | val | ) | (val & ATPL230_TXRXBUF_TX_INT_TX1_Msk) |
| #define ATPL230_GET_TXINT_TX2 | ( | val | ) | (val & ATPL230_TXRXBUF_TX_INT_TX2_Msk) |
| #define ATPL230_GET_TXINT_TX3 | ( | val | ) | (val & ATPL230_TXRXBUF_TX_INT_TX3_Msk) |
| #define ATPL230_MAC_EN (0x1u) |
| #define ATPL230_MAC_EN_Msk (ATPL230_MAC_EN << ATPL230_MAC_EN_Pos) |
Referenced by phy_get_mac_en(), phy_mac_crc_disable(), and phy_mac_crc_enable().
| #define ATPL230_MAC_EN_Pos 0 |
| #define ATPL230_NOISE_AGCS_VARIATION 6 |
| #define ATPL230_NOISE_BCHN_PREV_RX 5 |
| #define ATPL230_NOISE_BCHN_PREV_TX 4 |
| #define ATPL230_NOISE_CAPTURE_IN_PROCESS 0 |
| #define ATPL230_NOISE_CAPTURE_SUCCESS 1 |
| #define ATPL230_NOISE_START_RX 3 |
| #define ATPL230_NOISE_START_TX 2 |
| #define ATPL230_PARAM | ( | val | ) | (val & 0xF100) |
Referenced by phy_get_cfg_param(), and phy_set_cfg_param().
| #define ATPL230_PARAM_MSK 0x0100 |
Referenced by phy_get_cfg_param(), and phy_set_cfg_param().
| #define ATPL230_REG_PARAM | ( | val | ) | (val & 0xF000) |
Referenced by pal_cmd_cfg_ex(), phy_cmd_cfg_param(), phy_get_cfg_param(), and phy_set_cfg_param().
| #define ATPL230_REG_PARAM_MSK 0xF000 |
| #define ATPL230_SFR_BCH_ERR (0x1u) |
| #define ATPL230_SFR_BCH_ERR_Msk (ATPL230_SFR_BCH_ERR << ATPL230_SFR_BCH_ERR_Pos) |
(ATPL230) Busy Channel Error Flag
Referenced by phy_tx_frame_result_cb().
| #define ATPL230_SFR_BCH_ERR_Pos 7 |
| #define ATPL230_SFR_CD (0x1u) |
| #define ATPL230_SFR_CD_Msk (ATPL230_SFR_CD << ATPL230_SFR_CD_Pos) |
(ATPL230) Carrier Detect flag
Referenced by phy_carrier_detect_disable(), phy_carrier_detect_enable(), and phy_get_carrier_detect().
| #define ATPL230_SFR_CD_Pos 6 |
| #define ATPL230_SFR_ERR_PYL (0x1u) |
| #define ATPL230_SFR_ERR_PYL_Msk (ATPL230_SFR_ERR_PYL << ATPL230_SFR_ERR_PYL_Pos) |
(ATPL230) Unsupported Modulation Scheme flag
Referenced by phy_clear_sfr_err(), and phy_get_sfr_err().
| #define ATPL230_SFR_ERR_PYL_Pos 4 |
| #define ATPL230_SFR_PHY_INT (0x1u) |
| #define ATPL230_SFR_PHY_INT_Msk (ATPL230_SFR_PHY_INT << ATPL230_SFR_PHY_INT_Pos) |
(ATPL230) Physical Layer interruption
Referenced by phy_clear_global_interrupt().
| #define ATPL230_SFR_PHY_INT_Pos 0 |
| #define ATPL230_SFR_UMD (0x1u) |
| #define ATPL230_SFR_UMD_Msk (ATPL230_SFR_UMD << ATPL230_SFR_UMD_Pos) |
(ATPL230) Unsupported Modulation Scheme flag
| #define ATPL230_SFR_UMD_Pos 5 |
| #define ATPL230_SYS_CONFIG_ERR (0x1u) |
| #define ATPL230_SYS_CONFIG_ERR_Msk (ATPL230_SYS_CONFIG_ERR << ATPL230_SYS_CONFIG_ERR_Pos) |
(ATPL230) Physical Layer Error Flag
| #define ATPL230_SYS_CONFIG_ERR_Pos 1 |
| #define ATPL230_SYS_CONFIG_PD (0x1u) |
| #define ATPL230_SYS_CONFIG_PD_Msk (ATPL230_SYS_CONFIG_PD << ATPL230_SYS_CONFIG_PD_Pos) |
(ATPL230) Converter Power Down
| #define ATPL230_SYS_CONFIG_PD_Pos 3 |
| #define ATPL230_SYS_CONFIG_RST (0x1u) |
| #define ATPL230_SYS_CONFIG_RST_Msk (ATPL230_SYS_CONFIG_RST << ATPL230_SYS_CONFIG_RST_Pos) |
(ATPL230) Physical Layer Reset
Referenced by _init_phy_layer().
| #define ATPL230_SYS_CONFIG_RST_Pos 0 |
| #define ATPL230_SYS_CONFIG_STOP_CLKOUT (0x1u) |
| #define ATPL230_SYS_CONFIG_STOP_CLKOUT_Msk (ATPL230_SYS_CONFIG_STOP_CLKOUT << ATPL230_SYS_CONFIG_STOP_CLKOUT_Pos) |
(ATPL230) Stop output clock
| #define ATPL230_SYS_CONFIG_STOP_CLKOUT_Pos 7 |
| #define ATPL230_SYS_CONFIG_STOP_ENRAM (0x1u) |
| #define ATPL230_SYS_CONFIG_STOP_ENRAM_Msk (ATPL230_SYS_CONFIG_STOP_ENRAM << ATPL230_SYS_CONFIG_STOP_ENRAM_Pos) |
(ATPL230) RAMs Output Enable
Referenced by _init_phy_layer().
| #define ATPL230_SYS_CONFIG_STOP_ENRAM_Pos 7 |
| #define ATPL230_SYS_CONFIG_STOP_GCLK1X (0x1u) |
| #define ATPL230_SYS_CONFIG_STOP_GCLK1X_Msk (ATPL230_SYS_CONFIG_STOP_GCLK1X << ATPL230_SYS_CONFIG_STOP_GCLK1X_Pos) |
(ATPL230) Stop 20MHz clock
| #define ATPL230_SYS_CONFIG_STOP_GCLK1X_Pos 4 |
| #define ATPL230_SYS_CONFIG_STOP_GCLK2X (0x1u) |
| #define ATPL230_SYS_CONFIG_STOP_GCLK2X_Msk (ATPL230_SYS_CONFIG_STOP_GCLK2X << ATPL230_SYS_CONFIG_STOP_GCLK2X_Pos) |
(ATPL230) Stop 40MHz clock
| #define ATPL230_SYS_CONFIG_STOP_GCLK2X_Pos 5 |
| #define ATPL230_SYS_CONFIG_STOP_GCLKNX (0x1u) |
| #define ATPL230_SYS_CONFIG_STOP_GCLKNX_Msk (ATPL230_SYS_CONFIG_STOP_GCLKNX << ATPL230_SYS_CONFIG_STOP_GCLKNX_Pos) |
(ATPL230) Stop 200MHz clock
| #define ATPL230_SYS_CONFIG_STOP_GCLKNX_Pos 6 |
| #define ATPL230_SYS_CONFIG_WDG_EN (0x1u) |
| #define ATPL230_SYS_CONFIG_WDG_EN_Msk (ATPL230_SYS_CONFIG_WDG_EN << ATPL230_SYS_CONFIG_WDG_EN_Pos) |
(ATPL230) Physical Layer Watchdog enable
| #define ATPL230_SYS_CONFIG_WDG_EN_Pos 2 |
| #define ATPL230_TXRXBUF_NOISECONF_EBN (0x1u) |
| #define ATPL230_TXRXBUF_NOISECONF_EBN_Msk (ATPL230_TXRXBUF_NOISECONF_EBN << ATPL230_TXRXBUF_NOISECONF_EBN_Pos) |
(ATPL230) Enable Noise Buffer
Referenced by serial_if_api_parser().
| #define ATPL230_TXRXBUF_NOISECONF_EBN_Pos 4 |
| #define ATPL230_TXRXBUF_NOISECONF_ETN (0x7u) |
| #define ATPL230_TXRXBUF_NOISECONF_ETN_Msk (ATPL230_TXRXBUF_NOISECONF_ETN << ATPL230_TXRXBUF_NOISECONF_ETN_Pos) |
(ATPL230) Noise Error Type
| #define ATPL230_TXRXBUF_NOISECONF_ETN_Pos 5 |
| #define ATPL230_TXRXBUF_NOISECONF_FTN (0x1u) |
| #define ATPL230_TXRXBUF_NOISECONF_FTN_Msk (ATPL230_TXRXBUF_NOISECONF_FTN << ATPL230_TXRXBUF_NOISECONF_FTN_Pos) |
(ATPL230) Capture Noise Forced
Referenced by serial_if_api_parser().
| #define ATPL230_TXRXBUF_NOISECONF_FTN_Pos 3 |
| #define ATPL230_TXRXBUF_NOISECONF_NS (0x7u) |
| #define ATPL230_TXRXBUF_NOISECONF_NS_Msk (ATPL230_TXRXBUF_NOISECONF_NS << ATPL230_TXRXBUF_NOISECONF_NS_Pos) |
(ATPL230) Number of symbols wanted
Referenced by serial_if_api_parser().
| #define ATPL230_TXRXBUF_NOISECONF_NS_Pos 0 |
| #define ATPL230_TXRXBUF_RESULT_BUSY_CHANNEL 3 |
Referenced by phy_tx_frame_result_cb(), and prvGetTxResultTask().
| #define ATPL230_TXRXBUF_RESULT_INPROCESS 0 |
Referenced by phy_tx_frame_result_cb(), and prvGetTxResultTask().
| #define ATPL230_TXRXBUF_RESULT_INVALID_SCHEME 6 |
Referenced by phy_tx_frame_result_cb(), and prvGetTxResultTask().
| #define ATPL230_TXRXBUF_RESULT_PREV_TX_INPROCESS 4 |
Referenced by phy_tx_frame_result_cb(), and prvGetTxResultTask().
| #define ATPL230_TXRXBUF_RESULT_RX_INPROCESS 5 |
Referenced by phy_tx_frame_result_cb(), and prvGetTxResultTask().
| #define ATPL230_TXRXBUF_RESULT_SUCCESSFUL 1 |
Referenced by phy_tx_frame_result_cb(), and prvGetTxResultTask().
| #define ATPL230_TXRXBUF_RESULT_TIMEOUT 7 |
Referenced by phy_tx_frame_result_cb(), and prvGetTxResultTask().
| #define ATPL230_TXRXBUF_RESULT_TX0 (0x7u) |
| #define ATPL230_TXRXBUF_RESULT_TX0_Msk (ATPL230_TXRXBUF_RESULT_TX0 << ATPL230_TXRXBUF_RESULT_TX0_Pos) |
(ATPL230) Transmission result in buffer 0
| #define ATPL230_TXRXBUF_RESULT_TX0_Pos 8 |
| #define ATPL230_TXRXBUF_RESULT_TX1 (0x7u) |
| #define ATPL230_TXRXBUF_RESULT_TX1_Msk (ATPL230_TXRXBUF_RESULT_TX1 << ATPL230_TXRXBUF_RESULT_TX1_Pos) |
(ATPL230) Transmission result in buffer 1
| #define ATPL230_TXRXBUF_RESULT_TX1_Pos 12 |
| #define ATPL230_TXRXBUF_RESULT_TX2 (0x7u) |
| #define ATPL230_TXRXBUF_RESULT_TX2_Msk (ATPL230_TXRXBUF_RESULT_TX2 << ATPL230_TXRXBUF_RESULT_TX2_Pos) |
(ATPL230) Transmission result in buffer 2
| #define ATPL230_TXRXBUF_RESULT_TX2_Pos 0 |
| #define ATPL230_TXRXBUF_RESULT_TX3 (0x7u) |
| #define ATPL230_TXRXBUF_RESULT_TX3_Msk (ATPL230_TXRXBUF_RESULT_TX3 << ATPL230_TXRXBUF_RESULT_TX3_Pos) |
(ATPL230) Transmission result in buffer 3
| #define ATPL230_TXRXBUF_RESULT_TX3_Pos 4 |
| #define ATPL230_TXRXBUF_RESULT_WRONG_LEN 2 |
Referenced by phy_tx_frame_result_cb(), and prvGetTxResultTask().
| #define ATPL230_TXRXBUF_RX_INT_HRX0_Msk (1u) |
(ATPL230) Notice Header Interrupt Reception Buffer 0
Referenced by _phy_rx_task().
| #define ATPL230_TXRXBUF_RX_INT_HRX1_Msk (2u) |
(ATPL230) Notice Header Interrupt Reception Buffer 1
| #define ATPL230_TXRXBUF_RX_INT_HRX2_Msk (4u) |
(ATPL230) Notice Header Interrupt Reception Buffer 2
| #define ATPL230_TXRXBUF_RX_INT_HRX3_Msk (8u) |
(ATPL230) Notice Header Interrupt Reception Buffer 3
| #define ATPL230_TXRXBUF_RX_INT_PRX0_Msk (16u) |
(ATPL230) Notice Payload Interrupt Reception Buffer 0
Referenced by _reset_rx_flag_interrupt().
| #define ATPL230_TXRXBUF_RX_INT_PRX1_Msk (32u) |
(ATPL230) Notice Payload Interrupt Reception Buffer 1
| #define ATPL230_TXRXBUF_RX_INT_PRX2_Msk (64u) |
(ATPL230) Notice Payload Interrupt Reception Buffer 2
| #define ATPL230_TXRXBUF_RX_INT_PRX3_Msk (128u) |
(ATPL230) Notice Payload Interrupt Reception Buffer 3
| #define ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX0 (0x3u) |
| #define ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX0_Msk (ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX0 << ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX0_Pos) |
(ATPL230) Robust Mode Reading in Reception Buffer 0
| #define ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX0_Pos 0 |
| #define ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX1 (0x3u) |
| #define ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX1_Msk (ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX1 << ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX1_Pos) |
(ATPL230) Robust Mode Reading in Reception Buffer 1
| #define ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX1_Pos 2 |
| #define ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX2 (0x3u) |
| #define ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX2_Msk (ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX2 << ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX2_Pos) |
(ATPL230) Robust Mode Reading in Reception Buffer 2
| #define ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX2_Pos 4 |
| #define ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX3 (0x3u) |
| #define ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX3_Msk (ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX3 << ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX3_Pos) |
(ATPL230) Robust Mode Reading in Reception Buffer 3
| #define ATPL230_TXRXBUF_RXCONF_ROBO_MODE_RX3_Pos 6 |
| #define ATPL230_TXRXBUF_TX_INT_N_Msk (16u) |
(ATPL230) Notice Interrupt Noise Buffer
Referenced by _phy_rx_task().
| #define ATPL230_TXRXBUF_TX_INT_TX0_Msk (1u) |
(ATPL230) Notice Interrupt Transmission Buffer 0
Referenced by _phy_tx_result_task().
| #define ATPL230_TXRXBUF_TX_INT_TX1_Msk (2u) |
(ATPL230) Notice Interrupt Transmission Buffer 1
| #define ATPL230_TXRXBUF_TX_INT_TX2_Msk (4u) |
(ATPL230) Notice Interrupt Transmission Buffer 2
| #define ATPL230_TXRXBUF_TX_INT_TX3_Msk (8u) |
(ATPL230) Notice Interrupt Transmission Buffer 3
| #define ATPL230_TXRXBUF_TXCONF_ATR (0x1u) |
| #define ATPL230_TXRXBUF_TXCONF_ATR_Msk (ATPL230_TXRXBUF_TXCONF_ATR << ATPL230_TXRXBUF_TXCONF_ATR_Pos) |
(ATPL230) TxRx control mode
| #define ATPL230_TXRXBUF_TXCONF_ATR_Pos 5 |
| #define ATPL230_TXRXBUF_TXCONF_BF (0x1u) |
| #define ATPL230_TXRXBUF_TXCONF_BF_Msk (ATPL230_TXRXBUF_TXCONF_BF << ATPL230_TXRXBUF_TXCONF_BF_Pos) |
(ATPL230) Bit Flipping mode
Referenced by phy_tx_frame().
| #define ATPL230_TXRXBUF_TXCONF_BF_Pos 4 |
| #define ATPL230_TXRXBUF_TXCONF_BR1 (0x1u) |
(ATPL230) Branch 1 enable/disable for emission
Referenced by phy_tx_frame().
| #define ATPL230_TXRXBUF_TXCONF_BR2 (0x2u) |
(ATPL230) Branch 2 enable/disable for emission
Referenced by phy_tx_frame().
| #define ATPL230_TXRXBUF_TXCONF_BR_Msk (0x3u) |
(ATPL230) Branch select mask
Referenced by phy_tx_frame().
| #define ATPL230_TXRXBUF_TXCONF_DC (0x1u) |
| #define ATPL230_TXRXBUF_TXCONF_DC_Msk (ATPL230_TXRXBUF_TXCONF_DC << ATPL230_TXRXBUF_TXCONF_DC_Pos) |
(ATPL230) Carrier Detect enabled/disabled for emission
Referenced by phy_carrier_detect_buff_disable(), and phy_carrier_detect_buff_enable().
| #define ATPL230_TXRXBUF_TXCONF_DC_Pos 1 |
| #define ATPL230_TXRXBUF_TXCONF_DR (0x1u) |
| #define ATPL230_TXRXBUF_TXCONF_DR_Msk (ATPL230_TXRXBUF_TXCONF_DR << ATPL230_TXRXBUF_TXCONF_DR_Pos) |
(ATPL230) Reception enabled/disabled for emission
Referenced by phy_reception_buff_disable(), and phy_reception_buff_enable().
| #define ATPL230_TXRXBUF_TXCONF_DR_Pos 0 |
| #define ATPL230_TXRXBUF_TXCONF_EB (0x1u) |
| #define ATPL230_TXRXBUF_TXCONF_EB_Msk (ATPL230_TXRXBUF_TXCONF_EB << ATPL230_TXRXBUF_TXCONF_EB_Pos) |
(ATPL230) Buffer enabled/disabled
Referenced by phy_transmission_buff_disable(), phy_transmission_buff_is_enable(), and phy_tx_frame().
| #define ATPL230_TXRXBUF_TXCONF_EB_Pos 2 |
Referenced by phy_transmission_buff_is_enable().
| #define ATPL230_TXRXBUF_TXCONF_FE (0x1u) |
| #define ATPL230_TXRXBUF_TXCONF_FE_Msk (ATPL230_TXRXBUF_TXCONF_FE << ATPL230_TXRXBUF_TXCONF_FE_Pos) |
(ATPL230) Emission forced/unforced
Referenced by phy_force_tx_buff_disable(), and phy_force_tx_buff_enable().
| #define ATPL230_TXRXBUF_TXCONF_FE_Pos 3 |
| #define ATPL230_TXRXBUF_TXCONF_PCO (0x1u) |
| #define ATPL230_TXRXBUF_TXCONF_PCO_Msk (ATPL230_TXRXBUF_TXCONF_PCO << ATPL230_TXRXBUF_TXCONF_PCO_Pos) |
(ATPL230) Peak Cut mode
Referenced by phy_tx_frame().
| #define ATPL230_TXRXBUF_TXCONF_PCO_Pos 7 |
| #define ATPL230_TXRXBUF_TXCONF_TRS (0x1u) |
| #define ATPL230_TXRXBUF_TXCONF_TRS_Msk (ATPL230_TXRXBUF_TXCONF_TRS << ATPL230_TXRXBUF_TXCONF_TRS_Pos) |
(ATPL230) TxRx established by Software
| #define ATPL230_TXRXBUF_TXCONF_TRS_Pos 6 |
| #define ATPL230_VALID_CFG_KEY 0xBA |
Valid chip configuration key.
Referenced by _init_phy_layer().
| #define ATPL230_VERSION_NUM 0x23000102 |
Referenced by _init_phy_layer().
| #define ATPL230_VERSION_STR "23.00.01.02" |
| #define ATPLCOUP000_v1 0x01 |
Referenced by display_config(), get_transmission_coupling(), phy_init_channel_cfg(), and phy_init_coupling_cfg().
| #define ATPLCOUP000_v2 0x02 |
Referenced by display_config(), get_transmission_coupling(), phy_init_channel_cfg(), and phy_init_coupling_cfg().
| #define ATPLCOUP001_v1 0x11 |
Referenced by display_config(), get_transmission_coupling(), phy_init_channel_cfg(), and phy_init_coupling_cfg().
| #define ATPLCOUP002_v1 0x21 |
Referenced by display_config(), get_transmission_coupling(), phy_init_channel_cfg(), and phy_init_coupling_cfg().
| #define ATPLCOUP002_v2 0x22 |
Referenced by display_config(), get_transmission_coupling(), phy_init_channel_cfg(), and phy_init_coupling_cfg().
| #define ATPLCOUP003_v1 0x31 |
Referenced by display_config(), get_transmission_coupling(), phy_init_channel_cfg(), and phy_init_coupling_cfg().
| #define ATPLCOUP004_v1 0x41 |
Referenced by display_config(), get_transmission_coupling(), phy_init_channel_cfg(), and phy_init_coupling_cfg().
| #define ATPLCOUP005_v1 0x51 |
Referenced by display_config(), get_transmission_coupling(), phy_init_channel_cfg(), and phy_init_coupling_cfg().
| #define ATPLCOUP006_v1 0x61 |
Referenced by display_config(), get_transmission_coupling(), phy_init_channel_cfg(), and phy_init_coupling_cfg().
| #define ATPLCOUPXXX_NUM 9 |
Coupling Boards Identifiers.
| #define ATT_0dB 0xFF |
| #define ATT_10dB 0x50 |
| #define ATT_11dB 0x47 |
| #define ATT_12dB 0x40 |
| #define ATT_13dB 0x39 |
| #define ATT_14dB 0x32 |
| #define ATT_15dB 0x2D |
| #define ATT_16dB 0x28 |
| #define ATT_17dB 0x24 |
| #define ATT_18dB 0x20 |
| #define ATT_19dB 0x1C |
| #define ATT_1dB 0xE3 |
| #define ATT_20dB 0x19 |
| #define ATT_21dB 0x16 |
| #define ATT_2dB 0xCA |
| #define ATT_3dB 0xB4 |
| #define ATT_4dB 0xA0 |
| #define ATT_5dB 0x8F |
| #define ATT_6dB 0x7F |
| #define ATT_7dB 0x71 |
| #define ATT_8dB 0x65 |
| #define ATT_9dB 0x5A |
| #define DISABLE_SERIAL 0 |
Referenced by _prime_stack_process().
| #define DRIVER_1 1 |
DRIVER 1.
Referenced by phy_init_coupling_cfg(), and phy_tx_frame().
| #define DRIVER_1_2 3 |
DRIVER 1 + 2.
| #define DRIVER_2 2 |
DRIVER 2.
Referenced by phy_init_coupling_cfg(), and phy_tx_frame().
| #define DRV_POL_TX_0_RX_1 0 |
0 in emission and 1 in reception
Referenced by phy_init_coupling_cfg().
| #define DRV_POL_TX_1_RX_0 1 |
1 in emission and 0 in reception
| #define EMIT_GAIN_CHIRP 0x24 |
| #define EMIT_GAIN_SIGNAL 0x1C |
| #define EXTERNAL_DRV_MODE 2 |
EXTERNAL DRIVER.
Referenced by _update_emit1_mode(), _update_emit2_mode(), phy_init_coupling_cfg(), and phy_tx_frame().
| #define HI_STATE 0 |
High Impedance.
Referenced by auto_impedance_mode(), display_config(), get_impedance_mode(), phy_init_cfg(), phy_tx_frame(), phy_tx_frame_result_cb(), and prvAppPhyTask().
| #define ID_TC_PHY_TX_OFFSET_SYM ID_TC0 |
| #define INTERNAL_DRV_MODE 1 |
INTERNAL DRIVER.
Referenced by phy_init_coupling_cfg().
| #define LENGTH_DATA_ANGLE_REAL_IMAG_COMP (NUM_ROWS_DATA_ANGLE_REAL_IMAG_COMP * LENGTH_ROW_DATA_ANGLE_REAL_IMAG_COMP) |
| #define LENGTH_DATA_CHIRP (NUM_ROWS_DATA_CHIRP * LENGTH_ROW_DATA_CHIRP) |
Referenced by _init_IIR_filter().
| #define LENGTH_DATA_FILTER_IIR (NUM_ROWS_DATA_FILTER_IIR * LENGTH_ROW_DATA_FILTER_IIR) |
| #define LENGTH_DATA_OFFSET_CORRECTION (NUM_ROWS_DATA_OFFSET_CORRECTION * LENGTH_ROW_DATA_OFFSET_CORRECTION) |
| #define LENGTH_ROW_DATA_ANGLE_REAL_IMAG_COMP 2 |
| #define LENGTH_ROW_DATA_CHIRP 4 |
| #define LENGTH_ROW_DATA_FILTER_IIR 2 |
| #define LENGTH_ROW_DATA_OFFSET_CORRECTION 4 |
| #define LO_STATE 1 |
Low Impedance.
Referenced by display_config(), get_impedance_mode(), phy_tx_frame(), and phy_tx_frame_result_cb().
| #define LO_STATE_PK 3 |
Low Impedance + Peak Cut On.
Referenced by phy_tx_frame(), and phy_tx_frame_result_cb().
| #define MAC_GEN_HEADER_SIZE 9 |
Referenced by phy_rx_frame_cb(), and phy_tx_frame().
| #define MAC_HEADER_SIZE 7 |
Referenced by phy_rx_frame_cb(), and phy_tx_frame().
| #define MAX_LEN_D8PSK 11 |
Referenced by _init_phy_layer().
| #define MAX_LEN_D8PSK_VTB 25 |
Referenced by _init_phy_layer().
| #define MAX_LEN_DBPSK 39 |
Referenced by _init_phy_layer().
| #define MAX_LEN_DBPSK_ROBO (MAX_LEN_DBPSK_VTB << 2) |
| #define MAX_LEN_DBPSK_VTB 63 |
Referenced by _init_phy_layer().
| #define MAX_LEN_DQPSK 18 |
Referenced by _init_phy_layer().
| #define MAX_LEN_DQPSK_ROBO (MAX_LEN_DQPSK_VTB << 2) |
| #define MAX_LEN_DQPSK_VTB 39 |
Referenced by _init_phy_layer().
| #define MODE_EF10 0 |
10 MHz
| #define MODE_EF20 1 |
20 MHz
| #define MODE_EF40 2 |
40 MHz
| #define MODE_NOISE 0xFE |
Noise.
Referenced by _serial_if_get_rx_task(), and phy_rx_frame_cb().
| #define MODE_NUM_EF 3 |
Emitter Frecuencies Modes.
| #define MODE_TEST 0xFF |
Test.
Referenced by phy_rx_frame_cb(), and phy_tx_frame().
| #define MODE_TYPE_A 0x00 |
TYPE A FRAME.
Referenced by _serial_if_get_rx_task(), display_config(), get_transmission_mode(), main(), phy_rx_frame_cb(), phy_tx_frame(), serial_if_api_parser(), and sniffer_if_process().
| #define MODE_TYPE_B 0x02 |
TYPE B FRAME.
Referenced by display_config(), get_transmission_mode(), phy_rx_frame_cb(), phy_tx_frame(), and sniffer_if_process().
| #define MODE_TYPE_BC 0x03 |
TYPE BACKWARDS COMPATIBILTY FRAME.
Referenced by display_config(), get_transmission_mode(), phy_rx_frame_cb(), phy_tx_frame(), and sniffer_if_process().
| #define MOL_MINIMUM 21 |
| #define NOT_ALLOWED 0 |
| #define NUM_ROWS_DATA_ANGLE_REAL_IMAG_COMP 97 |
| #define NUM_ROWS_DATA_CHIRP 65 |
Referenced by _init_IIR_filter().
| #define NUM_ROWS_DATA_FILTER_IIR 40 |
Referenced by _init_IIR_filter().
| #define NUM_ROWS_DATA_OFFSET_CORRECTION 16 |
| #define PEAK_CFG_DISABLE 0 |
| #define PEAK_CFG_ENABLE 0x80 |
| #define PHY_CFG_GEN_ERR_INVALID_AES_ENABLE 4 |
Set configuration result: AES not available.
| #define PHY_CFG_INVALID_CHANNEL 3 |
Set configuration result: invalid channel.
Referenced by phy_set_cfg_param().
| #define PHY_CFG_INVALID_INPUT 1 |
Set configuration result: invalid input error or read only.
Referenced by phy_cmd_cfg_param(), phy_get_cfg_param(), and phy_set_cfg_param().
| #define PHY_CFG_READ_ONLY 2 |
Set configuration result: read only.
| #define PHY_CFG_SUCCESS 0 |
Set configuration result: success.
Referenced by phy_cmd_cfg_param(), phy_get_cfg_param(), phy_set_cfg_param(), and serial_if_api_parser().
| #define PHY_CMD_CFG_AND 2 |
AND operation.
Referenced by phy_cmd_cfg_param().
| #define PHY_CMD_CFG_OR 3 |
OR operation.
Referenced by phy_cmd_cfg_param(), and serial_if_api_parser().
| #define PHY_CMD_CFG_READ 0 |
Read operation.
| #define PHY_CMD_CFG_WRITE 1 |
Write operation.
| #define PHY_CMD_CFG_XOR 4 |
XOR operation.
Referenced by phy_cmd_cfg_param().
| #define PHY_DMA_OFFSET 16 |
Referenced by phy_rx_frame_cb(), and phy_tx_frame().
| #define PHY_HT_BEACON 2 |
Header type: BEACON PACKET.
Referenced by pal_data_indication_ex(), pal_data_request_ex(), and phy_rx_frame_cb().
| #define PHY_HT_GENERIC 0 |
Header type: GENERIC PACKET.
Referenced by _get_crc(), pal_data_indication_ex(), and pal_data_request_ex().
| #define PHY_HT_PROMOTION 1 |
Header type: PROMOTION PACKET.
Referenced by _serial_if_sniffer_get_num_symbols().
| #define PHY_ID_CFG_AGC0_KRSSI_OFFSET 0x0409 |
Offset for received signal strength (rssi) according to AGC 0 configuration.
| #define PHY_ID_CFG_AGC1_KRSSI_OFFSET 0x040A |
Offset for received signal strength (rssi) according to AGC 1 configuration.
| #define PHY_ID_CFG_AGC2_KRSSI_OFFSET 0x040B |
Offset for received signal strength (rssi) according to AGC 2 configuration.
| #define PHY_ID_CFG_AGC3_KRSSI_OFFSET 0x040C |
Offset for received signal strength (rssi) according to AGC 3 configuration.
| #define PHY_ID_CFG_AUTODETECT_BRANCH 0x0404 |
Flag to enable branch auto detection.
Referenced by main(), and prvAppPhyTask().
| #define PHY_ID_CFG_COUPLING_BOARD 0x0416 |
Coupling board in use.
Referenced by phy_set_cfg_param(), and prvAppPhyTask().
| #define PHY_ID_CFG_DRIVER1_MODE 0x0400 |
Flag to indicate if driver 1 is extern driver (1) or intern driver (0)
Referenced by phy_set_cfg_param().
| #define PHY_ID_CFG_DRIVER2_MODE 0x0401 |
Flag to indicate if driver 2 is extern driver (1) or intern driver (0)
Referenced by phy_set_cfg_param().
| #define PHY_ID_CFG_EMIT1_ACTIVE 0x0411 |
Emit 1 Active.
| #define PHY_ID_CFG_EMIT2_ACTIVE 0x0412 |
Emit 2 Active.
| #define PHY_ID_CFG_EMIT3_ACTIVE 0x0413 |
Emit 3 Active.
| #define PHY_ID_CFG_EMIT4_ACTIVE 0x0414 |
Emit 4 Active.
| #define PHY_ID_CFG_ENABLE_VLOW_PK 0x0422 |
Flag to enable Peak Cut On in case of low impedance.
| #define PHY_ID_CFG_HIGH_Z_DRIVER 0x0406 |
Select driver for high impedance.
| #define PHY_ID_CFG_IMPEDANCE 0x0405 |
When branch auto detection disabled, indicate impedance to use.
Referenced by main(), and prvAppPhyTask().
| #define PHY_ID_CFG_LOW_Z_DRIVER 0x0407 |
Select driver for high impedance.
| #define PHY_ID_CFG_N1_DELAY 0x040D |
N1 Delay.
| #define PHY_ID_CFG_N2_DELAY 0x040F |
N2 delay.
| #define PHY_ID_CFG_P1_DELAY 0x040E |
P1 Delay.
| #define PHY_ID_CFG_P2_DELAY 0x0410 |
P2 delay.
| #define PHY_ID_CFG_PRIME_MODE 0x0417 |
PRIME mode (see mode values in atpl230.h)
| #define PHY_ID_CFG_RX_CORR_THRESHOLD 0x0420 |
Threshold for autocorrelation filter.
| #define PHY_ID_CFG_TIME_AFTER_TX_HIGHZ 0x041C |
Time (unit depends on platform) for HIMP pin after transmission with high impedance.
| #define PHY_ID_CFG_TIME_AFTER_TX_LOWZ 0x041E |
Time (unit depends on platform) for TXRX pin after transmission with low impedance.
| #define PHY_ID_CFG_TIME_BEFORE_TX_HIGHZ 0x0418 |
Time in 10's of us for HIMP pin before transmission with high impedance.
| #define PHY_ID_CFG_TIME_BEFORE_TX_LOWZ 0x041A |
Time in 10's of us for TXRX pin before transmission with low impedance.
| #define PHY_ID_CFG_TXRX1_POLARITY 0x0402 |
Flag to indicate if txrx1 polarity is high or low active.
Referenced by phy_set_cfg_param().
| #define PHY_ID_CFG_TXRX2_POLARITY 0x0403 |
Flag to indicate if txrx2 polarity is high or low active.
Referenced by phy_set_cfg_param().
| #define PHY_ID_CFG_TXRX_CHANNEL 0x0415 |
Transmission/Reception Channel.
Referenced by _serial_if_get_rx_task(), _serial_if_get_tx_result_task(), phy_set_cfg_param(), prvAppPhyTask(), serial_if_sniffer_api_parser(), and sniffer_if_process().
| #define PHY_ID_CFG_VLOW_Z_DRIVER 0x0408 |
Select driver for high impedance.
| #define PHY_ID_INFO_MODEL 0x010A |
Model identifier.
| #define PHY_ID_INFO_PRODUCT 0x0100 |
Product identifier.
| #define PHY_ID_INFO_VERSION 0x010C |
Version identifier.
| #define PHY_ID_RX_BUFFER_ID 0x0111 |
Buffer identifier of received message.
Referenced by pal_zct_get().
| #define PHY_ID_RX_INFO_HEADER_RCV 0x0114 |
Flag to indicate if header has already been received.
| #define PHY_ID_RX_INFO_MODE 0x0115 |
Payload length in OFDM symbols.
| #define PHY_ID_RX_INFO_SCHEME 0x0113 |
Modulation Scheme of last received message.
| #define PHY_ID_RX_PAYLOAD_LEN 0x011E |
RX Payload length in bytes.
| #define PHY_ID_RX_PAYLOAD_LEN_SYM 0x0120 |
RX Payload length in OFDM symbols.
Referenced by sniffer_if_process().
| #define PHY_ID_RX_QR_MODE_ID 0x0112 |
Flag to enable / disable Rx Quality Report Mode.
Referenced by pal_init(), and sniffer_if_init().
| #define PHY_ID_STATS_RX_BAD_CRC 0x015C |
Bad CRC in received message.
| #define PHY_ID_STATS_RX_BAD_LEN 0x0158 |
Bad len in message (too short - too long)
| #define PHY_ID_STATS_RX_TOTAL 0x014C |
Received correctly messages count.
| #define PHY_ID_STATS_RX_TOTAL_BYTES 0x0150 |
Received bytes count.
| #define PHY_ID_STATS_RX_TOTAL_ERRORS 0x0154 |
Reception errors count.
| #define PHY_ID_STATS_TX_BAD_BUSY_CHANNEL 0x013C |
Transmission failure owing to busy channel.
| #define PHY_ID_STATS_TX_BAD_BUSY_TX 0x0138 |
Already in transmission.
| #define PHY_ID_STATS_TX_BAD_FORMAT 0x0144 |
Message to transmit in bad format.
| #define PHY_ID_STATS_TX_BAD_LEN 0x0140 |
Bad len in message (too short - too long)
| #define PHY_ID_STATS_TX_TIMEOUT 0x0148 |
Timeout error in transmission.
| #define PHY_ID_STATS_TX_TOTAL 0x012C |
Transmitted correctly messages count.
| #define PHY_ID_STATS_TX_TOTAL_BYTES 0x0130 |
Transmitted bytes count.
| #define PHY_ID_STATS_TX_TOTAL_ERRORS 0x0134 |
Transmission errors count.
| #define PHY_ID_TX1_ATT_CHIRP_HIGHZ 0x0202 |
Channel_1 Attenuation chirp in High impedance.
| #define PHY_ID_TX1_ATT_CHIRP_LOWZ 0x0204 |
Channel_1 Attenuation chirp in low impedance.
| #define PHY_ID_TX1_ATT_CHIRP_VLOWZ 0x0206 |
Channel_1 Attenuation chirp in very low impedance.
| #define PHY_ID_TX1_ATT_SIGNAL_HIGHZ 0x0203 |
Channel_1 Attenuation signal in High impedance.
| #define PHY_ID_TX1_ATT_SIGNAL_LOWZ 0x0205 |
Channel_1 Attenuation signal in low impedance.
| #define PHY_ID_TX1_ATT_SIGNAL_VLOWZ 0x0207 |
Channel_1 Attenuation signal in very low impedance.
| #define PHY_ID_TX1_LOAD_THRESHOLD1 0x0208 |
Channel_1 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX1_LOAD_THRESHOLD2 0x020A |
Channel_1 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX1_LOAD_THRESHOLD3 0x020C |
Channel_1 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX1_LOAD_THRESHOLD4 0x020E |
Channel_1 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX2_ATT_CHIRP_HIGHZ 0x0210 |
Channel_2 Attenuation chirp in High impedance.
| #define PHY_ID_TX2_ATT_CHIRP_LOWZ 0x0212 |
Channel_2 Attenuation chirp in low impedance.
| #define PHY_ID_TX2_ATT_CHIRP_VLOWZ 0x0214 |
Channel_2 Attenuation chirp in very low impedance.
| #define PHY_ID_TX2_ATT_SIGNAL_HIGHZ 0x0211 |
Channel_2 Attenuation signal in High impedance.
| #define PHY_ID_TX2_ATT_SIGNAL_LOWZ 0x0213 |
Channel_2 Attenuation signal in low impedance.
| #define PHY_ID_TX2_ATT_SIGNAL_VLOWZ 0x0215 |
Channel_2 Attenuation signal in very low impedance.
| #define PHY_ID_TX2_LOAD_THRESHOLD1 0x0216 |
Channel_2 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX2_LOAD_THRESHOLD2 0x0218 |
Channel_2 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX2_LOAD_THRESHOLD3 0x021A |
Channel_2 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX2_LOAD_THRESHOLD4 0x021C |
Channel_2 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX3_ATT_CHIRP_HIGHZ 0x021E |
Channel_3 Attenuation chirp in High impedance.
| #define PHY_ID_TX3_ATT_CHIRP_LOWZ 0x0220 |
Channel_3 Attenuation chirp in low impedance.
| #define PHY_ID_TX3_ATT_CHIRP_VLOWZ 0x0222 |
Channel_3 Attenuation chirp in very low impedance.
| #define PHY_ID_TX3_ATT_SIGNAL_HIGHZ 0x021F |
Channel_3 Attenuation signal in High impedance.
| #define PHY_ID_TX3_ATT_SIGNAL_LOWZ 0x0221 |
Channel_3 Attenuation signal in low impedance.
| #define PHY_ID_TX3_ATT_SIGNAL_VLOWZ 0x0223 |
Channel_3 Attenuation signal in very low impedance.
| #define PHY_ID_TX3_LOAD_THRESHOLD1 0x0224 |
Channel_3 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX3_LOAD_THRESHOLD2 0x0226 |
Channel_3 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX3_LOAD_THRESHOLD3 0x0228 |
Channel_3 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX3_LOAD_THRESHOLD4 0x022A |
Channel_3 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX4_ATT_CHIRP_HIGHZ 0x022C |
Channel_4 Attenuation chirp in High impedance.
| #define PHY_ID_TX4_ATT_CHIRP_LOWZ 0x022E |
Channel_4 Attenuation chirp in low impedance.
| #define PHY_ID_TX4_ATT_CHIRP_VLOWZ 0x0230 |
Channel_4 Attenuation chirp in very low impedance.
| #define PHY_ID_TX4_ATT_SIGNAL_HIGHZ 0x022D |
Channel_4 Attenuation signal in High impedance.
| #define PHY_ID_TX4_ATT_SIGNAL_LOWZ 0x022F |
Channel_4 Attenuation signal in low impedance.
| #define PHY_ID_TX4_ATT_SIGNAL_VLOWZ 0x0231 |
Channel_4 Attenuation signal in very low impedance.
| #define PHY_ID_TX4_LOAD_THRESHOLD1 0x0232 |
Channel_4 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX4_LOAD_THRESHOLD2 0x0234 |
Channel_4 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX4_LOAD_THRESHOLD3 0x0236 |
Channel_4 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX4_LOAD_THRESHOLD4 0x0238 |
Channel_4 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX5_ATT_CHIRP_HIGHZ 0x023A |
Channel_5 Attenuation chirp in High impedance.
| #define PHY_ID_TX5_ATT_CHIRP_LOWZ 0x023C |
Channel_5 Attenuation chirp in low impedance.
| #define PHY_ID_TX5_ATT_CHIRP_VLOWZ 0x023E |
Channel_5 Attenuation chirp in very low impedance.
| #define PHY_ID_TX5_ATT_SIGNAL_HIGHZ 0x023B |
Channel_5 Attenuation signal in High impedance.
| #define PHY_ID_TX5_ATT_SIGNAL_LOWZ 0x023D |
Channel_5 Attenuation signal in low impedance.
| #define PHY_ID_TX5_ATT_SIGNAL_VLOWZ 0x023F |
Channel_5 Attenuation signal in very low impedance.
| #define PHY_ID_TX5_LOAD_THRESHOLD1 0x0240 |
Channel_5 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX5_LOAD_THRESHOLD2 0x0242 |
Channel_5 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX5_LOAD_THRESHOLD3 0x0244 |
Channel_5 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX5_LOAD_THRESHOLD4 0x0246 |
Channel_5 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX6_ATT_CHIRP_HIGHZ 0x0248 |
Channel_6 Attenuation chirp in High impedance.
| #define PHY_ID_TX6_ATT_CHIRP_LOWZ 0x024A |
Channel_6 Attenuation chirp in low impedance.
| #define PHY_ID_TX6_ATT_CHIRP_VLOWZ 0x024C |
Channel_6 Attenuation chirp in very low impedance.
| #define PHY_ID_TX6_ATT_SIGNAL_HIGHZ 0x0249 |
Channel_6 Attenuation signal in High impedance.
| #define PHY_ID_TX6_ATT_SIGNAL_LOWZ 0x024B |
Channel_6 Attenuation signal in low impedance.
| #define PHY_ID_TX6_ATT_SIGNAL_VLOWZ 0x024D |
Channel_6 Attenuation signal in very low impedance.
| #define PHY_ID_TX6_LOAD_THRESHOLD1 0x024E |
Channel_6 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX6_LOAD_THRESHOLD2 0x0250 |
Channel_6 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX6_LOAD_THRESHOLD3 0x0252 |
Channel_6 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX6_LOAD_THRESHOLD4 0x0254 |
Channel_6 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX7_ATT_CHIRP_HIGHZ 0x0256 |
Channel_7 Attenuation chirp in High impedance.
| #define PHY_ID_TX7_ATT_CHIRP_LOWZ 0x0258 |
Channel_7 Attenuation chirp in low impedance.
| #define PHY_ID_TX7_ATT_CHIRP_VLOWZ 0x025A |
Channel_7 Attenuation chirp in very low impedance.
| #define PHY_ID_TX7_ATT_SIGNAL_HIGHZ 0x0257 |
Channel_7 Attenuation signal in High impedance.
| #define PHY_ID_TX7_ATT_SIGNAL_LOWZ 0x0259 |
Channel_7 Attenuation signal in low impedance.
| #define PHY_ID_TX7_ATT_SIGNAL_VLOWZ 0x025B |
Channel_7 Attenuation signal in very low impedance.
| #define PHY_ID_TX7_LOAD_THRESHOLD1 0x025C |
Channel_7 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX7_LOAD_THRESHOLD2 0x025E |
Channel_7 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX7_LOAD_THRESHOLD3 0x0260 |
Channel_7 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX7_LOAD_THRESHOLD4 0x0262 |
Channel_7 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX8_ATT_CHIRP_HIGHZ 0x0264 |
Channel_8 Attenuation chirp in High impedance.
| #define PHY_ID_TX8_ATT_CHIRP_LOWZ 0x0266 |
Channel_8 Attenuation chirp in low impedance.
| #define PHY_ID_TX8_ATT_CHIRP_VLOWZ 0x0268 |
Channel_8 Attenuation chirp in very low impedance.
| #define PHY_ID_TX8_ATT_SIGNAL_HIGHZ 0x0265 |
Channel_8 Attenuation signal in High impedance.
| #define PHY_ID_TX8_ATT_SIGNAL_LOWZ 0x0267 |
Channel_8 Attenuation signal in low impedance.
| #define PHY_ID_TX8_ATT_SIGNAL_VLOWZ 0x0269 |
Channel_8 Attenuation signal in very low impedance.
| #define PHY_ID_TX8_LOAD_THRESHOLD1 0x026A |
Channel_8 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX8_LOAD_THRESHOLD2 0x026C |
Channel_8 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX8_LOAD_THRESHOLD3 0x026E |
Channel_8 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX8_LOAD_THRESHOLD4 0x0270 |
Channel_8 Threshold for RMS calculated to detect load type.
| #define PHY_ID_TX_ATT_GLOBAL 0x0200 |
Global attenuation.
| #define PHY_ID_TX_BUFFER_ID 0x0117 |
Buffer identifier of transmitted message.
Referenced by pal_nl_get().
| #define PHY_ID_TX_CHN1 0x000150C7 |
| #define PHY_ID_TX_CHN2 0x00026A44 |
| #define PHY_ID_TX_CHN3 0x000383C1 |
| #define PHY_ID_TX_CHN4 0x00049D3D |
| #define PHY_ID_TX_CHN5 0x0005B6BA |
| #define PHY_ID_TX_CHN6 0x0006D036 |
| #define PHY_ID_TX_CHN7 0x0007E9B3 |
| #define PHY_ID_TX_CHN8 0x00090330 |
| #define PHY_ID_TX_INFO_DISABLE_RX 0x011C |
Flag to enable / disable reception at transmission start.
| #define PHY_ID_TX_INFO_LEVEL 0x0118 |
Level parameter of last transmitted message.
| #define PHY_ID_TX_INFO_MODE 0x011B |
Mode PRIME v1.3, PRIME v1.4 or PRIME v1.4 backward compatible.
| #define PHY_ID_TX_INFO_SCHEME 0x0119 |
Modulation scheme of last transmitted message.
| #define PHY_ID_TX_INFO_TDELAY 0x0128 |
Delay for transmission in 10's of us.
| #define PHY_ID_TX_PAYLOAD_LEN_SYM 0x0122 |
TX Payload length in OFDM symbols.
| #define PHY_ID_TX_QR_MODE_ID 0x011A |
Flag to enable / disable Tx Quality Report Mode.
Referenced by pal_init().
| #define PHY_MAX_PPDU_SIZE 512 |
Maximum physical pdu size.
Referenced by _init_phy_layer(), phy_rx_frame_cb(), and phy_tx_frame().
| #define PHY_NUM_CHANNELS 8 |
Configuration Identifiers.
| #define PHY_NUM_RX_BUFFERS 4 |
Number of reception buffers.
Referenced by _init_phy_layer(), and phy_rx_frame_cb().
| #define PHY_NUM_TX_BUFFERS 4 |
Number of transmission buffers.
Referenced by _init_phy_layer(), phy_tx_frame(), and phy_tx_frame_result_cb().
| #define PHY_RESET_HARD_TYPE 0 |
Referenced by _init_phy_layer(), phy_init(), and serial_if_api_parser().
| #define PHY_RESET_SOFT_TYPE 1 |
Referenced by pal_set_cfg_ex(), phy_tx_frame_result_cb(), prvAppPhyTask(), and serial_if_api_parser().
| #define PHY_TX_MIN_DELAY 10 /* 100 us. */ |
Referenced by phy_tx_frame().
| #define PHY_TX_RESULT_BUSY_CH ATPL230_TXRXBUF_RESULT_BUSY_CHANNEL |
Transmission result: busy channel error.
| #define PHY_TX_RESULT_BUSY_RX ATPL230_TXRXBUF_RESULT_RX_INPROCESS |
Transmission result: busy reception error.
| #define PHY_TX_RESULT_BUSY_TX ATPL230_TXRXBUF_RESULT_PREV_TX_INPROCESS |
Transmission result: busy transmission error.
| #define PHY_TX_RESULT_INV_BUFFER 8 |
Transmission result: invalid buffer identifier error.
Referenced by phy_tx_frame().
| #define PHY_TX_RESULT_INV_LENGTH ATPL230_TXRXBUF_RESULT_WRONG_LEN |
Transmission result: invalid length error.
Referenced by phy_tx_frame().
| #define PHY_TX_RESULT_INV_PRIME_MODE 9 |
Transmission result: invalid Prime Mode error.
Referenced by phy_tx_frame().
| #define PHY_TX_RESULT_INV_SCHEME ATPL230_TXRXBUF_RESULT_INVALID_SCHEME |
Transmission result: invalid scheme error.
Referenced by phy_tx_frame().
| #define PHY_TX_RESULT_PROCESS ATPL230_TXRXBUF_RESULT_INPROCESS |
Transmission result: already in process.
Referenced by pal_data_request_ex(), pal_get_cfg_ex(), and phy_tx_frame().
| #define PHY_TX_RESULT_SUCCESS ATPL230_TXRXBUF_RESULT_SUCCESSFUL |
Transmission result: end successfully.
| #define PHY_TX_RESULT_TIMEOUT ATPL230_TXRXBUF_RESULT_TIMEOUT |
Transmission result: timeout error.
| #define PHY_TX_SCHEDULING_MODE_ABSOLUTE 0 |
Absolute TX scheduling mode (absolute TX time specified)
Referenced by pal_data_request().
| #define PHY_TX_SCHEDULING_MODE_RELATIVE 1 |
Relative TX scheduling mode (delay for TX time specified)
Referenced by main(), and phy_tx_frame().
| #define PHY_TX_TIMEOUT_DELAYED 1500 /* 1.5 second */ |
| #define PHY_TX_TIMEOUT_DELAYED_10US PHY_TX_TIMEOUT_DELAYED * 100 |
| #define PHY_TX_TIMEOUT_IMMEDIATE 750 /* 750 ms */ |
| #define PHY_TX_TIMEOUT_IMMEDIATE_10US PHY_TX_TIMEOUT_IMMEDIATE * 100 |
Referenced by _init_phy_layer().
| #define PROTOCOL_D8PSK 0x02 |
Modulation scheme of the payload: Differential 8PSK.
Referenced by display_config(), and phy_tx_frame().
| #define PROTOCOL_D8PSK_VTB 0x06 |
Modulation scheme of the payload: Differential 8PSK with Convolutional Coding.
Referenced by display_config(), and phy_tx_frame().
| #define PROTOCOL_DBPSK 0x00 |
Modulation scheme of the payload: Differential BPSK.
Referenced by display_config(), and phy_tx_frame().
| #define PROTOCOL_DBPSK_ROBO 0x0C |
Modulation scheme of the payload: Differential BPSK with ROBO Mode.
Referenced by display_config(), and phy_tx_frame().
| #define PROTOCOL_DBPSK_VTB 0x04 |
Modulation scheme of the payload: Differential BPSK with Convolutional Coding.
Referenced by display_config(), main(), and phy_tx_frame().
| #define PROTOCOL_DQPSK 0x01 |
Modulation scheme of the payload: Differential QPSK.
Referenced by display_config(), and phy_tx_frame().
| #define PROTOCOL_DQPSK_ROBO 0x0D |
Modulation scheme of the payload: Differential QPSK with ROBO Mode.
Referenced by display_config(), and phy_tx_frame().
| #define PROTOCOL_DQPSK_VTB 0x05 |
Modulation scheme of the payload: Differential QPSK with Convolutional Coding.
Referenced by display_config(), and phy_tx_frame().
| #define REG_ATPL230_AFE_1023 (0xFEFE) |
| #define REG_ATPL230_AFE_CTL (0xFE90) |
Referenced by _update_txrx1_polarity(), and _update_txrx2_polarity().
| #define REG_ATPL230_AGC0_KRSSI (0xFE5C) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_AGC1_KRSSI (0xFE5D) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_AGC2_KRSSI (0xFE5F) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_AGC3_KRSSI (0xFE60) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_AGC_CTL (0xFF76) |
| #define REG_ATPL230_AGC_CTL_AUX (0xFF75) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_AGC_THRESHOLD_HIGH (0xFEB2) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_AGC_THRESHOLD_LOW (0xFEB3) |
| #define REG_ATPL230_CD_CONTROL (0xFF8D) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_CRC32_MAC_HIGH (0xFEBA) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_CRC32_MAC_LOW (0xFEBB) |
| #define REG_ATPL230_CRC8_MAC_HD_HIGH (0xFEC0) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_CRC8_MAC_HD_LOW (0xFEC1) |
| #define REG_ATPL230_CRC8_MAC_HIGH (0xFEBC) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_CRC8_MAC_LOW (0xFEBD) |
| #define REG_ATPL230_CRC8_PHY_HIGH (0xFEC2) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_CRC8_PHY_LOW (0xFEC3) |
| #define REG_ATPL230_EMIT1_ACTIVE (0xFEA3) |
Referenced by _update_emit1_mode().
| #define REG_ATPL230_EMIT2_ACTIVE (0xFEA4) |
Referenced by _update_emit1_mode().
| #define REG_ATPL230_EMIT3_ACTIVE (0xFEA5) |
Referenced by _update_emit2_mode().
| #define REG_ATPL230_EMIT4_ACTIVE (0xFEA6) |
Referenced by _update_emit2_mode().
| #define REG_ATPL230_EMIT_CONFIG (0xFE8F) |
Referenced by _update_emit1_mode(), and _update_emit2_mode().
| #define REG_ATPL230_EMITTER_FREC (0xFEDB) |
Referenced by _update_channel().
| #define REG_ATPL230_EQUALIZE_H (0xFF5E) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_EQUALIZE_L (0xFF5F) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FACTOR_COMP_DOWN (0xFF94) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FACTOR_COMP_DOWN_ROBO (0xFF3A) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FACTOR_COMP_UP (0xFF97) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FACTOR_COMP_UP_ROBO (0xFF3B) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FACTOR_ROBUST (0xFF54) |
| #define REG_ATPL230_FACTOR_ROBUST_3_2 (0xFF58) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FACTOR_THR_CTL (0xFF95) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FACTOR_THRESHOLD_2_3_AND_1_3 (0xFF56) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FACTOR_THRESHOLD_3_AND_2 (0xFF55) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FACTOR_THRESHOLD_4_AND_1 (0xFF51) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FFT_MODE (0xFEB0) |
Referenced by phy_tx_frame().
| #define REG_ATPL230_FILTER_MIN_HIGH (0xFE53) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FILTER_MIN_LOW (0xFE55) |
| #define REG_ATPL230_FILTER_MIN_MED (0xFE54) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_CORR_MIN (0xFF9F) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_CORR_MIN_ROBO (0xFF43) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_MAX_FACTOR_TH (0xFF9E) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_MAX_FACTOR_TH_ROBO (0xFF42) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_MIN_FACTOR_TH (0xFF9D) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_MIN_FACTOR_TH_ROBO (0xFF41) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_STEP_DOWN (0xFF9C) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_STEP_DOWN_ROBO (0xFF40) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_STEP_UP (0xFF9A) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_STEP_UP_FD (0xFF9B) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_STEP_UP_FD_ROBO (0xFF3F) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_STEP_UP_ROBO (0xFF3E) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_SUMADOR_CONF (0xFF93) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_TIME_DOWN (0xFF98) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_TIME_DOWN_ROBO (0xFF3C) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_TIME_UP (0xFF99) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_FT_TIME_UP_ROBO (0xFF3D) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_HIGH_TIMER_BEACON_REF (0xFE48) |
| #define REG_ATPL230_IIR_CONFIG (0xFED3) |
Referenced by _init_IIR_filter(), and _init_phy_layer().
| #define REG_ATPL230_INI_CHIRP1 (0xFF52) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_INI_CHIRP2 (0xFF53) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_LOAD_ADDRH (0xFF78) |
Referenced by _init_IIR_filter().
| #define REG_ATPL230_LOAD_ADDRL (0xFF79) |
Referenced by _store_filter_sec().
| #define REG_ATPL230_LOAD_CTL (0xFF80) |
Referenced by _init_IIR_filter(), and _init_phy_layer().
| #define REG_ATPL230_LOW_TIMER_BEACON_REF (0xFE4A) |
| #define REG_ATPL230_MAX_LEN_D8PSK (0xFECC) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_MAX_LEN_D8PSK_VTB (0xFECD) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_MAX_LEN_DBPSK (0xFEC8) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_MAX_LEN_DBPSK_VTB (0xFEC9) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_MAX_LEN_DQPSK (0xFECA) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_MAX_LEN_DQPSK_VTB (0xFECB) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_MED_TIMER_BEACON_REF (0xFE49) |
| #define REG_ATPL230_MIN_M_TH_HIGH (0xFF87) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_MIN_M_TH_LOW (0xFF88) |
| #define REG_ATPL230_MIN_R_TH (0xFF8B) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_MODE_CONJ (0xFEE0) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_N1_DELAY (0xFE9F) |
Referenced by _update_emit1_mode().
| #define REG_ATPL230_N2_DELAY (0xFEA1) |
Referenced by _update_emit2_mode().
| #define REG_ATPL230_N_CHIRP (0xFF84) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_N_MOD (0xFF81) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_N_RAMPH (0xFF82) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_N_RAMPL (0xFF83) |
| #define REG_ATPL230_NUM_AGCS_NOISE (0xFDFF) |
| #define REG_ATPL230_NUM_AGCS_RX0 (0xFDE6) |
| #define REG_ATPL230_NUM_AGCS_RX1 (0xFDE7) |
| #define REG_ATPL230_NUM_AGCS_RX2 (0xFDE8) |
| #define REG_ATPL230_NUM_AGCS_RX3 (0xFDE9) |
| #define REG_ATPL230_P1_DELAY (0xFEA0) |
Referenced by _update_emit1_mode().
| #define REG_ATPL230_P2_DELAY (0xFEA2) |
Referenced by _update_emit2_mode().
| #define REG_ATPL230_PASO_FASE_CORDIC_TX_H (0xFEFB) |
| #define REG_ATPL230_PASO_FASE_CORDIC_TX_L (0xFEFD) |
| #define REG_ATPL230_PASO_FASE_CORDIC_TX_M (0xFEFC) |
| #define REG_ATPL230_PASO_FASE_CORDIC_TX_VH (0xFEFA) |
Referenced by _update_channel().
| #define REG_ATPL230_PHY_CONFIG (0xFE68) |
Referenced by _init_phy_layer(), phy_get_mac_en(), phy_mac_crc_disable(), and phy_mac_crc_enable().
| #define REG_ATPL230_PHY_NOISE_INIT_ADDRESS 0x0000 |
Referenced by _init_phy_layer(), and phy_rx_frame_cb().
| #define REG_ATPL230_PHY_RX_INIT_ADDRESS (REG_ATPL230_PHY_TX_INIT_ADDRESS + PHY_MAX_PPDU_SIZE * PHY_NUM_TX_BUFFERS) |
Referenced by _init_phy_layer(), and phy_rx_frame_cb().
| #define REG_ATPL230_PHY_SFR (0xFE2A) |
| #define REG_ATPL230_PHY_TX_INIT_ADDRESS 0x0000 |
Referenced by _init_phy_layer(), and phy_tx_frame().
| #define REG_ATPL230_POSITIVE_FAIL_CONFIG (0xFEC4) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_POSITIVE_FAIL_HIGH (0xFEC5) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_POSITIVE_FAIL_LOW (0xFEC6) |
| #define REG_ATPL230_R_MARGIN (0xFF8C) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_ROBO_RX_TIME_OFFSET (0xFEB7) |
| #define REG_ATPL230_RSSI_OFFSET (0xFF4C) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_RX_TIME_OFFSET (0xFEB4) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_SNA0 (0xFE62) |
Referenced by _init_phy_layer(), phy_set_cfg_param(), serial_if_init(), sniffer_if_init(), sniffer_if_process(), and vPhyEmbeddedAppTask().
| #define REG_ATPL230_SNA1 (0xFE63) |
| #define REG_ATPL230_SNA2 (0xFE64) |
| #define REG_ATPL230_SNA3 (0xFE65) |
| #define REG_ATPL230_SNA4 (0xFE66) |
| #define REG_ATPL230_SNA5 (0xFE67) |
| #define REG_ATPL230_SOFT_STOP_TIMEH (0xFECE) |
Referenced by _init_phy_layer(), and phy_tx_frame().
| #define REG_ATPL230_SOFT_STOP_TIMEL (0xFECF) |
| #define REG_ATPL230_SOFT_TIME_X1_H (0xFF33) |
Referenced by _init_phy_layer(), and phy_tx_frame().
| #define REG_ATPL230_SOFT_TIME_X1_L (0xFF34) |
| #define REG_ATPL230_SOFT_TIME_X2_H (0xFF35) |
Referenced by _init_phy_layer(), and phy_tx_frame().
| #define REG_ATPL230_SOFT_TIME_X2_L (0xFF36) |
| #define REG_ATPL230_SOFT_TIME_Y1 (0xFF37) |
Referenced by _init_phy_layer(), and phy_tx_frame().
| #define REG_ATPL230_SOFT_TIME_Y2 (0xFF38) |
Referenced by _init_phy_layer(), and phy_tx_frame().
| #define REG_ATPL230_STEP_M_DOWN (0xFF86) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_STEP_M_UP (0xFF85) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_STEP_R_DOWN (0xFF8A) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_STEP_R_UP (0xFF89) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_SYS_CONFIG (0xFE2C) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_TX_DELAY_SAMPLES (0xFE57) |
| #define REG_ATPL230_TXRXBUF_BERHARD_AVG_RX0 (0xFD63) |
| #define REG_ATPL230_TXRXBUF_BERHARD_AVG_RX1 (0xFD64) |
| #define REG_ATPL230_TXRXBUF_BERHARD_AVG_RX2 (0xFD65) |
| #define REG_ATPL230_TXRXBUF_BERHARD_AVG_RX3 (0xFD66) |
| #define REG_ATPL230_TXRXBUF_BERHARD_MAX_RX0 (0xFD67) |
| #define REG_ATPL230_TXRXBUF_BERHARD_MAX_RX1 (0xFD68) |
| #define REG_ATPL230_TXRXBUF_BERHARD_MAX_RX2 (0xFD69) |
| #define REG_ATPL230_TXRXBUF_BERHARD_MAX_RX3 (0xFD6A) |
| #define REG_ATPL230_TXRXBUF_BERHARD_RX0 (0xFD5F) |
Mapped addresses for Viterbi hard Bit Error Rate value.
| #define REG_ATPL230_TXRXBUF_BERHARD_RX1 (0xFD60) |
| #define REG_ATPL230_TXRXBUF_BERHARD_RX2 (0xFD61) |
| #define REG_ATPL230_TXRXBUF_BERHARD_RX3 (0xFD62) |
| #define REG_ATPL230_TXRXBUF_BERSOFT_AVG_RX0 (0xFD57) |
| #define REG_ATPL230_TXRXBUF_BERSOFT_AVG_RX1 (0xFD58) |
| #define REG_ATPL230_TXRXBUF_BERSOFT_AVG_RX2 (0xFD59) |
| #define REG_ATPL230_TXRXBUF_BERSOFT_AVG_RX3 (0xFD5A) |
| #define REG_ATPL230_TXRXBUF_BERSOFT_MAX_RX0 (0xFD5B) |
| #define REG_ATPL230_TXRXBUF_BERSOFT_MAX_RX1 (0xFD5C) |
| #define REG_ATPL230_TXRXBUF_BERSOFT_MAX_RX2 (0xFD5D) |
| #define REG_ATPL230_TXRXBUF_BERSOFT_MAX_RX3 (0xFD5E) |
| #define REG_ATPL230_TXRXBUF_BERSOFT_RX0 (0xFD53) |
| #define REG_ATPL230_TXRXBUF_BERSOFT_RX1 (0xFD54) |
| #define REG_ATPL230_TXRXBUF_BERSOFT_RX2 (0xFD55) |
| #define REG_ATPL230_TXRXBUF_BERSOFT_RX3 (0xFD56) |
| #define REG_ATPL230_TXRXBUF_CDOFFSTA1 (0xFDE2) |
| #define REG_ATPL230_TXRXBUF_CDOFFSTA2 (0xFDE3) |
| #define REG_ATPL230_TXRXBUF_CDOFFSTA3 (0xFDE4) |
| #define REG_ATPL230_TXRXBUF_CDOFFSTA4 (0xFDE5) |
| #define REG_ATPL230_TXRXBUF_CDONSTA1 (0xFDDE) |
| #define REG_ATPL230_TXRXBUF_CDONSTA2 (0xFDDF) |
| #define REG_ATPL230_TXRXBUF_CDONSTA3 (0xFDE0) |
| #define REG_ATPL230_TXRXBUF_CDONSTA4 (0xFDE1) |
| #define REG_ATPL230_TXRXBUF_CHIRP_AMP_TX0 (0xFD28) |
Referenced by phy_tx_frame().
| #define REG_ATPL230_TXRXBUF_CHIRP_AMP_TX1 (0xFD29) |
| #define REG_ATPL230_TXRXBUF_CHIRP_AMP_TX2 (0xFD2A) |
| #define REG_ATPL230_TXRXBUF_CHIRP_AMP_TX3 (0xFD2B) |
| #define REG_ATPL230_TXRXBUF_CINRAVG_RX0 (0xFD7B) |
Referenced by phy_rx_frame_cb().
| #define REG_ATPL230_TXRXBUF_CINRAVG_RX1 (0xFD7C) |
| #define REG_ATPL230_TXRXBUF_CINRAVG_RX2 (0xFD7D) |
| #define REG_ATPL230_TXRXBUF_CINRAVG_RX3 (0xFD7E) |
| #define REG_ATPL230_TXRXBUF_CINRMAX_RX0 (0xFD7F) |
| #define REG_ATPL230_TXRXBUF_CINRMAX_RX1 (0xFD80) |
| #define REG_ATPL230_TXRXBUF_CINRMAX_RX2 (0xFD81) |
| #define REG_ATPL230_TXRXBUF_CINRMAX_RX3 (0xFD82) |
| #define REG_ATPL230_TXRXBUF_CINRMIN_RX0 (0xFD77) |
Referenced by _pal_get_qt(), pal_nl_get(), and phy_rx_frame_cb().
| #define REG_ATPL230_TXRXBUF_CINRMIN_RX1 (0xFD78) |
| #define REG_ATPL230_TXRXBUF_CINRMIN_RX2 (0xFD79) |
| #define REG_ATPL230_TXRXBUF_CINRMIN_RX3 (0xFD7A) |
| #define REG_ATPL230_TXRXBUF_EMIT_GAIN_TX0 (0xFE3C) |
Referenced by phy_tx_frame().
| #define REG_ATPL230_TXRXBUF_EMIT_GAIN_TX1 (0xFE3D) |
| #define REG_ATPL230_TXRXBUF_EMIT_GAIN_TX2 (0xFE3E) |
| #define REG_ATPL230_TXRXBUF_EMIT_GAIN_TX3 (0xFE3F) |
| #define REG_ATPL230_TXRXBUF_EMITIME1_TX0 (0xFD00) |
Referenced by pal_get_tx_result(), and phy_tx_frame().
| #define REG_ATPL230_TXRXBUF_EMITIME1_TX1 (0xFD04) |
| #define REG_ATPL230_TXRXBUF_EMITIME1_TX2 (0xFD08) |
| #define REG_ATPL230_TXRXBUF_EMITIME1_TX3 (0xFD0C) |
| #define REG_ATPL230_TXRXBUF_EMITIME2_TX0 (0xFD01) |
| #define REG_ATPL230_TXRXBUF_EMITIME2_TX1 (0xFD05) |
| #define REG_ATPL230_TXRXBUF_EMITIME2_TX2 (0xFD09) |
| #define REG_ATPL230_TXRXBUF_EMITIME2_TX3 (0xFD0D) |
| #define REG_ATPL230_TXRXBUF_EMITIME3_TX0 (0xFD02) |
| #define REG_ATPL230_TXRXBUF_EMITIME3_TX1 (0xFD06) |
| #define REG_ATPL230_TXRXBUF_EMITIME3_TX2 (0xFD0A) |
| #define REG_ATPL230_TXRXBUF_EMITIME3_TX3 (0xFD0E) |
| #define REG_ATPL230_TXRXBUF_EMITIME4_TX0 (0xFD03) |
| #define REG_ATPL230_TXRXBUF_EMITIME4_TX1 (0xFD07) |
| #define REG_ATPL230_TXRXBUF_EMITIME4_TX2 (0xFD0B) |
| #define REG_ATPL230_TXRXBUF_EMITIME4_TX3 (0xFD0F) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM1_RX0 (0xFDB3) |
Referenced by phy_rx_frame_cb().
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM1_RX1 (0xFDB7) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM1_RX2 (0xFDBB) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM1_RX3 (0xFDBF) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM2_RX0 (0xFDB4) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM2_RX1 (0xFDB8) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM2_RX2 (0xFDBC) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM2_RX3 (0xFDC0) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM3_RX0 (0xFDB5) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM3_RX1 (0xFDB9) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM3_RX2 (0xFDBD) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM3_RX3 (0xFDC1) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM4_RX0 (0xFDB6) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM4_RX1 (0xFDBA) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM4_RX2 (0xFDBE) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADACUM4_RX3 (0xFDC2) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADER1_RX0 (0xFDA3) |
Referenced by phy_rx_frame_cb().
| #define REG_ATPL230_TXRXBUF_EVM_HEADER1_RX1 (0xFDA5) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADER1_RX2 (0xFDA7) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADER1_RX3 (0xFDA9) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADER2_RX0 (0xFDA4) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADER2_RX1 (0xFDA6) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADER2_RX2 (0xFDA8) |
| #define REG_ATPL230_TXRXBUF_EVM_HEADER2_RX3 (0xFDAA) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM1_RX0 (0xFDC3) |
Referenced by phy_rx_frame_cb().
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM1_RX1 (0xFDC7) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM1_RX2 (0xFDCB) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM1_RX3 (0xFDCF) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM2_RX0 (0xFDC4) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM2_RX1 (0xFDC8) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM2_RX2 (0xFDCC) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM2_RX3 (0xFDD0) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM3_RX0 (0xFDC5) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM3_RX1 (0xFDC9) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM3_RX2 (0xFDCD) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM3_RX3 (0xFDD1) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM4_RX0 (0xFDC6) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM4_RX1 (0xFDCA) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM4_RX2 (0xFDCE) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLACUM4_RX3 (0xFDD2) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLOAD1_RX0 (0xFDAB) |
Referenced by phy_rx_frame_cb().
| #define REG_ATPL230_TXRXBUF_EVM_PAYLOAD1_RX1 (0xFDAD) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLOAD1_RX2 (0xFDAF) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLOAD1_RX3 (0xFDB1) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLOAD2_RX0 (0xFDAC) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLOAD2_RX1 (0xFDAE) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLOAD2_RX2 (0xFDB0) |
| #define REG_ATPL230_TXRXBUF_EVM_PAYLOAD2_RX3 (0xFDB2) |
| #define REG_ATPL230_TXRXBUF_GLOBAL_AMP_TX0 (0xFD20) |
Referenced by phy_tx_frame().
| #define REG_ATPL230_TXRXBUF_GLOBAL_AMP_TX1 (0xFD21) |
| #define REG_ATPL230_TXRXBUF_GLOBAL_AMP_TX2 (0xFD22) |
| #define REG_ATPL230_TXRXBUF_GLOBAL_AMP_TX3 (0xFD23) |
| #define REG_ATPL230_TXRXBUF_INITAD1_RX0 (0xFDD6) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_TXRXBUF_INITAD1_RX1 (0xFDD8) |
| #define REG_ATPL230_TXRXBUF_INITAD1_RX2 (0xFDDA) |
| #define REG_ATPL230_TXRXBUF_INITAD1_RX3 (0xFDDC) |
| #define REG_ATPL230_TXRXBUF_INITAD1_TX0 (0xFD40) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_TXRXBUF_INITAD1_TX1 (0xFD42) |
| #define REG_ATPL230_TXRXBUF_INITAD1_TX2 (0xFD44) |
| #define REG_ATPL230_TXRXBUF_INITAD1_TX3 (0xFD46) |
| #define REG_ATPL230_TXRXBUF_INITAD2_RX0 (0xFDD7) |
| #define REG_ATPL230_TXRXBUF_INITAD2_RX1 (0xFDD9) |
| #define REG_ATPL230_TXRXBUF_INITAD2_RX2 (0xFDDB) |
| #define REG_ATPL230_TXRXBUF_INITAD2_RX3 (0xFDDD) |
| #define REG_ATPL230_TXRXBUF_INITAD2_TX0 (0xFD41) |
| #define REG_ATPL230_TXRXBUF_INITAD2_TX1 (0xFD43) |
| #define REG_ATPL230_TXRXBUF_INITAD2_TX2 (0xFD45) |
| #define REG_ATPL230_TXRXBUF_INITAD2_TX3 (0xFD47) |
| #define REG_ATPL230_TXRXBUF_INITREG_ATPL230_NOISE1 (0xFDF8) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_TXRXBUF_INITREG_ATPL230_NOISE2 (0xFDF9) |
| #define REG_ATPL230_TXRXBUF_NOISECONF (0xFDFA) |
Referenced by phy_rx_frame_cb(), and serial_if_api_parser().
| #define REG_ATPL230_TXRXBUF_PEAK_CUT_GAIN_TX0 (0xFE38) |
Referenced by phy_tx_frame().
| #define REG_ATPL230_TXRXBUF_PEAK_CUT_GAIN_TX1 (0xFE39) |
| #define REG_ATPL230_TXRXBUF_PEAK_CUT_GAIN_TX2 (0xFE3A) |
| #define REG_ATPL230_TXRXBUF_PEAK_CUT_GAIN_TX3 (0xFE3B) |
| #define REG_ATPL230_TXRXBUF_RECTIME1_RX0 (0xFD83) |
Referenced by phy_rx_frame_cb(), and sniffer_if_process().
| #define REG_ATPL230_TXRXBUF_RECTIME1_RX1 (0xFD87) |
| #define REG_ATPL230_TXRXBUF_RECTIME1_RX2 (0xFD8B) |
| #define REG_ATPL230_TXRXBUF_RECTIME1_RX3 (0xFD8F) |
| #define REG_ATPL230_TXRXBUF_RECTIME2_RX0 (0xFD84) |
| #define REG_ATPL230_TXRXBUF_RECTIME2_RX1 (0xFD88) |
| #define REG_ATPL230_TXRXBUF_RECTIME2_RX2 (0xFD8C) |
| #define REG_ATPL230_TXRXBUF_RECTIME2_RX3 (0xFD90) |
| #define REG_ATPL230_TXRXBUF_RECTIME3_RX0 (0xFD85) |
| #define REG_ATPL230_TXRXBUF_RECTIME3_RX1 (0xFD89) |
| #define REG_ATPL230_TXRXBUF_RECTIME3_RX2 (0xFD8D) |
| #define REG_ATPL230_TXRXBUF_RECTIME3_RX3 (0xFD91) |
| #define REG_ATPL230_TXRXBUF_RECTIME4_RX0 (0xFD86) |
| #define REG_ATPL230_TXRXBUF_RECTIME4_RX1 (0xFD8A) |
| #define REG_ATPL230_TXRXBUF_RECTIME4_RX2 (0xFD8E) |
| #define REG_ATPL230_TXRXBUF_RECTIME4_RX3 (0xFD92) |
| #define REG_ATPL230_TXRXBUF_RECTIME_NOISE1 (0xFDF4) |
Referenced by serial_if_api_parser().
| #define REG_ATPL230_TXRXBUF_RECTIME_NOISE2 (0xFDF5) |
| #define REG_ATPL230_TXRXBUF_RECTIME_NOISE3 (0xFDF6) |
| #define REG_ATPL230_TXRXBUF_RECTIME_NOISE4 (0xFDF7) |
| #define REG_ATPL230_TXRXBUF_RESULT_TX10 (0xFD50) |
Referenced by phy_tx_frame_result_cb().
| #define REG_ATPL230_TXRXBUF_RESULT_TX32 (0xFD51) |
| #define REG_ATPL230_TXRXBUF_RMSCALC1_TX0 (0xFD48) |
Referenced by pal_get_cfg_ex(), and phy_tx_frame_result_cb().
| #define REG_ATPL230_TXRXBUF_RMSCALC1_TX1 (0xFD4A) |
| #define REG_ATPL230_TXRXBUF_RMSCALC1_TX2 (0xFD4C) |
| #define REG_ATPL230_TXRXBUF_RMSCALC1_TX3 (0xFD4E) |
| #define REG_ATPL230_TXRXBUF_RMSCALC2_TX0 (0xFD49) |
| #define REG_ATPL230_TXRXBUF_RMSCALC2_TX1 (0xFD4B) |
| #define REG_ATPL230_TXRXBUF_RMSCALC2_TX2 (0xFD4D) |
| #define REG_ATPL230_TXRXBUF_RMSCALC2_TX3 (0xFD4F) |
| #define REG_ATPL230_TXRXBUF_RSSIAVG_NOISE (0xFDFD) |
| #define REG_ATPL230_TXRXBUF_RSSIAVG_RX0 (0xFD6F) |
Referenced by pal_nl_get(), and phy_rx_frame_cb().
| #define REG_ATPL230_TXRXBUF_RSSIAVG_RX1 (0xFD70) |
| #define REG_ATPL230_TXRXBUF_RSSIAVG_RX2 (0xFD71) |
| #define REG_ATPL230_TXRXBUF_RSSIAVG_RX3 (0xFD72) |
| #define REG_ATPL230_TXRXBUF_RSSIMAX_NOISE (0xFDFE) |
| #define REG_ATPL230_TXRXBUF_RSSIMAX_RX0 (0xFD73) |
| #define REG_ATPL230_TXRXBUF_RSSIMAX_RX1 (0xFD74) |
| #define REG_ATPL230_TXRXBUF_RSSIMAX_RX2 (0xFD75) |
| #define REG_ATPL230_TXRXBUF_RSSIMAX_RX3 (0xFD76) |
| #define REG_ATPL230_TXRXBUF_RSSIMIN_NOISE (0xFDFC) |
| #define REG_ATPL230_TXRXBUF_RSSIMIN_RX0 (0xFD6B) |
| #define REG_ATPL230_TXRXBUF_RSSIMIN_RX1 (0xFD6C) |
| #define REG_ATPL230_TXRXBUF_RSSIMIN_RX2 (0xFD6D) |
| #define REG_ATPL230_TXRXBUF_RSSIMIN_RX3 (0xFD6E) |
| #define REG_ATPL230_TXRXBUF_RX_INT (0xFDD4) |
Referenced by _init_phy_layer(), _phy_rx_task(), _reset_rx_flag_interrupt(), and phy_handler().
| #define REG_ATPL230_TXRXBUF_RXCONF (0xFDD5) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_TXRXBUF_RXCONF_INFO_ROBO_MODE (0xFDF3) |
Referenced by phy_rx_frame_cb().
| #define REG_ATPL230_TXRXBUF_SELECT_BUFF_RX (0xFDD3) |
Referenced by _init_phy_layer().
| #define REG_ATPL230_TXRXBUF_SIGNAL_AMP_TX0 (0xFD24) |
Referenced by phy_tx_frame().
| #define REG_ATPL230_TXRXBUF_SIGNAL_AMP_TX1 (0xFD25) |
| #define REG_ATPL230_TXRXBUF_SIGNAL_AMP_TX2 (0xFD26) |
| #define REG_ATPL230_TXRXBUF_SIGNAL_AMP_TX3 (0xFD27) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT1_TX0 (0xFD2C) |
Referenced by _init_phy_layer(), and phy_tx_frame().
| #define REG_ATPL230_TXRXBUF_TIMEOUT1_TX1 (0xFD30) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT1_TX2 (0xFD34) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT1_TX3 (0xFD38) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT2_TX0 (0xFD2D) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT2_TX1 (0xFD31) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT2_TX2 (0xFD35) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT2_TX3 (0xFD39) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT3_TX0 (0xFD2E) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT3_TX1 (0xFD32) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT3_TX2 (0xFD36) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT3_TX3 (0xFD3A) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT4_TX0 (0xFD2F) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT4_TX1 (0xFD33) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT4_TX2 (0xFD37) |
| #define REG_ATPL230_TXRXBUF_TIMEOUT4_TX3 (0xFD3B) |
| #define REG_ATPL230_TXRXBUF_TX_INT (0xFD52) |
Referenced by _init_phy_layer(), _phy_rx_task(), _phy_tx_result_task(), and phy_handler().
| #define REG_ATPL230_TXRXBUF_TXCONF_ROBO_CTL (0xFDF2) |
Referenced by phy_tx_frame().
| #define REG_ATPL230_TXRXBUF_TXCONF_SELBRANCH (0xFDFB) |
Referenced by phy_tx_frame().
| #define REG_ATPL230_TXRXBUF_TXCONF_TX0 (0xFD3C) |
| #define REG_ATPL230_TXRXBUF_TXCONF_TX1 (0xFD3D) |
| #define REG_ATPL230_TXRXBUF_TXCONF_TX2 (0xFD3E) |
| #define REG_ATPL230_TXRXBUF_TXCONF_TX3 (0xFD3F) |
| #define REG_ATPL230_TXRXBUF_TXRX_TA1_TX0 (0xFD10) |
Referenced by phy_tx_frame().
| #define REG_ATPL230_TXRXBUF_TXRX_TA1_TX1 (0xFD12) |
| #define REG_ATPL230_TXRXBUF_TXRX_TA1_TX2 (0xFD14) |
| #define REG_ATPL230_TXRXBUF_TXRX_TA1_TX3 (0xFD16) |
| #define REG_ATPL230_TXRXBUF_TXRX_TA2_TX0 (0xFD11) |
| #define REG_ATPL230_TXRXBUF_TXRX_TA2_TX1 (0xFD13) |
| #define REG_ATPL230_TXRXBUF_TXRX_TA2_TX2 (0xFD15) |
| #define REG_ATPL230_TXRXBUF_TXRX_TA2_TX3 (0xFD17) |
| #define REG_ATPL230_TXRXBUF_TXRX_TB1_TX0 (0xFD18) |
Referenced by phy_tx_frame().
| #define REG_ATPL230_TXRXBUF_TXRX_TB1_TX1 (0xFD1A) |
| #define REG_ATPL230_TXRXBUF_TXRX_TB1_TX2 (0xFD1C) |
| #define REG_ATPL230_TXRXBUF_TXRX_TB1_TX3 (0xFD1E) |
| #define REG_ATPL230_TXRXBUF_TXRX_TB2_TX0 (0xFD19) |
| #define REG_ATPL230_TXRXBUF_TXRX_TB2_TX1 (0xFD1B) |
| #define REG_ATPL230_TXRXBUF_TXRX_TB2_TX2 (0xFD1D) |
| #define REG_ATPL230_TXRXBUF_TXRX_TB2_TX3 (0xFD1F) |
| #define REG_ATPL230_TXRXBUF_ZCT1_RX0 (0xFD93) |
Referenced by pal_zct_get().
| #define REG_ATPL230_TXRXBUF_ZCT1_RX1 (0xFD97) |
| #define REG_ATPL230_TXRXBUF_ZCT1_RX2 (0xFD9B) |
| #define REG_ATPL230_TXRXBUF_ZCT1_RX3 (0xFD9F) |
| #define REG_ATPL230_TXRXBUF_ZCT2_RX0 (0xFD94) |
| #define REG_ATPL230_TXRXBUF_ZCT2_RX1 (0xFD98) |
| #define REG_ATPL230_TXRXBUF_ZCT2_RX2 (0xFD9C) |
| #define REG_ATPL230_TXRXBUF_ZCT2_RX3 (0xFDA0) |
| #define REG_ATPL230_TXRXBUF_ZCT3_RX0 (0xFD95) |
| #define REG_ATPL230_TXRXBUF_ZCT3_RX1 (0xFD99) |
| #define REG_ATPL230_TXRXBUF_ZCT3_RX2 (0xFD9D) |
| #define REG_ATPL230_TXRXBUF_ZCT3_RX3 (0xFDA1) |
| #define REG_ATPL230_TXRXBUF_ZCT4_RX0 (0xFD96) |
| #define REG_ATPL230_TXRXBUF_ZCT4_RX1 (0xFD9A) |
| #define REG_ATPL230_TXRXBUF_ZCT4_RX2 (0xFD9E) |
| #define REG_ATPL230_TXRXBUF_ZCT4_RX3 (0xFDA2) |
| #define REG_ATPL230_VCRC_CONF (0xFF16) |
Referenced by _get_crc().
| #define REG_ATPL230_VCRC_CRC_H (0xFF1A) |
| #define REG_ATPL230_VCRC_CRC_L (0xFF1C) |
| #define REG_ATPL230_VCRC_CRC_M (0xFF1B) |
| #define REG_ATPL230_VCRC_CRC_VH (0xFF19) |
Referenced by _get_crc().
| #define REG_ATPL230_VCRC_CTL (0xFF18) |
Referenced by _get_crc().
| #define REG_ATPL230_VCRC_INPUT (0xFF17) |
Referenced by _get_crc().
| #define REG_ATPL230_VCRC_POLY_H (0xFF0F) |
| #define REG_ATPL230_VCRC_POLY_L (0xFF11) |
| #define REG_ATPL230_VCRC_POLY_M (0xFF10) |
| #define REG_ATPL230_VCRC_POLY_VH (0xFF0E) |
Referenced by _get_crc().
| #define REG_ATPL230_VCRC_RST_H (0xFF13) |
| #define REG_ATPL230_VCRC_RST_L (0xFF15) |
| #define REG_ATPL230_VCRC_RST_M (0xFF14) |
| #define REG_ATPL230_VCRC_RST_VH (0xFF12) |
Referenced by _get_crc().
| #define REG_ATPL230_VERSION (0xFEFF) |
| #define REG_ATPL230_VHIGH_TIMER_BEACON_REF (0xFE47) |
Referenced by pal_timer_get(), phy_tx_frame(), and serial_if_api_parser().
| #define SERIAL_IF_ENABLE 0x1 |
Referenced by main(), and phy_reset().
| #define SNIFFER_IF_ENABLE 0x2 |
Referenced by main(), and phy_reset().
| #define TC_PHY_TX_OFFSET_SYM TC0 |
| #define TC_PHY_TX_OFFSET_SYM_CHN 0 |
| #define TC_PHY_TX_OFFSET_SYM_Handler TC0_Handler |
| #define TC_PHY_TX_OFFSET_SYM_IRQn TC0_IRQn |
| #define VCRC16_CONF 0xC1 |
| #define VCRC16_POLYNOM 0x00000107 |
| #define VCRC16_RST 0x00000000 |
| #define VCRC24_CONF 0xC2 |
| #define VCRC24_POLYNOM 0x00010107 |
| #define VCRC24_RST 0x00000000 |
| #define VCRC32_CONF 0xC3 |
| #define VCRC32_POLYNOM 0x04C11DB7 |
| #define VCRC32_RST 0x00000000 |
| #define VCRC8_CONF 0xC0 |
| #define VCRC8_POLYNOM 0x00000007 |
| #define VCRC8_RST 0x00000000 |
| #define VCRC_TYPES_NUMBER 4 |
Referenced by _get_crc().
| #define VLO_STATE 2 |
Very Low Impedance.
Referenced by display_config(), get_impedance_mode(), and phy_tx_frame_result_cb().
| enum VCRCTypes |
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static |
Get CRC value from the buffer content.
| uc_crc_type | CRC type |
| puc_buf | Pointer to Data to calculate CRC |
| us_len | Data length |
| uc_header_type | Header Type |
| crc | value |
References CRC_TYPE_16, CRC_TYPE_24, CRC_TYPE_32, CRC_TYPE_8, PHY_HT_GENERIC, pplc_if_and8(), pplc_if_or8(), pplc_if_read32(), pplc_if_write32(), pplc_if_write8(), pplc_if_write_rep(), REG_ATPL230_VCRC_CONF, REG_ATPL230_VCRC_CRC_VH, REG_ATPL230_VCRC_CTL, REG_ATPL230_VCRC_INPUT, REG_ATPL230_VCRC_POLY_VH, REG_ATPL230_VCRC_RST_VH, and VCRC_TYPES_NUMBER.
Referenced by _upd_sna_crc().
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Filter IIR initialization.
References _store_filter_sec(), LENGTH_DATA_CHIRP, NUM_ROWS_DATA_CHIRP, NUM_ROWS_DATA_FILTER_IIR, pplc_if_and8(), pplc_if_write8(), REG_ATPL230_IIR_CONFIG, REG_ATPL230_LOAD_ADDRH, and REG_ATPL230_LOAD_CTL.
Referenced by _init_phy_layer().
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PHY init layer.
| uc_rst_type | 0: Complete initialization; 1: No init internal vars neither internal filters |
References _init_IIR_filter(), _update_channel(), _update_emit1_mode(), _update_emit2_mode(), _update_txrx1_polarity(), _update_txrx2_polarity(), atpl230Cfg_t::agc0KrssiOffset, atpl230Cfg_t::agc1KrssiOffset, atpl230Cfg_t::agc2KrssiOffset, atpl230Cfg_t::agc3KrssiOffset, ATPL230_SYS_CONFIG_RST_Msk, ATPL230_SYS_CONFIG_STOP_ENRAM_Msk, ATPL230_VALID_CFG_KEY, ATPL230_VERSION_NUM, Disable_global_interrupt, atpl230Cfg_t::driver1Mode, atpl230Cfg_t::driver2Mode, Enable_global_interrupt, MAX_LEN_D8PSK, MAX_LEN_D8PSK_VTB, MAX_LEN_DBPSK, MAX_LEN_DBPSK_VTB, MAX_LEN_DQPSK, MAX_LEN_DQPSK_VTB, phy_clear_global_interrupt(), phy_get_mac_en(), phy_init_cfg(), phy_init_channel_cfg(), phy_init_coupling_cfg(), phy_mac_crc_disable(), phy_mac_crc_enable(), PHY_MAX_PPDU_SIZE, PHY_NUM_RX_BUFFERS, PHY_NUM_TX_BUFFERS, PHY_RESET_HARD_TYPE, PHY_TX_TIMEOUT_IMMEDIATE_10US, pplc_if_and8(), pplc_if_or8(), pplc_if_read_buf(), pplc_if_write16(), pplc_if_write32(), pplc_if_write8(), pplc_if_write_buf(), atpl230_t::prodId, REG_ATPL230_AGC0_KRSSI, REG_ATPL230_AGC1_KRSSI, REG_ATPL230_AGC2_KRSSI, REG_ATPL230_AGC3_KRSSI, REG_ATPL230_AGC_CTL_AUX, REG_ATPL230_AGC_THRESHOLD_HIGH, REG_ATPL230_CD_CONTROL, REG_ATPL230_CRC32_MAC_HIGH, REG_ATPL230_CRC8_MAC_HD_HIGH, REG_ATPL230_CRC8_MAC_HIGH, REG_ATPL230_CRC8_PHY_HIGH, REG_ATPL230_EQUALIZE_H, REG_ATPL230_EQUALIZE_L, REG_ATPL230_FACTOR_COMP_DOWN, REG_ATPL230_FACTOR_COMP_DOWN_ROBO, REG_ATPL230_FACTOR_COMP_UP, REG_ATPL230_FACTOR_COMP_UP_ROBO, REG_ATPL230_FACTOR_ROBUST_3_2, REG_ATPL230_FACTOR_THR_CTL, REG_ATPL230_FACTOR_THRESHOLD_2_3_AND_1_3, REG_ATPL230_FACTOR_THRESHOLD_3_AND_2, REG_ATPL230_FACTOR_THRESHOLD_4_AND_1, REG_ATPL230_FILTER_MIN_HIGH, REG_ATPL230_FILTER_MIN_MED, REG_ATPL230_FT_CORR_MIN, REG_ATPL230_FT_CORR_MIN_ROBO, REG_ATPL230_FT_MAX_FACTOR_TH, REG_ATPL230_FT_MAX_FACTOR_TH_ROBO, REG_ATPL230_FT_MIN_FACTOR_TH, REG_ATPL230_FT_MIN_FACTOR_TH_ROBO, REG_ATPL230_FT_STEP_DOWN, REG_ATPL230_FT_STEP_DOWN_ROBO, REG_ATPL230_FT_STEP_UP, REG_ATPL230_FT_STEP_UP_FD, REG_ATPL230_FT_STEP_UP_FD_ROBO, REG_ATPL230_FT_STEP_UP_ROBO, REG_ATPL230_FT_SUMADOR_CONF, REG_ATPL230_FT_TIME_DOWN, REG_ATPL230_FT_TIME_DOWN_ROBO, REG_ATPL230_FT_TIME_UP, REG_ATPL230_FT_TIME_UP_ROBO, REG_ATPL230_IIR_CONFIG, REG_ATPL230_INI_CHIRP1, REG_ATPL230_INI_CHIRP2, REG_ATPL230_LOAD_CTL, REG_ATPL230_MAX_LEN_D8PSK, REG_ATPL230_MAX_LEN_D8PSK_VTB, REG_ATPL230_MAX_LEN_DBPSK, REG_ATPL230_MAX_LEN_DBPSK_VTB, REG_ATPL230_MAX_LEN_DQPSK, REG_ATPL230_MAX_LEN_DQPSK_VTB, REG_ATPL230_MIN_M_TH_HIGH, REG_ATPL230_MIN_R_TH, REG_ATPL230_MODE_CONJ, REG_ATPL230_N_CHIRP, REG_ATPL230_N_MOD, REG_ATPL230_N_RAMPH, REG_ATPL230_PHY_CONFIG, REG_ATPL230_PHY_NOISE_INIT_ADDRESS, REG_ATPL230_PHY_RX_INIT_ADDRESS, REG_ATPL230_PHY_TX_INIT_ADDRESS, REG_ATPL230_POSITIVE_FAIL_CONFIG, REG_ATPL230_POSITIVE_FAIL_HIGH, REG_ATPL230_R_MARGIN, REG_ATPL230_RSSI_OFFSET, REG_ATPL230_RX_TIME_OFFSET, REG_ATPL230_SNA0, REG_ATPL230_SOFT_STOP_TIMEH, REG_ATPL230_SOFT_TIME_X1_H, REG_ATPL230_SOFT_TIME_X2_H, REG_ATPL230_SOFT_TIME_Y1, REG_ATPL230_SOFT_TIME_Y2, REG_ATPL230_STEP_M_DOWN, REG_ATPL230_STEP_M_UP, REG_ATPL230_STEP_R_DOWN, REG_ATPL230_STEP_R_UP, REG_ATPL230_SYS_CONFIG, REG_ATPL230_TXRXBUF_INITAD1_RX0, REG_ATPL230_TXRXBUF_INITAD1_TX0, REG_ATPL230_TXRXBUF_INITREG_ATPL230_NOISE1, REG_ATPL230_TXRXBUF_RX_INT, REG_ATPL230_TXRXBUF_RXCONF, REG_ATPL230_TXRXBUF_SELECT_BUFF_RX, REG_ATPL230_TXRXBUF_TIMEOUT1_TX0, REG_ATPL230_TXRXBUF_TX_INT, atpl230Cfg_t::rxCorrThreshold, atpl230_t::rxIdBuff, atpl230_t::rxQRMode, atpl230_t::txIdBuff, atpl230_t::txQRMode, atpl230Cfg_t::txrx1Polarity, atpl230Cfg_t::txrx2Polarity, atpl230Cfg_t::txrxChannel, and atpl230_t::version.
Referenced by phy_reset(), and phy_tx_frame_result_cb().
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Task to process RX PLC.
References ATPL230_GET_RXINT_HRX0, ATPL230_GET_RXINT_PRX0, ATPL230_TXRXBUF_RX_INT_HRX0_Msk, ATPL230_TXRXBUF_TX_INT_N_Msk, pplc_if_and8(), REG_ATPL230_TXRXBUF_RX_INT, and REG_ATPL230_TXRXBUF_TX_INT.
Referenced by phy_handler().
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Task to process TX PLC.
References ATPL230_GET_TXINT_TX0, ATPL230_TXRXBUF_TX_INT_TX0_Msk, phy_carrier_detect_buff_enable(), phy_reception_buff_enable(), pplc_if_and8(), REG_ATPL230_TXRXBUF_TX_INT, and uc_reg_tx_int.
Referenced by phy_handler().
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Reset reception interrupt.
| uc_buf_idx | Buffer index |
References ATPL230_TXRXBUF_RX_INT_PRX0_Msk, pplc_if_and8(), and REG_ATPL230_TXRXBUF_RX_INT.
Referenced by phy_rx_frame_cb().
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static |
Store Filter secuence.
| puc_fir_data | Pointer to filter table data (start pointer) |
| uc_cmd | Internal Memory CMD |
| uc_num_rows | Number of rows in the filter table |
| uc_way_mode | Mode to read filter table [0: normal mode, 1: inverse mode] |
| uc_start_mem_byte | Byte to start write operation in internal memory |
| uc_inv_mode | Select inverse data mode |
References pplc_if_write_buf(), REG_ATPL230_LOAD_ADDRL, and us_value.
Referenced by _init_IIR_filter().
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static |
Update CRC of SNA.
Used as initial CRC value in case of generic header type
| puc_sna | Pointer to SNA |
References _get_crc(), CRC_TYPE_16, CRC_TYPE_24, CRC_TYPE_32, and CRC_TYPE_8.
Referenced by phy_set_cfg_param().
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static |
Update channel in atpl230 device.
Update attenuation values depending on channel to use.
| uc_channel | Communication Channel [1..8] |
References pplc_if_write32(), pplc_if_write8(), REG_ATPL230_EMITTER_FREC, REG_ATPL230_PASO_FASE_CORDIC_TX_VH, atpl230ChnCfg_t::tx1AttChirpHighZ, atpl230ChnCfg_t::tx1AttChirpLowZ, atpl230ChnCfg_t::tx1AttChirpVLowZ, atpl230ChnCfg_t::tx1AttSignalHighZ, atpl230ChnCfg_t::tx1AttSignalLowZ, atpl230ChnCfg_t::tx1AttSignalVLowZ, atpl230ChnCfg_t::tx1LoadThreshold1, atpl230ChnCfg_t::tx1LoadThreshold2, atpl230ChnCfg_t::tx1LoadThreshold3, atpl230ChnCfg_t::tx1LoadThreshold4, and atpl230Cfg_t::txrxChannel.
Referenced by _init_phy_layer(), and phy_set_cfg_param().
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Update emit 1 mode in atpl230 device.
Update Emit mode register configuration.
| uc_emode | Emit Mode [INTERNAL DRIVER, EXTERNAL DRIVER] |
References atpl230Cfg_t::emit1Active, atpl230Cfg_t::emit2Active, EXTERNAL_DRV_MODE, atpl230Cfg_t::n1Delay, atpl230Cfg_t::p1Delay, pplc_if_and8(), pplc_if_or8(), pplc_if_write8(), REG_ATPL230_EMIT1_ACTIVE, REG_ATPL230_EMIT2_ACTIVE, REG_ATPL230_EMIT_CONFIG, REG_ATPL230_N1_DELAY, and REG_ATPL230_P1_DELAY.
Referenced by _init_phy_layer(), and phy_set_cfg_param().
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Update emit 2 mode in atpl230 device.
Update Emit mode register configuration.
| uc_emode | Emit Mode [INTERNAL DRIVER, EXTERNAL DRIVER] |
References atpl230Cfg_t::emit3Active, atpl230Cfg_t::emit4Active, EXTERNAL_DRV_MODE, atpl230Cfg_t::n2Delay, atpl230Cfg_t::p2Delay, pplc_if_and8(), pplc_if_or8(), pplc_if_write8(), REG_ATPL230_EMIT3_ACTIVE, REG_ATPL230_EMIT4_ACTIVE, REG_ATPL230_EMIT_CONFIG, REG_ATPL230_N2_DELAY, and REG_ATPL230_P2_DELAY.
Referenced by _init_phy_layer(), and phy_set_cfg_param().
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Update polarity of TXRX 1 in atpl230 device.
Update Polarity register configuration.
| uc_pol | Polarity Mode [DRV_POL_TX_0_RX_1, DRV_POL_TX_1_RX_0] |
References pplc_if_and8(), pplc_if_or8(), and REG_ATPL230_AFE_CTL.
Referenced by _init_phy_layer(), and phy_set_cfg_param().
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static |
Update polarity of TXRX 2 in atpl230 device.
Update Polarity register configuration.
| uc_pol | Polarity Mode [DRV_POL_TX_0_RX_1, DRV_POL_TX_1_RX_0] |
References pplc_if_and8(), pplc_if_or8(), and REG_ATPL230_AFE_CTL.
Referenced by _init_phy_layer().
| void Dummy_serial_if_init | ( | void | ) |
Dummy Phy Tester Tool Serialization Addon.
| void Dummy_sniffer_if_init | ( | uint8_t | uc_enable_led | ) |
Dummy Phy Sniffer Serialization Addon.
References UNUSED.
|
inlinestatic |
Disable carrier detect in specific buffer.
References ATPL230_TXRXBUF_TXCONF_DC_Msk, pplc_if_or8(), and REG_ATPL230_TXRXBUF_TXCONF_TX0.
Referenced by phy_tx_frame().
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inlinestatic |
Enable carrier detect in specific buffer.
References ATPL230_TXRXBUF_TXCONF_DC_Msk, pplc_if_and8(), and REG_ATPL230_TXRXBUF_TXCONF_TX0.
Referenced by _phy_tx_result_task().
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inlinestatic |
Disable Carrier Detect.
References ATPL230_SFR_CD_Msk, pplc_if_and8(), and REG_ATPL230_PHY_SFR.
|
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Enable Carrier Detect.
References ATPL230_SFR_CD_Msk, pplc_if_or8(), and REG_ATPL230_PHY_SFR.
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Clear global interruption.
References ATPL230_SFR_PHY_INT_Msk, pplc_if_or8(), and REG_ATPL230_PHY_SFR.
Referenced by _init_phy_layer(), and phy_handler().
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Clear PHY SFR -1.
References ATPL230_SFR_ERR_PYL_Msk, pplc_if_and8(), and REG_ATPL230_PHY_SFR.
Referenced by phy_handler().
| uint8_t phy_cmd_cfg_param | ( | uint16_t | us_id, |
| uint8_t | uc_cmd, | ||
| uint8_t | uc_mask | ||
| ) |
Set PHY layer parameter.
| us_id | Parameter Identification (see atpl230.h) |
| uc_cmd | Command to operation (PHY_CMD_CFG_AND, PHY_CMD_CFG_OR, PHY_CMD_CFG_XOR) |
| uc_mask | Mask Bits |
References ATPL230_REG_PARAM, PHY_CFG_INVALID_INPUT, PHY_CFG_SUCCESS, PHY_CMD_CFG_AND, PHY_CMD_CFG_OR, PHY_CMD_CFG_XOR, pplc_if_and8(), pplc_if_or8(), and pplc_if_xor8().
Referenced by pal_cmd_cfg_ex(), and serial_if_api_parser().
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Disable forced transmission in specific buffer.
References ATPL230_TXRXBUF_TXCONF_FE_Msk, pplc_if_and8(), and REG_ATPL230_TXRXBUF_TXCONF_TX0.
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Enable forced transmission in specific buffer.
References ATPL230_TXRXBUF_TXCONF_FE_Msk, pplc_if_or8(), and REG_ATPL230_TXRXBUF_TXCONF_TX0.
Referenced by phy_tx_frame().
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Get Carrier Detect.
References ATPL230_SFR_CD_Msk, pplc_if_read8(), and REG_ATPL230_PHY_SFR.
| uint8_t phy_get_cfg_param | ( | uint16_t | us_id, |
| void * | p_val, | ||
| uint16_t | uc_len | ||
| ) |
Get PHY layer parameter.
| us_id | Parameter Identification (see atpl230.h) |
| *p_val | Pointer to parameter value |
| uc_len | Length of the parameter |
References ATPL230_ATT_PARAM, ATPL230_ATT_PARAM_MSK, ATPL230_CFG_PARAM, ATPL230_CFG_PARAM_MSK, ATPL230_PARAM, ATPL230_PARAM_MSK, ATPL230_REG_PARAM, NULL, PHY_CFG_INVALID_INPUT, PHY_CFG_SUCCESS, pplc_if_read16(), pplc_if_read32(), pplc_if_read8(), and pplc_if_read_buf().
Referenced by _pal_get_qt(), _serial_if_get_rx_task(), _serial_if_get_tx_result_task(), main(), pal_cd_get(), pal_get_cfg_ex(), pal_get_tx_result(), pal_nl_get(), pal_timer_get(), pal_zct_get(), prvAppPhyTask(), serial_if_api_parser(), and sniffer_if_process().
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Get MAC coproc.
References ATPL230_MAC_EN_Msk, pplc_if_read8(), and REG_ATPL230_PHY_CONFIG.
Referenced by _init_phy_layer(), pal_get_cfg_ex(), phy_rx_frame_cb(), phy_tx_frame(), and sniffer_if_process().
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Get PHY SFR -1 flag.
References ATPL230_SFR_ERR_PYL_Msk, pplc_if_read8(), and REG_ATPL230_PHY_SFR.
Referenced by phy_handler().
| void phy_handler | ( | void | ) |
PHY interrupt management.
References _phy_rx_task(), _phy_tx_result_task(), phy_clear_global_interrupt(), phy_clear_sfr_err(), phy_get_sfr_err(), pplc_if_and8(), pplc_if_read8(), REG_ATPL230_TXRXBUF_RX_INT, REG_ATPL230_TXRXBUF_TX_INT, and uc_reg_rx_int.
Referenced by phy_init().
| void phy_init | ( | uint8_t | uc_ifaceEnable | ) |
Create PHY tasks, queues and semaphores Initialize physical parameters and configure ATPL230 device.
References phy_handler(), phy_reset(), PHY_RESET_HARD_TYPE, pplc_if_init(), and pplc_set_handler().
Referenced by _prime_stack_process(), and main().
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Disable MAC CRC processing.
References ATPL230_MAC_EN_Msk, pplc_if_and8(), and REG_ATPL230_PHY_CONFIG.
Referenced by _init_phy_layer(), pal_init(), pal_set_cfg_ex(), prvAppPhyTask(), serial_if_init(), serial_if_sniffer_api_parser(), sniffer_if_init(), and vPhyEmbeddedAppTask().
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Enable MAC CRC processing.
References ATPL230_MAC_EN_Msk, pplc_if_or8(), and REG_ATPL230_PHY_CONFIG.
Referenced by _init_phy_layer(), pal_set_cfg_ex(), and serial_if_sniffer_api_parser().
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Disable reception in specific buffer.
References ATPL230_TXRXBUF_TXCONF_DR_Msk, pplc_if_or8(), and REG_ATPL230_TXRXBUF_TXCONF_TX0.
Referenced by phy_tx_frame().
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Enable reception in specific buffer.
References ATPL230_TXRXBUF_TXCONF_DR_Msk, pplc_if_and8(), and REG_ATPL230_TXRXBUF_TXCONF_TX0.
Referenced by _phy_tx_result_task().
| void phy_reset | ( | uint8_t | uc_reset_type | ) |
Reset PHY layer including pplc service and serial ifaces Initialize physical parameters and configure ATPL230 device.
References _init_phy_layer(), SERIAL_IF_ENABLE, serial_if_init(), SNIFFER_IF_ENABLE, and sniffer_if_init().
Referenced by pal_set_cfg_ex(), phy_init(), prvAppPhyTask(), and serial_if_api_parser().
| void phy_rx_frame_cb | ( | xPhyMsgRx_t * | px_msg | ) |
Read the received data with ATPL230 device.
| px_msg | Pointer to message structure data. |
References _reset_rx_flag_interrupt(), ATPL230_GET_HEADER_TYPE, ATPL230_GET_NOISE_NS, ATPL230_GET_NOISE_RESULT, ATPL230_GET_ROBO_MODE_RX, xPhyMsgRx_t::cinr_avg, xPhyMsgRx_t::data_buf, xPhyMsgRx_t::data_len, xPhyMsgRx_t::evm_header, xPhyMsgRx_t::evm_header_acum, xPhyMsgRx_t::evm_payload, xPhyMsgRx_t::evm_payload_acum, xPhyMsgRx_t::header_type, MAC_GEN_HEADER_SIZE, MAC_HEADER_SIZE, xPhyMsgRx_t::mode, MODE_NOISE, MODE_TEST, MODE_TYPE_A, MODE_TYPE_B, MODE_TYPE_BC, xPhyMsgRx_t::noise_result, PHY_DMA_OFFSET, phy_get_mac_en(), PHY_HT_BEACON, PHY_MAX_PPDU_SIZE, PHY_NUM_RX_BUFFERS, pplc_if_read16(), pplc_if_read32(), pplc_if_read8(), pplc_if_read_buf(), REG_ATPL230_PHY_NOISE_INIT_ADDRESS, REG_ATPL230_PHY_RX_INIT_ADDRESS, REG_ATPL230_TXRXBUF_CINRAVG_RX0, REG_ATPL230_TXRXBUF_CINRMIN_RX0, REG_ATPL230_TXRXBUF_EVM_HEADACUM1_RX0, REG_ATPL230_TXRXBUF_EVM_HEADER1_RX0, REG_ATPL230_TXRXBUF_EVM_PAYLACUM1_RX0, REG_ATPL230_TXRXBUF_EVM_PAYLOAD1_RX0, REG_ATPL230_TXRXBUF_NOISECONF, REG_ATPL230_TXRXBUF_RECTIME1_RX0, REG_ATPL230_TXRXBUF_RSSIAVG_RX0, REG_ATPL230_TXRXBUF_RXCONF_INFO_ROBO_MODE, xPhyMsgRx_t::rssi_avg, xPhyMsgRx_t::rx_time, atpl230_t::rxBadLen, atpl230_t::rxHdrRcv, atpl230_t::rxIdBuff, atpl230_t::rxMode, atpl230_t::rxPayloadLen, atpl230_t::rxPayloadLenSym, atpl230_t::rxQRMode, atpl230_t::rxScheme, atpl230_t::rxTotal, atpl230_t::rxTotalBytes, atpl230_t::rxTotalErrors, xPhyMsgRx_t::scheme, xPhyMsgRx_t::uc_buff_id, and uc_last_rx_buf.
Referenced by _serial_if_get_rx_task(), pal_get_rx(), prvGetRxTask(), and sniffer_if_process().
| uint8_t phy_set_cfg_param | ( | uint16_t | us_id, |
| void * | p_val, | ||
| uint16_t | uc_len | ||
| ) |
Set PHY layer parameter.
| us_id | Parameter Identification (see atpl230.h) |
| *p_val | Pointer to parameter value |
| uc_len | Length of the parameter |
References _upd_sna_crc(), _update_channel(), _update_emit1_mode(), _update_emit2_mode(), _update_txrx1_polarity(), ATPL230_ATT_PARAM, ATPL230_ATT_PARAM_MSK, ATPL230_CFG_PARAM, ATPL230_CFG_PARAM_MSK, ATPL230_PARAM, ATPL230_PARAM_MSK, ATPL230_REG_PARAM, atpl230Cfg_t::atplCoupling, NULL, PHY_CFG_INVALID_CHANNEL, PHY_CFG_INVALID_INPUT, PHY_CFG_SUCCESS, PHY_ID_CFG_COUPLING_BOARD, PHY_ID_CFG_DRIVER1_MODE, PHY_ID_CFG_DRIVER2_MODE, PHY_ID_CFG_TXRX1_POLARITY, PHY_ID_CFG_TXRX2_POLARITY, PHY_ID_CFG_TXRX_CHANNEL, phy_init_channel_cfg(), phy_init_coupling_cfg(), pplc_if_write16(), pplc_if_write32(), pplc_if_write8(), pplc_if_write_buf(), REG_ATPL230_SNA0, and atpl230Cfg_t::txrxChannel.
Referenced by pal_init(), pal_set_cfg_ex(), prvAppPhyTask(), serial_if_api_parser(), serial_if_init(), serial_if_sniffer_api_parser(), sniffer_if_init(), sniffer_if_process(), and vPhyEmbeddedAppTask().
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Disable transmission in specific buffer.
References ATPL230_TXRXBUF_TXCONF_EB_Msk, pplc_if_and8(), and REG_ATPL230_TXRXBUF_TXCONF_TX0.
Referenced by pal_set_cfg_ex().
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Get status of specific buffer.
| true | if buffer is enabled |
| false | if buffer is disabled |
References ATPL230_TXRXBUF_TXCONF_EB_Msk, ATPL230_TXRXBUF_TXCONF_EB_Pos, pplc_if_read8(), and REG_ATPL230_TXRXBUF_TXCONF_TX0.
Referenced by phy_tx_frame().
| uint8_t phy_tx_frame | ( | xPhyMsgTx_t * | px_msg | ) |
Write the transmitted data with ATPL230 device.
| px_msg | Pointer to message structure data. |
| PHY_TX_RESULT_PROCESS | on success. |
| PHY_TX_RESULT_INV_LENGTH | on invalid length error. |
| PHY_TX_RESULT_BUSY_CH | on busy channel error. |
| PHY_TX_RESULT_BUSY_TX | on busy transmission error. |
| PHY_TX_RESULT_INV_SCHEME | on invalid scheme error. |
| PHY_TX_RESULT_TIMEOUT | on timeout error. |
References ATPL230_FFT_MODE_CONT_Msk, ATPL230_FFT_MODE_EN_Msk, ATPL230_GET_HEADER_TYPE, ATPL230_TXRXBUF_TXCONF_BF_Msk, ATPL230_TXRXBUF_TXCONF_BR1, ATPL230_TXRXBUF_TXCONF_BR2, ATPL230_TXRXBUF_TXCONF_BR_Msk, ATPL230_TXRXBUF_TXCONF_EB_Msk, ATPL230_TXRXBUF_TXCONF_PCO_Msk, xPhyMsgTx_t::att_level, xPhyMsgTx_t::data_buf, xPhyMsgTx_t::data_len, xPhyMsgTx_t::disable_rx, atpl230Cfg_t::driver1Mode, atpl230Cfg_t::driver2Mode, DRIVER_1, DRIVER_2, EXTERNAL_DRV_MODE, HI_STATE, atpl230Cfg_t::high_Z_driver, atpl230Cfg_t::impedance, LO_STATE, LO_STATE_PK, atpl230Cfg_t::low_Z_driver, MAC_GEN_HEADER_SIZE, MAC_HEADER_SIZE, xPhyMsgTx_t::mode, MODE_TEST, MODE_TYPE_A, MODE_TYPE_B, MODE_TYPE_BC, phy_carrier_detect_buff_disable(), PHY_DMA_OFFSET, phy_force_tx_buff_enable(), phy_get_mac_en(), PHY_MAX_PPDU_SIZE, PHY_NUM_TX_BUFFERS, phy_reception_buff_disable(), phy_transmission_buff_is_enable(), PHY_TX_MIN_DELAY, PHY_TX_RESULT_INV_BUFFER, PHY_TX_RESULT_INV_LENGTH, PHY_TX_RESULT_INV_PRIME_MODE, PHY_TX_RESULT_INV_SCHEME, PHY_TX_RESULT_PROCESS, PHY_TX_SCHEDULING_MODE_RELATIVE, pplc_if_and8(), pplc_if_or8(), pplc_if_read32(), pplc_if_write16(), pplc_if_write32(), pplc_if_write8(), pplc_if_write_buf(), PROTOCOL_D8PSK, PROTOCOL_D8PSK_VTB, PROTOCOL_DBPSK, PROTOCOL_DBPSK_ROBO, PROTOCOL_DBPSK_VTB, PROTOCOL_DQPSK, PROTOCOL_DQPSK_ROBO, PROTOCOL_DQPSK_VTB, REG_ATPL230_FFT_MODE, REG_ATPL230_PHY_TX_INIT_ADDRESS, REG_ATPL230_SOFT_STOP_TIMEH, REG_ATPL230_SOFT_TIME_X1_H, REG_ATPL230_SOFT_TIME_X2_H, REG_ATPL230_SOFT_TIME_Y1, REG_ATPL230_SOFT_TIME_Y2, REG_ATPL230_TXRXBUF_CHIRP_AMP_TX0, REG_ATPL230_TXRXBUF_EMIT_GAIN_TX0, REG_ATPL230_TXRXBUF_EMITIME1_TX0, REG_ATPL230_TXRXBUF_GLOBAL_AMP_TX0, REG_ATPL230_TXRXBUF_PEAK_CUT_GAIN_TX0, REG_ATPL230_TXRXBUF_SIGNAL_AMP_TX0, REG_ATPL230_TXRXBUF_TIMEOUT1_TX0, REG_ATPL230_TXRXBUF_TXCONF_ROBO_CTL, REG_ATPL230_TXRXBUF_TXCONF_SELBRANCH, REG_ATPL230_TXRXBUF_TXCONF_TX0, REG_ATPL230_TXRXBUF_TXRX_TA1_TX0, REG_ATPL230_TXRXBUF_TXRX_TB1_TX0, REG_ATPL230_VHIGH_TIMER_BEACON_REF, xPhyMsgTx_t::scheme, xPhyMsgTx_t::tdelay, atpl230Cfg_t::timeAfterTxHighZ, atpl230Cfg_t::timeAfterTxLowZ, atpl230Cfg_t::timeBeforeTxHighZ, atpl230Cfg_t::timeBeforeTxLowZ, xPhyMsgTx_t::tmode, atpl230ChnCfg_t::txAttGlobal, atpl230_t::txBadBusyTx, atpl230_t::txBadFormat, atpl230_t::txBadLen, atpl230_t::txDisableRx, atpl230_t::txIdBuff, atpl230_t::txLevel, atpl230_t::txMode, atpl230_t::txPayloadLenSym, atpl230Cfg_t::txrxChannel, atpl230_t::txScheme, atpl230_t::txTdelay, xPhyMsgTx_t::uc_buff_id, and atpl230Cfg_t::vlow_Z_driver.
Referenced by pal_data_request_ex(), prvAppPhyTask(), and serial_if_api_parser().
| void phy_tx_frame_result_cb | ( | xPhyMsgTxResult_t * | px_tx_result | ) |
Task to process TX PLC.
References _init_phy_layer(), ATPL230_GET_TX_RESULT_TX0, ATPL230_GET_TX_RESULT_TX1, ATPL230_GET_TX_RESULT_TX2, ATPL230_GET_TX_RESULT_TX3, ATPL230_SFR_BCH_ERR_Msk, ATPL230_TXRXBUF_RESULT_BUSY_CHANNEL, ATPL230_TXRXBUF_RESULT_INPROCESS, ATPL230_TXRXBUF_RESULT_INVALID_SCHEME, ATPL230_TXRXBUF_RESULT_PREV_TX_INPROCESS, ATPL230_TXRXBUF_RESULT_RX_INPROCESS, ATPL230_TXRXBUF_RESULT_SUCCESSFUL, ATPL230_TXRXBUF_RESULT_TIMEOUT, ATPL230_TXRXBUF_RESULT_WRONG_LEN, atpl230Cfg_t::autoDetectBranch, atpl230Cfg_t::enable_vlow_pk, HI_STATE, atpl230Cfg_t::impedance, LO_STATE, LO_STATE_PK, PHY_NUM_TX_BUFFERS, PHY_RESET_SOFT_TYPE, pplc_if_or8(), pplc_if_read16(), REG_ATPL230_PHY_SFR, REG_ATPL230_TXRXBUF_RESULT_TX10, REG_ATPL230_TXRXBUF_RMSCALC1_TX0, xPhyMsgTxResult_t::rms_calc, atpl230_t::txBadBusyChannel, atpl230_t::txBadBusyTx, atpl230_t::txBadFormat, atpl230_t::txBadLen, atpl230_t::txQRMode, atpl230_t::txTimeout, atpl230_t::txTotal, atpl230_t::txTotalBytes, atpl230_t::txTotalErrors, xPhyMsgTxResult_t::uc_id_buffer, uc_last_tx_buf, xPhyMsgTxResult_t::uc_result, and VLO_STATE.
Referenced by _serial_if_get_tx_result_task(), pal_get_tx_result(), and prvGetTxResultTask().
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| atpl230Cfg_t atpl230Cfg |
Referenced by main(), phy_init_cfg(), phy_init_channel_cfg(), and phy_init_coupling_cfg().
| atpl230ChnCfg_t atpl230ChnCfg |
| const float f_escalado_a22 |
| const float f_escalado_a23 |
| const float f_escalado_b22 |
| const float f_escalado_b23 |
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| const uint8_t uc_data_angle_real_imag_comp[LENGTH_DATA_ANGLE_REAL_IMAG_COMP] |
| uint8_t uc_data_angle_real_imag_comp[LENGTH_DATA_ANGLE_REAL_IMAG_COMP] |
| const uint8_t uc_data_chirp[LENGTH_DATA_CHIRP] |
| uint8_t uc_data_chirp[LENGTH_DATA_CHIRP] |
| const uint8_t uc_data_filter_IIR[LENGTH_DATA_FILTER_IIR] |
| uint8_t uc_data_filter_IIR[LENGTH_DATA_FILTER_IIR] |
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Referenced by phy_rx_frame_cb().
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Referenced by phy_tx_frame_result_cb().
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Referenced by phy_handler().
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Referenced by _phy_tx_result_task().
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| uint32_t ul_data_offset_correction[NUM_ROWS_DATA_OFFSET_CORRECTION] |
| const uint32_t ul_data_offset_correction[NUM_ROWS_DATA_OFFSET_CORRECTION] |
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1.8.5