Microchip® Advanced Software Framework

Data Structures | Macros | Typedefs | Enumerations | Functions | Variables
lorawan_multiband.h File Reference

LORAWAN Regional multiband common inlcude file.

Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.

#include "lorawan.h"
#include "radio_interface.h"
#include "lorawan_reg_params.h"
#include "conf_regparams.h"
#include "pds_interface.h"

Data Structures

struct  _channelParams
 
union  _CmnParams
 
struct  _DRParams
 Regional parameters which are controlled by Data Rate. More...
 
struct  _DutyCycleTimer
 
struct  _JoinBackoffTimer
 
struct  _JoinDutyCycleTimer
 
struct  _LBTTimer
 
struct  _OthChannelParams
 
struct  _RegParams
 
struct  _RegParamsType1
 
struct  _RegParamsType2
 
struct  _RegPdsItems
 
struct  _SubBandParams
 

Macros

#define Adv_LC0_433   {433175000, 433175000, DEFAULT_CH_BAND , 1, 12, 0xFF}
 
#define ADV_LC0_865_IN   {865062500, 865062500, 0, 1, DEFAULT_EIRP_IN, 0xFF}
 
#define Adv_LC0_868   {868100000, 868100000, DEFAULT_CH_BAND , 1, 16,0xFF}
 
#define ADV_LC0_920_KR   {922100000,922100000, 0, 1, 14, 0xFF}
 
#define ADV_LC0_923   {923200000,923200000, 0, 1, 16, 0xFF}
 
#define ADV_LC0_923_JP   {923200000,923200000, DEFAULT_CH_SUBBAND_JP, 1, DEFAULT_EIRP_JP, 0xFF}
 
#define Adv_LC1_433   {433375000, 433375000, DEFAULT_CH_BAND , 1, 12, 0xFF}
 
#define ADV_LC1_865_IN   {865402500, 865402500, 0, 1, DEFAULT_EIRP_IN, 0xFF}
 
#define Adv_LC1_868   {868300000, 868300000, DEFAULT_CH_BAND , 1, 16,0xFF}
 
#define ADV_LC1_920_KR   {922300000,922300000, 0, 1, 14, 0xFF}
 
#define ADV_LC1_923   {923400000,923400000, 0, 1, 16, 0xFF}
 
#define ADV_LC1_923_JP   {923400000,923400000, DEFAULT_CH_SUBBAND_JP, 1, DEFAULT_EIRP_JP, 0xFF}
 
#define Adv_LC2_433   {433575000, 433575000, DEFAULT_CH_BAND , 1, 12, 0xFF}
 
#define ADV_LC2_865_IN   {865985000, 865985000, 0, 1, DEFAULT_EIRP_IN, 0xFF}
 
#define Adv_LC2_868   {868500000, 868500000, DEFAULT_CH_BAND , 1, 16,0xFF}
 
#define ADV_LC2_920_KR   {922500000,922500000, 0, 1, 14, 0xFF}
 
#define ALL_CHANNELS   1
 
#define DATA_RANGE_DEFINED   0x02
 
#define DATARATE_COUNT_JP   8
 
#define DEFAULT_CH_BAND   1
 
#define DEFAULT_CH_BAND_EU   1
 
#define DEFAULT_CH_SUBBAND_JP   1
 
#define DEFAULT_EIRP_AS   16
 
#define DEFAULT_EIRP_AU   30
 
#define DEFAULT_EIRP_EU   16
 
#define DEFAULT_EIRP_IN   30
 
#define DEFAULT_EIRP_JP   16
 
#define DEFAULT_EIRP_KR_HF   14
 
#define DEFAULT_EIRP_KR_LF   10
 
#define DEFAULT_EIRP_NA   30
 
#define DOWNSTREAM_CH0_AU   (FREQ_923300KHZ)
 
#define DOWNSTREAM_CH0_NA   FREQ_923300KHZ
 
#define DR0_PARAMS_AS   {8, 51, 0, -33 , 12, BW_125KHZ, MODULATION_LORA}
 
#define DR0_PARAMS_AU   {8, 51, 0, -33, 12, BW_125KHZ, MODULATION_LORA}
 
#define DR0_PARAMS_EU   {8,51,0,-33,12,BW_125KHZ,MODULATION_LORA}
 
#define DR0_PARAMS_IN   {8,51,0,-33,12,BW_125KHZ,MODULATION_LORA}
 
#define DR0_PARAMS_JP   {8, 51, 0, -33 , 12, BW_125KHZ, MODULATION_LORA}
 
#define DR0_PARAMS_KR   {8, 51, 0, -33, 12,BW_125KHZ,MODULATION_LORA}
 
#define DR0_PARAMS_NA   {18,11,0,-58,10,BW_125KHZ,MODULATION_LORA}
 
#define DR10_PARAMS_AU   {7, 242, 0, 1, 10, BW_500KHZ, MODULATION_LORA}
 
#define DR10_PARAMS_NA   {7,242,0,1,10,BW_500KHZ,MODULATION_LORA}
 
#define DR11_PARAMS_AU   {12 ,242, 0, -2, 9, BW_500KHZ, MODULATION_LORA}
 
#define DR11_PARAMS_NA   {12,242,0,-2,9,BW_500KHZ,MODULATION_LORA}
 
#define DR12_PARAMS_AU   {22 ,242, 0, -4, 8, BW_500KHZ, MODULATION_LORA}
 
#define DR12_PARAMS_NA   {22,242,0,-4,8,BW_500KHZ,MODULATION_LORA}
 
#define DR13_PARAMS_AU   {42 ,242, 0, -4, 7, BW_500KHZ, MODULATION_LORA}
 
#define DR13_PARAMS_NA   {42,242,0,-4,7,BW_500KHZ,MODULATION_LORA}
 
#define DR1_PARAMS_AS   {10, 51, 0, -50 , 11, BW_125KHZ, MODULATION_LORA}
 
#define DR1_PARAMS_AU   {11, 51, 0, -50, 11, BW_125KHZ, MODULATION_LORA}
 
#define DR1_PARAMS_EU   {11,51,0,-45,11,BW_125KHZ,MODULATION_LORA}
 
#define DR1_PARAMS_IN   {10,51,0,-50,11,BW_125KHZ,MODULATION_LORA}
 
#define DR1_PARAMS_JP   {10, 51, 0, -50 , 11, BW_125KHZ, MODULATION_LORA}
 
#define DR1_PARAMS_KR   {10, 51, 0, -50, 11,BW_125KHZ,MODULATION_LORA}
 
#define DR1_PARAMS_NA   {5,53,0,6,9,BW_125KHZ,MODULATION_LORA}
 
#define DR2_PARAMS_AS   {14, 51, 11, -58 , 10, BW_125KHZ, MODULATION_LORA}
 
#define DR2_PARAMS_AU   {18, 51, 0, -58, 10, BW_125KHZ, MODULATION_LORA}
 
#define DR2_PARAMS_EU   {23,51,0,-52,10,BW_125KHZ,MODULATION_LORA}
 
#define DR2_PARAMS_IN   {14,51,0,-58,10,BW_125KHZ,MODULATION_LORA}
 
#define DR2_PARAMS_JP   {14, 51, 11, -58 , 10, BW_125KHZ, MODULATION_LORA}
 
#define DR2_PARAMS_KR   {14, 51, 0, -58, 10,BW_125KHZ,MODULATION_LORA}
 
#define DR2_PARAMS_NA   {7,125,0,1,8,BW_125KHZ,MODULATION_LORA}
 
#define DR3_PARAMS_AS   {26, 115, 53, -62 , 9, BW_125KHZ, MODULATION_LORA}
 
#define DR3_PARAMS_AU   {28, 115, 0, -62, 9, BW_125KHZ, MODULATION_LORA}
 
#define DR3_PARAMS_EU   {28,115,0,-62,9,BW_125KHZ,MODULATION_LORA}
 
#define DR3_PARAMS_IN   {26,115,0,-62,9,BW_125KHZ,MODULATION_LORA}
 
#define DR3_PARAMS_JP   {26, 115, 53, -62 , 9, BW_125KHZ, MODULATION_LORA}
 
#define DR3_PARAMS_KR   {26, 115, 0, -62, 9,BW_125KHZ,MODULATION_LORA}
 
#define DR3_PARAMS_NA   {12,242,0,-2,7,BW_125KHZ,MODULATION_LORA}
 
#define DR4_PARAMS_AS   {49, 242, 125, -66 , 8, BW_125KHZ, MODULATION_LORA}
 
#define DR4_PARAMS_AU   {61, 242, 0, -66, 8, BW_125KHZ, MODULATION_LORA}
 
#define DR4_PARAMS_EU   {61,242,0,-66,8,BW_125KHZ,MODULATION_LORA}
 
#define DR4_PARAMS_IN   {49,242,0,-66,8,BW_125KHZ,MODULATION_LORA}
 
#define DR4_PARAMS_JP   {49, 242, 125, -66 , 8, BW_125KHZ, MODULATION_LORA}
 
#define DR4_PARAMS_KR   {49, 242, 0, -66, 8,BW_125KHZ,MODULATION_LORA}
 
#define DR4_PARAMS_NA   {22,242,0,-4,8,BW_500KHZ,MODULATION_LORA}
 
#define DR5_PARAMS_AS   {83, 242, 242, -68 , 7, BW_125KHZ, MODULATION_LORA}
 
#define DR5_PARAMS_AU   {83 ,242, 0, -68, 7, BW_125KHZ, MODULATION_LORA}
 
#define DR5_PARAMS_EU   {83,242,0,-68,7,BW_125KHZ,MODULATION_LORA}
 
#define DR5_PARAMS_IN   {83,242,0,-68,7,BW_125KHZ,MODULATION_LORA}
 
#define DR5_PARAMS_JP   {83, 242, 242, -68 , 7, BW_125KHZ, MODULATION_LORA}
 
#define DR5_PARAMS_KR   {83, 242, 0, -68, 7,BW_125KHZ,MODULATION_LORA}
 
#define DR5_PARAMS_NA   {0,0,0,0,0,BW_UNDEFINED,MODULATION_LORA}
 
#define DR6_PARAMS_AS   {60, 242, 242, -15 , 7, BW_250KHZ, MODULATION_LORA}
 
#define DR6_PARAMS_AU   {61 ,242, 0, -66, 8, BW_500KHZ, MODULATION_LORA}
 
#define DR6_PARAMS_EU   {60,242,0,-15,7,BW_250KHZ,MODULATION_LORA}
 
#define DR6_PARAMS_IN   {0,0,0,0,0,BW_UNDEFINED,MODULATION_LORA}
 
#define DR6_PARAMS_JP   {60, 242, 242, -15 , 7, BW_250KHZ, MODULATION_LORA}
 
#define DR6_PARAMS_NA   {0,0,0,0,0,BW_UNDEFINED,MODULATION_LORA}
 
#define DR7_PARAMS_AS   {100, 242, 242, -50 , 0, BW_UNDEFINED, MODULATION_FSK}
 
#define DR7_PARAMS_AU   {0, 0, 0, 0, 0, BW_UNDEFINED, MODULATION_LORA}
 
#define DR7_PARAMS_EU   {100,242,0,-50,0,BW_UNDEFINED,MODULATION_FSK}
 
#define DR7_PARAMS_IN   {8,242,0,-2,0,BW_UNDEFINED,MODULATION_FSK}
 
#define DR7_PARAMS_JP   {100, 242, 242, -50 , 0, BW_UNDEFINED, MODULATION_FSK}
 
#define DR7_PARAMS_NA   {0,0,0,0,0,BW_UNDEFINED,MODULATION_LORA}
 
#define DR8_PARAMS_AU   {7, 53, 0, 12, 12, BW_500KHZ, MODULATION_LORA}
 
#define DR8_PARAMS_NA   {35,53,0,-43,12,BW_500KHZ,MODULATION_LORA}
 
#define DR9_PARAMS_AU   {5, 129, 0, 6, 11, BW_500KHZ, MODULATION_LORA}
 
#define DR9_PARAMS_NA   {7,129,0,6,11,BW_500KHZ,MODULATION_LORA}
 
#define DUTY_CYCLE_DEFINED   0x04
 
#define FREQUENCY_DEFINED   0x01
 
#define LBT_ENABLE   true
 
#define LBT_SCAN_PERIOD_JP   5 /*ms*/
 
#define LBT_SCAN_PERIOD_KR   10 /*ms*/
 
#define LBT_SIGNAL_THRESHOLD_JP   -80 /*dBm*/
 
#define LBT_SIGNAL_THRESHOLD_KR   -65 /*dBm*/
 
#define LBT_TRANSMIT_CHANNEL_PAUSE_DURATION   50 /*ms*/
 
#define LC0_433   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC0_865_IN   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC0_868   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC0_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC0_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC0_920_KR   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC0_923   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC0_923_JP   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC10_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC10_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC11_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC11_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC12_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC12_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC13_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC13_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC14_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC14_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC15_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC15_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC16_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC16_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC17_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC17_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC18_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC18_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC19_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC19_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC1_433   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC1_865_IN   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC1_868   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC1_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC1_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC1_920_KR   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC1_923   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC1_923_JP   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC20_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC20_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC21_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC21_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC22_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC22_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC23_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC23_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC24_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC24_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC25_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC25_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC26_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC26_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC27_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC27_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC28_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC28_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC29_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC29_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC2_433   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC2_865_IN   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC2_868   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC2_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC2_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC2_920_KR   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
 
#define LC30_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC30_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC31_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC31_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC32_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC32_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC33_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC33_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC34_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC34_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC35_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC35_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC36_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC36_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC37_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC37_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC38_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC38_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC39_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC39_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC3_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC3_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC40_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC40_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC41_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC41_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC42_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC42_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC43_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC43_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC44_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC44_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC45_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC45_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC46_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC46_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC47_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC47_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC48_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC48_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC49_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC49_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC4_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC4_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC50_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC50_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC51_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC51_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC52_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC52_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC53_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC53_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC54_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC54_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC55_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC55_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC56_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC56_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC57_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC57_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC58_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC58_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC59_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC59_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC5_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC5_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC60_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC60_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC61_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC61_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC62_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC62_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC63_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC63_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC64_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
 
#define LC64_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
 
#define LC65_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
 
#define LC65_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
 
#define LC66_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
 
#define LC66_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
 
#define LC67_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
 
#define LC67_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
 
#define LC68_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
 
#define LC68_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
 
#define LC69_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
 
#define LC69_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
 
#define LC6_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC6_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC70_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
 
#define LC70_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
 
#define LC71_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
 
#define LC71_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
 
#define LC7_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC7_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC8_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC8_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define LC9_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
 
#define LC9_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
 
#define MAC_433_RX1_WINDOW_DATARATE   DR5
 
#define MAC_433_RX2_WINDOW_DATARATE   DR0
 
#define MAC_433_RX2_WINDOW_FREQ   FREQ_433050KHZ
 
#define MAC_868_RX1_WINDOW_DATARATE   DR0
 
#define MAC_868_RX2_WINDOW_DATARATE   DR0
 
#define MAC_868_RX2_WINDOW_FREQ   FREQ_869525KHZ
 
#define MAC_AS923_RX1_WINDOW_DATARATE   (DR2)
 
#define MAC_AS923_RX2_WINDOW_DATARATE   (DR2)
 
#define MAC_AS923_RX2_WINDOW_FREQ   (FREQ_923200KHZ)
 
#define MAC_RX1_WINDOW_DATARATE   MAC_868_RX1_WINDOW_DATARATE
 
#define MAC_RX1_WINDOW_DATARATE_AS   MAC_AS923_RX1_WINDOW_DATARATE
 
#define MAC_RX1_WINDOW_DATARATE_AU   (DR8)
 
#define MAC_RX1_WINDOW_DATARATE_IN   (DR0)
 
#define MAC_RX1_WINDOW_DATARATE_JP   (DR2)
 
#define MAC_RX1_WINDOW_DATARATE_KR   (DR0)
 
#define MAC_RX1_WINDOW_DATARATE_NA   DR10
 
#define MAC_RX2_WINDOW_DATARATE   MAC_868_RX2_WINDOW_DATARATE
 
#define MAC_RX2_WINDOW_DATARATE_AS   MAC_AS923_RX2_WINDOW_DATARATE
 
#define MAC_RX2_WINDOW_DATARATE_AU   (DR8)
 
#define MAC_RX2_WINDOW_DATARATE_IN   (DR2)
 
#define MAC_RX2_WINDOW_DATARATE_JP   (DR2)
 
#define MAC_RX2_WINDOW_DATARATE_KR   (DR0)
 
#define MAC_RX2_WINDOW_DATARATE_NA   DR8
 
#define MAC_RX2_WINDOW_FREQ   MAC_868_RX2_WINDOW_FREQ
 
#define MAC_RX2_WINDOW_FREQ_AS   MAC_AS923_RX2_WINDOW_FREQ
 
#define MAC_RX2_WINDOW_FREQ_AU   (FREQ_923300KHZ)
 
#define MAC_RX2_WINDOW_FREQ_IN   (FREQ_866550KHZ)
 
#define MAC_RX2_WINDOW_FREQ_JP   (FREQ_923200KHZ)
 
#define MAC_RX2_WINDOW_FREQ_KR   (FREQ_921900KHZ)
 
#define MAC_RX2_WINDOW_FREQ_NA   FREQ_923300KHZ
 
#define MAX_CHANNELS_AS   (16)
 
#define MAX_CHANNELS_AU_NA   72
 
#define MAX_CHANNELS_BANDWIDTH_125_AU_NA   64
 
#define MAX_CHANNELS_BANDWIDTH_500_AU_NA   8
 
#define MAX_CHANNELS_EU   16
 
#define MAX_CHANNELS_IN   16
 
#define MAX_CHANNELS_JP   16
 
#define MAX_CHANNELS_KR   16
 
#define MAX_CHANNELS_NA   72
 
#define MAX_CHANNELS_T1   MAX_CHANNELS_NA
 
#define MAX_CHANNELS_T2   MAX_CHANNELS_EU
 
#define MAX_DR_COUNT   14
 
#define MAX_DRPARAMS_EU   8
 
#define MAX_DRPARAMS_NA   14
 
#define MAX_DRPARAMS_T1   MAX_DRPARAMS_NA
 
#define MAX_DRPARAMS_T2   MAX_DRPARAMS_EU
 
#define MAX_NUM_SUBBANDS   (0)
 
#define MAX_NUM_SUBBANDS   (MAX_NUM_SUBBANDS_EU)
 
#define MAX_NUM_SUBBANDS_AS   (1)
 
#define MAX_NUM_SUBBANDS_EU   (6)
 
#define MAX_NUM_SUBBANDS_IN   (1)
 
#define MAX_NUM_SUBBANDS_JP   (2)
 
#define MAX_NUM_SUBBANDS_KR   (1)
 
#define MAX_SUBBANDS   8
 
#define MAX_TX_PWR_CNT   11
 
#define MAX_TX_PWR_INDEX_AS   7
 
#define MIN_CHANNEL_INDEX_IN   3
 
#define MIN_CHANNEL_INDEX_JP   2
 
#define MIN_CHANNEL_INDEX_KR   3
 
#define NEW_CHANNEL_INDEX_AS   2
 
#define NO_OF_CH_IN_SUBBAND   8
 
#define PDS_REG_AS_MAX_VALUE   3
 
#define PDS_REG_AU_MAX_VALUE   2
 
#define PDS_REG_EU868_FID1_MAX_VALUE   1
 
#define PDS_REG_EU868_FID2_MAX_VALUE   1
 
#define PDS_REG_IND_MAX_VALUE   2
 
#define PDS_REG_JPN_FID1_MAX_VALUE   2
 
#define PDS_REG_KR_FID1_MAX_VALUE   2
 
#define REG_AS_PDS_START_INDEX   PDS_FILE_REG_AS_05_IDX << 8
 
#define REG_AU_PDS_FID1_START_INDEX   PDS_FILE_REG_AU_09_IDX << 8
 
#define REG_EU868_PDS_FID1_START_INDEX   PDS_FILE_REG_EU868_04_IDX << 8
 
#define REG_EU868_PDS_FID2_START_INDEX   PDS_FILE_REG_EU868_12_IDX << 8
 
#define REG_IND_PDS_START_INDEX   PDS_FILE_REG_IND_07_IDX << 8
 
#define REG_JPN_PDS_FID1_START_INDEX   PDS_FILE_REG_JPN_08_IDX << 8
 
#define REG_KR_PDS_FID1_START_INDEX   PDS_FILE_REG_KR_06_IDX << 8
 
#define REG_NA_PDS_FID1_START_INDEX   PDS_FILE_REG_NA_03_IDX << 8
 
#define REG_PARAMS_TIMERS_COUNT   (4u)
 
#define SB0_433   {433000000, 434800000, 0/*, 100*/}
 
#define SB0_868   {863000000, 865000000, 0/*, 1000*/}
 
#define SB0_923   {902000000, 928000000, 0/*, 100*/}
 
#define SB0_923_DC_0   (100)
 
#define SB0_923_JP   {920000000, 922200000, 0}
 
#define SB0_923_JP_DC_0   (100)
 
#define SB0_DT   1000
 
#define SB1_868   {865000001, 868000000, 0/*, 100*/}
 
#define SB1_923_JP   {922400000, 928000000, 0}
 
#define SB1_923_JP_DC_0   (10)
 
#define SB1_DT   100
 
#define SB2_868   {868000001, 868600000, 0/*, 100*/}
 
#define SB2_DT   100
 
#define SB3_868   {868700000, 869200000, 0/*, 1000*/}
 
#define SB3_DT   1000
 
#define SB4_868   {869400000, 869650000, 0/*, 10*/}
 
#define SB4_DT   10
 
#define SB5_868   {869700000, 870000000, 0/*, 100*/}
 
#define SB5_DT   100
 
#define UPSTREAM_CH0_AU   (FREQ_915200KHZ)
 
#define UPSTREAM_CH0_NA   FREQ_902300KHZ
 
#define UPSTREAM_CH64_AU   (FREQ_915900KHZ)
 
#define UPSTREAM_CH64_NA   FREQ_903000KHZ
 
#define WITHOUT_DEFAULT_CHANNELS   0
 

Typedefs

typedef struct _channelParams ChannelParams_t
 
typedef union _CmnParams CmnParams_t
 
typedef struct _DRParams DRParams_t
 Regional parameters which are controlled by Data Rate. More...
 
typedef struct _DutyCycleTimer DutyCycleTimer_t
 
typedef struct _JoinBackoffTimer JoinBackoffTimer_t
 
typedef struct _JoinDutyCycleTimer JoinDutyCycleTimer_t
 
typedef struct _LBTTimer LBTTimer_t
 
typedef struct _OthChannelParams OthChannelParams_t
 
typedef enum _pds_reg_as_items pds_reg_as_items_t
 
typedef enum _pds_reg_au_items pds_reg_au_items_t
 
typedef enum
_pds_reg_fid1_eu868_items 		pds_reg_eu868_fid1_items_t
 
typedef enum
_pds_reg_eu868_fid2_items 		pds_reg_eu868_fid2_items_t
 
typedef enum _pds_reg_ind_items pds_reg_ind_items_t
 
typedef enum
_pds_reg_jpn_fid1_items 		pds_reg_jpn_fid1_items_t
 
typedef enum _pds_reg_kr_fid1_items pds_reg_kr_fid1_items_t
 
typedef enum _pds_reg_na_items pds_reg_na_items_t
 
typedef StackRetStatus_t(* pLoraRegGetAttr_t )(LorawanRegionalAttributes_t attr, void *attrInput, void *attrOutput)
 
typedef StackRetStatus_t(* pLoraRegSetAttr_t )(LorawanRegionalAttributes_t attr, void *attrInput)
 
typedef StackRetStatus_t(* pLoraRegValidateAttr_t )(LorawanRegionalAttributes_t attr, void *attrInput)
 
typedef void(* pUpdateChIdStatus_t )(uint8_t chid, bool statusNew)
 
typedef struct _RegParams RegParams_t
 
typedef struct _RegParamsType1 RegParamsType1_t
 
typedef struct _RegParamsType2 RegParamsType2_t
 
typedef struct _RegPdsItems RegPdsItems_t
 
typedef struct _SubBandParams SubBandParams_t
 

Enumerations

enum  _pds_reg_as_items {
  PDS_REG_AS_CH_PARAM_1 = REG_AS_PDS_START_INDEX,
  PDS_REG_AS_CH_PARAM_2,
  PDS_REG_AS_BAND
}
 
enum  _pds_reg_au_items {
  PDS_REG_AU_CH_PARAM = REG_AU_PDS_FID1_START_INDEX,
  PDS_REG_AU_LAST_USED_SB
}
 
enum  _pds_reg_eu868_fid2_items { PDS_REG_EU868_CH_PARAM_2 = REG_EU868_PDS_FID2_START_INDEX }
 
enum  _pds_reg_fid1_eu868_items { PDS_REG_EU868_CH_PARAM_1 = REG_EU868_PDS_FID1_START_INDEX }
 
enum  _pds_reg_ind_items {
  PDS_REG_IND_CH_PARAM_1 = REG_IND_PDS_START_INDEX,
  PDS_REG_IND_CH_PARAM_2
}
 
enum  _pds_reg_jpn_fid1_items {
  PDS_REG_JPN_CH_PARAM_1 = REG_JPN_PDS_FID1_START_INDEX,
  PDS_REG_JPN_CH_PARAM_2
}
 
enum  _pds_reg_kr_fid1_items {
  PDS_REG_KR_CH_PARAM_1 = REG_KR_PDS_FID1_START_INDEX,
  PDS_REG_KR_CH_PARAM_2
}
 
enum  _pds_reg_na_items {
  PDS_REG_NA_CH_PARAM = REG_NA_PDS_FID1_START_INDEX,
  PDS_REG_NA_LAST_USED_SB,
  PDS_REG_NA_MAX_VALUE
}
 

Functions

StackRetStatus_t CreateAllRegSoftwareTimers (void)
 
void Enableallchannels (void)
 
void InitDefault433Channels (void)
 
void InitDefault868Channels (void)
 
void InitDefault920Channels (void)
 
void InitDefault920ChannelsKR (void)
 
void InitDefault923Channels (void)
 
StackRetStatus_t InValidAttr (LorawanRegionalAttributes_t attr, void *attrInput)
 
StackRetStatus_t InValidGetAttr (LorawanRegionalAttributes_t attr, void *attrInput, void *attrOutput)
 
void JoinBackoffCallback (uint8_t param)
 
StackRetStatus_t LORAReg_InitAS (IsmBand_t ismBand)
 
StackRetStatus_t LORAReg_InitAU (IsmBand_t ismBand)
 
StackRetStatus_t LORAReg_InitEU (IsmBand_t ismBand)
 
void LORAREG_InitGetAttrFnPtrsAS (void)
 
void LORAREG_InitGetAttrFnPtrsAU (void)
 
void LORAREG_InitGetAttrFnPtrsEU (void)
 
void LORAREG_InitGetAttrFnPtrsIN (void)
 
void LORAREG_InitGetAttrFnPtrsJP (void)
 
void LORAREG_InitGetAttrFnPtrsKR (void)
 
void LORAREG_InitGetAttrFnPtrsNA (void)
 
StackRetStatus_t LORAReg_InitIN (IsmBand_t ismBand)
 
StackRetStatus_t LORAReg_InitJP (IsmBand_t ismBand)
 
StackRetStatus_t LORAReg_InitKR (IsmBand_t ismBand)
 
StackRetStatus_t LORAReg_InitNA (IsmBand_t ismBand)
 
void LORAREG_InitSetAttrFnPtrsAS (void)
 
void LORAREG_InitSetAttrFnPtrsAU (void)
 
void LORAREG_InitSetAttrFnPtrsEU (void)
 
void LORAREG_InitSetAttrFnPtrsIN (void)
 
void LORAREG_InitSetAttrFnPtrsJP (void)
 
void LORAREG_InitSetAttrFnPtrsKR (void)
 
void LORAREG_InitSetAttrFnPtrsNA (void)
 
void LORAREG_InitValidateAttrFnPtrsAS (void)
 
void LORAREG_InitValidateAttrFnPtrsAU (void)
 
void LORAREG_InitValidateAttrFnPtrsEU (void)
 
void LORAREG_InitValidateAttrFnPtrsIN (void)
 
void LORAREG_InitValidateAttrFnPtrsJP (void)
 
void LORAREG_InitValidateAttrFnPtrsKR (void)
 
void LORAREG_InitValidateAttrFnPtrsNA (void)
 
void StopAllRegSoftwareTimers (void)
 

Variables

RegParams_t RegParams
 
uint8_t regTimerId [REG_PARAMS_TIMERS_COUNT]
 

#define Adv_LC0_433   {433175000, 433175000, DEFAULT_CH_BAND , 1, 12, 0xFF}
#define ADV_LC0_865_IN   {865062500, 865062500, 0, 1, DEFAULT_EIRP_IN, 0xFF}
#define Adv_LC0_868   {868100000, 868100000, DEFAULT_CH_BAND , 1, 16,0xFF}
#define ADV_LC0_920_KR   {922100000,922100000, 0, 1, 14, 0xFF}
#define ADV_LC0_923   {923200000,923200000, 0, 1, 16, 0xFF}
#define ADV_LC0_923_JP   {923200000,923200000, DEFAULT_CH_SUBBAND_JP, 1, DEFAULT_EIRP_JP, 0xFF}
#define Adv_LC1_433   {433375000, 433375000, DEFAULT_CH_BAND , 1, 12, 0xFF}
#define ADV_LC1_865_IN   {865402500, 865402500, 0, 1, DEFAULT_EIRP_IN, 0xFF}
#define Adv_LC1_868   {868300000, 868300000, DEFAULT_CH_BAND , 1, 16,0xFF}
#define ADV_LC1_920_KR   {922300000,922300000, 0, 1, 14, 0xFF}
#define ADV_LC1_923   {923400000,923400000, 0, 1, 16, 0xFF}
#define ADV_LC1_923_JP   {923400000,923400000, DEFAULT_CH_SUBBAND_JP, 1, DEFAULT_EIRP_JP, 0xFF}
#define Adv_LC2_433   {433575000, 433575000, DEFAULT_CH_BAND , 1, 12, 0xFF}
#define ADV_LC2_865_IN   {865985000, 865985000, 0, 1, DEFAULT_EIRP_IN, 0xFF}
#define Adv_LC2_868   {868500000, 868500000, DEFAULT_CH_BAND , 1, 16,0xFF}
#define ADV_LC2_920_KR   {922500000,922500000, 0, 1, 14, 0xFF}
#define ALL_CHANNELS   1
#define DATA_RANGE_DEFINED   0x02

Referenced by setDataRangeT2(), UpdateChannelIdStatusT2(), and ValidateChannelMaskT2().

#define DATARATE_COUNT_JP   8
#define DEFAULT_CH_BAND   1
#define DEFAULT_CH_BAND_EU   1
#define DEFAULT_CH_SUBBAND_JP   1
#define DEFAULT_EIRP_AS   16

Referenced by LORAReg_InitAS().

#define DEFAULT_EIRP_AU   30

Referenced by LORAReg_InitAU().

#define DEFAULT_EIRP_EU   16

Referenced by LORAReg_InitEU().

#define DEFAULT_EIRP_IN   30

Referenced by LORAReg_InitIN().

#define DEFAULT_EIRP_JP   16

Referenced by LORAReg_InitJP().

#define DEFAULT_EIRP_KR_HF   14

Referenced by LORAReg_InitKR(), and UpdateChannelIdStatusT4().

#define DEFAULT_EIRP_KR_LF   10

Referenced by UpdateChannelIdStatusT4().

#define DEFAULT_EIRP_NA   30

Referenced by LORAReg_InitNA().

#define DOWNSTREAM_CH0_AU   (FREQ_923300KHZ)

Referenced by LORAReg_InitAU().

#define DOWNSTREAM_CH0_NA   FREQ_923300KHZ

Referenced by LORAReg_InitNA().

#define DR0_PARAMS_AS   {8, 51, 0, -33 , 12, BW_125KHZ, MODULATION_LORA}
#define DR0_PARAMS_AU   {8, 51, 0, -33, 12, BW_125KHZ, MODULATION_LORA}
#define DR0_PARAMS_EU   {8,51,0,-33,12,BW_125KHZ,MODULATION_LORA}
#define DR0_PARAMS_IN   {8,51,0,-33,12,BW_125KHZ,MODULATION_LORA}
#define DR0_PARAMS_JP   {8, 51, 0, -33 , 12, BW_125KHZ, MODULATION_LORA}
#define DR0_PARAMS_KR   {8, 51, 0, -33, 12,BW_125KHZ,MODULATION_LORA}
#define DR0_PARAMS_NA   {18,11,0,-58,10,BW_125KHZ,MODULATION_LORA}
#define DR10_PARAMS_AU   {7, 242, 0, 1, 10, BW_500KHZ, MODULATION_LORA}
#define DR10_PARAMS_NA   {7,242,0,1,10,BW_500KHZ,MODULATION_LORA}
#define DR11_PARAMS_AU   {12 ,242, 0, -2, 9, BW_500KHZ, MODULATION_LORA}
#define DR11_PARAMS_NA   {12,242,0,-2,9,BW_500KHZ,MODULATION_LORA}
#define DR12_PARAMS_AU   {22 ,242, 0, -4, 8, BW_500KHZ, MODULATION_LORA}
#define DR12_PARAMS_NA   {22,242,0,-4,8,BW_500KHZ,MODULATION_LORA}
#define DR13_PARAMS_AU   {42 ,242, 0, -4, 7, BW_500KHZ, MODULATION_LORA}
#define DR13_PARAMS_NA   {42,242,0,-4,7,BW_500KHZ,MODULATION_LORA}
#define DR1_PARAMS_AS   {10, 51, 0, -50 , 11, BW_125KHZ, MODULATION_LORA}
#define DR1_PARAMS_AU   {11, 51, 0, -50, 11, BW_125KHZ, MODULATION_LORA}
#define DR1_PARAMS_EU   {11,51,0,-45,11,BW_125KHZ,MODULATION_LORA}
#define DR1_PARAMS_IN   {10,51,0,-50,11,BW_125KHZ,MODULATION_LORA}
#define DR1_PARAMS_JP   {10, 51, 0, -50 , 11, BW_125KHZ, MODULATION_LORA}
#define DR1_PARAMS_KR   {10, 51, 0, -50, 11,BW_125KHZ,MODULATION_LORA}
#define DR1_PARAMS_NA   {5,53,0,6,9,BW_125KHZ,MODULATION_LORA}
#define DR2_PARAMS_AS   {14, 51, 11, -58 , 10, BW_125KHZ, MODULATION_LORA}
#define DR2_PARAMS_AU   {18, 51, 0, -58, 10, BW_125KHZ, MODULATION_LORA}
#define DR2_PARAMS_EU   {23,51,0,-52,10,BW_125KHZ,MODULATION_LORA}
#define DR2_PARAMS_IN   {14,51,0,-58,10,BW_125KHZ,MODULATION_LORA}
#define DR2_PARAMS_JP   {14, 51, 11, -58 , 10, BW_125KHZ, MODULATION_LORA}
#define DR2_PARAMS_KR   {14, 51, 0, -58, 10,BW_125KHZ,MODULATION_LORA}
#define DR2_PARAMS_NA   {7,125,0,1,8,BW_125KHZ,MODULATION_LORA}
#define DR3_PARAMS_AS   {26, 115, 53, -62 , 9, BW_125KHZ, MODULATION_LORA}
#define DR3_PARAMS_AU   {28, 115, 0, -62, 9, BW_125KHZ, MODULATION_LORA}
#define DR3_PARAMS_EU   {28,115,0,-62,9,BW_125KHZ,MODULATION_LORA}
#define DR3_PARAMS_IN   {26,115,0,-62,9,BW_125KHZ,MODULATION_LORA}
#define DR3_PARAMS_JP   {26, 115, 53, -62 , 9, BW_125KHZ, MODULATION_LORA}
#define DR3_PARAMS_KR   {26, 115, 0, -62, 9,BW_125KHZ,MODULATION_LORA}
#define DR3_PARAMS_NA   {12,242,0,-2,7,BW_125KHZ,MODULATION_LORA}
#define DR4_PARAMS_AS   {49, 242, 125, -66 , 8, BW_125KHZ, MODULATION_LORA}
#define DR4_PARAMS_AU   {61, 242, 0, -66, 8, BW_125KHZ, MODULATION_LORA}
#define DR4_PARAMS_EU   {61,242,0,-66,8,BW_125KHZ,MODULATION_LORA}
#define DR4_PARAMS_IN   {49,242,0,-66,8,BW_125KHZ,MODULATION_LORA}
#define DR4_PARAMS_JP   {49, 242, 125, -66 , 8, BW_125KHZ, MODULATION_LORA}
#define DR4_PARAMS_KR   {49, 242, 0, -66, 8,BW_125KHZ,MODULATION_LORA}
#define DR4_PARAMS_NA   {22,242,0,-4,8,BW_500KHZ,MODULATION_LORA}
#define DR5_PARAMS_AS   {83, 242, 242, -68 , 7, BW_125KHZ, MODULATION_LORA}
#define DR5_PARAMS_AU   {83 ,242, 0, -68, 7, BW_125KHZ, MODULATION_LORA}
#define DR5_PARAMS_EU   {83,242,0,-68,7,BW_125KHZ,MODULATION_LORA}
#define DR5_PARAMS_IN   {83,242,0,-68,7,BW_125KHZ,MODULATION_LORA}
#define DR5_PARAMS_JP   {83, 242, 242, -68 , 7, BW_125KHZ, MODULATION_LORA}
#define DR5_PARAMS_KR   {83, 242, 0, -68, 7,BW_125KHZ,MODULATION_LORA}
#define DR5_PARAMS_NA   {0,0,0,0,0,BW_UNDEFINED,MODULATION_LORA}
#define DR6_PARAMS_AS   {60, 242, 242, -15 , 7, BW_250KHZ, MODULATION_LORA}
#define DR6_PARAMS_AU   {61 ,242, 0, -66, 8, BW_500KHZ, MODULATION_LORA}
#define DR6_PARAMS_EU   {60,242,0,-15,7,BW_250KHZ,MODULATION_LORA}
#define DR6_PARAMS_IN   {0,0,0,0,0,BW_UNDEFINED,MODULATION_LORA}
#define DR6_PARAMS_JP   {60, 242, 242, -15 , 7, BW_250KHZ, MODULATION_LORA}
#define DR6_PARAMS_NA   {0,0,0,0,0,BW_UNDEFINED,MODULATION_LORA}
#define DR7_PARAMS_AS   {100, 242, 242, -50 , 0, BW_UNDEFINED, MODULATION_FSK}
#define DR7_PARAMS_AU   {0, 0, 0, 0, 0, BW_UNDEFINED, MODULATION_LORA}
#define DR7_PARAMS_EU   {100,242,0,-50,0,BW_UNDEFINED,MODULATION_FSK}
#define DR7_PARAMS_IN   {8,242,0,-2,0,BW_UNDEFINED,MODULATION_FSK}
#define DR7_PARAMS_JP   {100, 242, 242, -50 , 0, BW_UNDEFINED, MODULATION_FSK}
#define DR7_PARAMS_NA   {0,0,0,0,0,BW_UNDEFINED,MODULATION_LORA}
#define DR8_PARAMS_AU   {7, 53, 0, 12, 12, BW_500KHZ, MODULATION_LORA}
#define DR8_PARAMS_NA   {35,53,0,-43,12,BW_500KHZ,MODULATION_LORA}
#define DR9_PARAMS_AU   {5, 129, 0, 6, 11, BW_500KHZ, MODULATION_LORA}
#define DR9_PARAMS_NA   {7,129,0,6,11,BW_500KHZ,MODULATION_LORA}
#define DUTY_CYCLE_DEFINED   0x04

Referenced by setDutyCycle().

#define FREQUENCY_DEFINED   0x01

Referenced by setFrequency(), UpdateChannelIdStatusT2(), and ValidateChannelMaskT2().

#define LBT_ENABLE   true

Referenced by LORAREG_GetAttr_DefLBTParams().

#define LBT_SCAN_PERIOD_JP   5 /*ms*/

Referenced by LORAReg_InitJP().

#define LBT_SCAN_PERIOD_KR   10 /*ms*/

Referenced by LORAReg_InitKR().

#define LBT_SIGNAL_THRESHOLD_JP   -80 /*dBm*/

Referenced by LORAReg_InitJP().

#define LBT_SIGNAL_THRESHOLD_KR   -65 /*dBm*/

Referenced by LORAReg_InitKR().

#define LBT_TRANSMIT_CHANNEL_PAUSE_DURATION   50 /*ms*/

Referenced by setLBTTimer().

#define LC0_433   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC0_865_IN   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC0_868   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC0_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC0_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC0_920_KR   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC0_923   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC0_923_JP   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC10_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC10_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC11_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC11_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC12_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC12_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC13_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC13_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC14_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC14_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC15_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC15_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC16_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC16_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC17_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC17_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC18_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC18_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC19_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC19_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC1_433   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC1_865_IN   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC1_868   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC1_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC1_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC1_920_KR   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC1_923   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC1_923_JP   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC20_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC20_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC21_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC21_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC22_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC22_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC23_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC23_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC24_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC24_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC25_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC25_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC26_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC26_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC27_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC27_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC28_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC28_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC29_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC29_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC2_433   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC2_865_IN   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC2_868   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC2_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC2_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC2_920_KR   {ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) }}
#define LC30_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC30_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC31_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC31_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC32_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC32_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC33_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC33_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC34_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC34_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC35_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC35_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC36_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC36_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC37_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC37_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC38_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC38_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC39_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC39_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC3_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC3_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC40_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC40_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC41_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC41_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC42_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC42_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC43_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC43_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC44_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC44_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC45_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC45_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC46_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC46_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC47_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC47_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC48_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC48_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC49_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC49_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC4_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC4_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC50_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC50_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC51_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC51_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC52_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC52_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC53_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC53_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC54_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC54_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC55_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC55_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC56_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC56_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC57_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC57_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC58_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC58_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC59_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC59_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC5_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC5_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC60_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC60_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC61_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC61_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC62_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC62_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC63_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC63_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC64_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
#define LC64_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
#define LC65_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
#define LC65_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
#define LC66_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
#define LC66_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
#define LC67_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
#define LC67_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
#define LC68_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
#define LC68_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
#define LC69_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
#define LC69_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
#define LC6_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC6_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC70_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
#define LC70_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
#define LC71_915_AU   { ENABLED, { ( ( DR6 << SHIFT4 ) | DR6 ) } }
#define LC71_915_NA   { ENABLED, { ( ( DR4 << SHIFT4 ) | DR4 ) } }
#define LC7_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC7_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC8_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC8_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define LC9_915_AU   { ENABLED, { ( ( DR5 << SHIFT4 ) | DR0 ) } }
#define LC9_915_NA   { ENABLED, { ( ( DR3 << SHIFT4 ) | DR0 ) } }
#define MAC_433_RX1_WINDOW_DATARATE   DR5

Referenced by LORAReg_InitEU().

#define MAC_433_RX2_WINDOW_DATARATE   DR0

Referenced by LORAReg_InitEU().

#define MAC_433_RX2_WINDOW_FREQ   FREQ_433050KHZ

Referenced by LORAReg_InitEU().

#define MAC_868_RX1_WINDOW_DATARATE   DR0

Referenced by LORAReg_InitEU().

#define MAC_868_RX2_WINDOW_DATARATE   DR0

Referenced by LORAReg_InitEU().

#define MAC_868_RX2_WINDOW_FREQ   FREQ_869525KHZ

Referenced by LORAReg_InitEU().

#define MAC_AS923_RX1_WINDOW_DATARATE   (DR2)
#define MAC_AS923_RX2_WINDOW_DATARATE   (DR2)
#define MAC_AS923_RX2_WINDOW_FREQ   (FREQ_923200KHZ)
#define MAC_RX1_WINDOW_DATARATE   MAC_868_RX1_WINDOW_DATARATE
#define MAC_RX1_WINDOW_DATARATE_AS   MAC_AS923_RX1_WINDOW_DATARATE

Referenced by LORAReg_InitAS().

#define MAC_RX1_WINDOW_DATARATE_AU   (DR8)

Referenced by LORAReg_InitAU().

#define MAC_RX1_WINDOW_DATARATE_IN   (DR0)

Referenced by LORAReg_InitIN().

#define MAC_RX1_WINDOW_DATARATE_JP   (DR2)

Referenced by LORAReg_InitJP().

#define MAC_RX1_WINDOW_DATARATE_KR   (DR0)

Referenced by LORAReg_InitKR().

#define MAC_RX1_WINDOW_DATARATE_NA   DR10

Referenced by LORAReg_InitNA().

#define MAC_RX2_WINDOW_DATARATE   MAC_868_RX2_WINDOW_DATARATE
#define MAC_RX2_WINDOW_DATARATE_AS   MAC_AS923_RX2_WINDOW_DATARATE

Referenced by LORAReg_InitAS().

#define MAC_RX2_WINDOW_DATARATE_AU   (DR8)

Referenced by LORAReg_InitAU().

#define MAC_RX2_WINDOW_DATARATE_IN   (DR2)

Referenced by LORAReg_InitIN().

#define MAC_RX2_WINDOW_DATARATE_JP   (DR2)

Referenced by LORAReg_InitJP().

#define MAC_RX2_WINDOW_DATARATE_KR   (DR0)

Referenced by LORAReg_InitKR().

#define MAC_RX2_WINDOW_DATARATE_NA   DR8

Referenced by LORAReg_InitNA().

#define MAC_RX2_WINDOW_FREQ   MAC_868_RX2_WINDOW_FREQ
#define MAC_RX2_WINDOW_FREQ_AS   MAC_AS923_RX2_WINDOW_FREQ

Referenced by LORAReg_InitAS().

#define MAC_RX2_WINDOW_FREQ_AU   (FREQ_923300KHZ)

Referenced by LORAReg_InitAU().

#define MAC_RX2_WINDOW_FREQ_IN   (FREQ_866550KHZ)

Referenced by LORAReg_InitIN().

#define MAC_RX2_WINDOW_FREQ_JP   (FREQ_923200KHZ)

Referenced by LORAReg_InitJP().

#define MAC_RX2_WINDOW_FREQ_KR   (FREQ_921900KHZ)

Referenced by LORAReg_InitKR().

#define MAC_RX2_WINDOW_FREQ_NA   FREQ_923300KHZ

Referenced by LORAReg_InitNA().

#define MAX_CHANNELS_AS   (16)

Referenced by LORAReg_InitAS().

#define MAX_CHANNELS_AU_NA   72

Referenced by LORAReg_InitAU().

#define MAX_CHANNELS_BANDWIDTH_125_AU_NA   64

Referenced by getRx1WindowparamsType1(), GetTxChannelConfig1(), LORAReg_InitAU(), LORAReg_InitNA(), SearchAvailableChannel1(), and setJoinSuccess().

#define MAX_CHANNELS_BANDWIDTH_500_AU_NA   8

Referenced by LORAReg_InitAU(), LORAReg_InitNA(), and SearchAvailableChannel1().

#define MAX_CHANNELS_EU   16
#define MAX_CHANNELS_IN   16

Referenced by InitDefault865Channels(), and LORAReg_InitIN().

#define MAX_CHANNELS_JP   16

Referenced by LORAReg_InitJP().

#define MAX_CHANNELS_KR   16

Referenced by LORAReg_InitKR().

#define MAX_CHANNELS_NA   72
#define MAX_CHANNELS_T1   MAX_CHANNELS_NA

Referenced by LORAReg_InitNA().

#define MAX_CHANNELS_T2   MAX_CHANNELS_EU

Referenced by LORAReg_InitEU().

#define MAX_DR_COUNT   14
#define MAX_DRPARAMS_EU   8
#define MAX_DRPARAMS_NA   14
#define MAX_DRPARAMS_T1   MAX_DRPARAMS_NA
#define MAX_DRPARAMS_T2   MAX_DRPARAMS_EU
#define MAX_NUM_SUBBANDS   (0)
#define MAX_NUM_SUBBANDS   (MAX_NUM_SUBBANDS_EU)
#define MAX_NUM_SUBBANDS_AS   (1)

Referenced by LORAReg_InitAS().

#define MAX_NUM_SUBBANDS_EU   (6)

Referenced by LORAReg_InitEU().

#define MAX_NUM_SUBBANDS_IN   (1)

Referenced by LORAReg_InitIN().

#define MAX_NUM_SUBBANDS_JP   (2)

Referenced by LORAReg_InitJP().

#define MAX_NUM_SUBBANDS_KR   (1)

Referenced by LORAReg_InitKR().

#define MAX_SUBBANDS   8

Referenced by Enableallchannels(), SearchAvailableChannel1(), setEnableAllChs(), and setJoinSuccess().

#define MAX_TX_PWR_CNT   11
#define MAX_TX_PWR_INDEX_AS   7

Referenced by LORAReg_InitAS().

#define MIN_CHANNEL_INDEX_IN   3

Referenced by InitDefault865Channels(), and LORAReg_InitIN().

#define MIN_CHANNEL_INDEX_JP   2

Referenced by LORAReg_InitJP().

#define MIN_CHANNEL_INDEX_KR   3

Referenced by LORAReg_InitKR().

#define NEW_CHANNEL_INDEX_AS   2

Referenced by LORAReg_InitAS().

#define NO_OF_CH_IN_SUBBAND   8

Referenced by Enableallchannels(), SearchAvailableChannel1(), setEnableAllChs(), and setJoinSuccess().

#define PDS_REG_AS_MAX_VALUE   3

Referenced by LORAReg_InitAS().

#define PDS_REG_AU_MAX_VALUE   2

Referenced by LORAReg_InitAU().

#define PDS_REG_EU868_FID1_MAX_VALUE   1

Referenced by LORAReg_InitEU().

#define PDS_REG_EU868_FID2_MAX_VALUE   1

Referenced by LORAReg_InitEU().

#define PDS_REG_IND_MAX_VALUE   2

Referenced by LORAReg_InitIN().

#define PDS_REG_JPN_FID1_MAX_VALUE   2

Referenced by LORAReg_InitJP().

#define PDS_REG_KR_FID1_MAX_VALUE   2

Referenced by LORAReg_InitKR().

#define REG_AS_PDS_START_INDEX   PDS_FILE_REG_AS_05_IDX << 8
#define REG_AU_PDS_FID1_START_INDEX   PDS_FILE_REG_AU_09_IDX << 8
#define REG_EU868_PDS_FID1_START_INDEX   PDS_FILE_REG_EU868_04_IDX << 8
#define REG_EU868_PDS_FID2_START_INDEX   PDS_FILE_REG_EU868_12_IDX << 8
#define REG_IND_PDS_START_INDEX   PDS_FILE_REG_IND_07_IDX << 8
#define REG_JPN_PDS_FID1_START_INDEX   PDS_FILE_REG_JPN_08_IDX << 8
#define REG_KR_PDS_FID1_START_INDEX   PDS_FILE_REG_KR_06_IDX << 8
#define REG_NA_PDS_FID1_START_INDEX   PDS_FILE_REG_NA_03_IDX << 8
#define REG_PARAMS_TIMERS_COUNT   (4u)

Referenced by CreateAllRegSoftwareTimers(), and StopAllRegSoftwareTimers().

#define SB0_433   {433000000, 434800000, 0/*, 100*/}
#define SB0_868   {863000000, 865000000, 0/*, 1000*/}
#define SB0_923   {902000000, 928000000, 0/*, 100*/}
#define SB0_923_DC_0   (100)
#define SB0_923_JP   {920000000, 922200000, 0}
#define SB0_923_JP_DC_0   (100)
#define SB0_DT   1000
#define SB1_868   {865000001, 868000000, 0/*, 100*/}
#define SB1_923_JP   {922400000, 928000000, 0}
#define SB1_923_JP_DC_0   (10)
#define SB1_DT   100
#define SB2_868   {868000001, 868600000, 0/*, 100*/}
#define SB2_DT   100
#define SB3_868   {868700000, 869200000, 0/*, 1000*/}
#define SB3_DT   1000
#define SB4_868   {869400000, 869650000, 0/*, 10*/}
#define SB4_DT   10
#define SB5_868   {869700000, 870000000, 0/*, 100*/}
#define SB5_DT   100
#define UPSTREAM_CH0_AU   (FREQ_915200KHZ)

Referenced by LORAReg_InitAU().

#define UPSTREAM_CH0_NA   FREQ_902300KHZ

Referenced by LORAReg_InitNA().

#define UPSTREAM_CH64_AU   (FREQ_915900KHZ)

Referenced by LORAReg_InitAU().

#define UPSTREAM_CH64_NA   FREQ_903000KHZ

Referenced by LORAReg_InitNA().

#define WITHOUT_DEFAULT_CHANNELS   0

typedef struct _channelParams ChannelParams_t
typedef union _CmnParams CmnParams_t
typedef struct _DRParams DRParams_t

Regional parameters which are controlled by Data Rate.

typedef struct _DutyCycleTimer DutyCycleTimer_t
typedef struct _JoinBackoffTimer JoinBackoffTimer_t
typedef struct _JoinDutyCycleTimer JoinDutyCycleTimer_t
typedef struct _LBTTimer LBTTimer_t
typedef struct _OthChannelParams OthChannelParams_t
typedef enum _pds_reg_as_items pds_reg_as_items_t
typedef enum _pds_reg_au_items pds_reg_au_items_t
typedef enum _pds_reg_fid1_eu868_items pds_reg_eu868_fid1_items_t
typedef enum _pds_reg_eu868_fid2_items pds_reg_eu868_fid2_items_t
typedef enum _pds_reg_ind_items pds_reg_ind_items_t
typedef enum _pds_reg_jpn_fid1_items pds_reg_jpn_fid1_items_t
typedef enum _pds_reg_kr_fid1_items pds_reg_kr_fid1_items_t
typedef enum _pds_reg_na_items pds_reg_na_items_t
typedef StackRetStatus_t(* pLoraRegGetAttr_t)(LorawanRegionalAttributes_t attr, void *attrInput, void *attrOutput)
typedef StackRetStatus_t(* pLoraRegSetAttr_t)(LorawanRegionalAttributes_t attr, void *attrInput)
typedef StackRetStatus_t(* pLoraRegValidateAttr_t)(LorawanRegionalAttributes_t attr, void *attrInput)
typedef void(* pUpdateChIdStatus_t)(uint8_t chid, bool statusNew)
typedef struct _RegParams RegParams_t
typedef struct _RegParamsType1 RegParamsType1_t
typedef struct _RegParamsType2 RegParamsType2_t
typedef struct _RegPdsItems RegPdsItems_t
typedef struct _SubBandParams SubBandParams_t

enum _pds_reg_as_items
Enumerator
PDS_REG_AS_CH_PARAM_1 
PDS_REG_AS_CH_PARAM_2 
PDS_REG_AS_BAND 
enum _pds_reg_au_items
Enumerator
PDS_REG_AU_CH_PARAM 
PDS_REG_AU_LAST_USED_SB 
enum _pds_reg_eu868_fid2_items
Enumerator
PDS_REG_EU868_CH_PARAM_2 
enum _pds_reg_fid1_eu868_items
Enumerator
PDS_REG_EU868_CH_PARAM_1 
enum _pds_reg_ind_items
Enumerator
PDS_REG_IND_CH_PARAM_1 
PDS_REG_IND_CH_PARAM_2 
enum _pds_reg_jpn_fid1_items
Enumerator
PDS_REG_JPN_CH_PARAM_1 
PDS_REG_JPN_CH_PARAM_2 
enum _pds_reg_kr_fid1_items
Enumerator
PDS_REG_KR_CH_PARAM_1 
PDS_REG_KR_CH_PARAM_2 
enum _pds_reg_na_items
Enumerator
PDS_REG_NA_CH_PARAM 
PDS_REG_NA_LAST_USED_SB 
PDS_REG_NA_MAX_VALUE 

StackRetStatus_t CreateAllRegSoftwareTimers ( void  )

References i, LORAWAN_SUCCESS, REG_PARAMS_TIMERS_COUNT, regTimerId, and SwTimerCreate().

Referenced by LORAREG_Init().

void Enableallchannels ( void  )

References _RegPdsItems::ch_param_1_item_id, _RegParams::cmnParams, ENABLED, i, _RegPdsItems::lastUsedSB, _RegParamsType1::lastUsedSB, MAX_SUBBANDS, NO_OF_CH_IN_SUBBAND, _CmnParams::paramsType1, _RegParams::pChParams, PDS_STORE, _RegParams::regParamItems, and _channelParams::status.

Referenced by LORAREG_EnableallChannels().

void InitDefault433Channels ( void  )

References _channelParams::dataRange, i, _RegParams::maxChannels, _RegParams::pChParams, _RegParams::pOtherChParams, _RegParams::pSubBandParams, RegParams, and _DataRange::value.

Referenced by LORAREG_EnableallChannels(), and LORAReg_InitEU().

void InitDefault868Channels ( void  )

References _RegParams::cmnParams, _channelParams::dataRange, i, _RegParams::maxChannels, _CmnParams::paramsType2, _RegParams::pChParams, _RegParams::pOtherChParams, _RegParams::pSubBandParams, RegParams, _RegParamsType2::subBandDutyCycle, SubBandDutyCycle868, and _DataRange::value.

Referenced by LORAREG_EnableallChannels(), and LORAReg_InitEU().

void InitDefault920Channels ( void  )

References _RegParamsType2::channelTimer, _RegParams::cmnParams, _channelParams::dataRange, i, _RegParams::lastUsedChannelIndex, _RegParams::maxChannels, _CmnParams::paramsType2, _RegParams::pChParams, _RegParams::pOtherChParams, _RegParams::pSubBandParams, RegParams, _RegParamsType2::subBandDutyCycle, SubBandDutyCycleJP923, and _DataRange::value.

Referenced by LORAREG_EnableallChannels(), and LORAReg_InitJP().

void InitDefault920ChannelsKR ( void  )

References _RegParamsType2::channelTimer, _RegParams::cmnParams, _channelParams::dataRange, DISABLED, i, _OthChannelParams::joinRequestChannel, _RegParams::lastUsedChannelIndex, _RegParams::maxChannels, _TxParams::maxEIRP, _CmnParams::paramsType2, _RegParams::pChParams, _RegParams::pOtherChParams, RegParams, _channelParams::status, _RegParamsType2::txParams, and _DataRange::value.

Referenced by LORAREG_EnableallChannels(), and LORAReg_InitKR().

void InitDefault923Channels ( void  )

References _RegParams::cmnParams, _channelParams::dataRange, i, _RegParams::maxChannels, _CmnParams::paramsType2, _RegParams::pChParams, _RegParams::pOtherChParams, _RegParams::pSubBandParams, RegParams, _RegParamsType2::subBandDutyCycle, SubBandDutyCycle923, and _DataRange::value.

Referenced by LORAREG_EnableallChannels(), and LORAReg_InitAS().

StackRetStatus_t InValidAttr ( LorawanRegionalAttributes_t  attr,
void *  attrInput 
)

References LORAWAN_INVALID_REQUEST.

Referenced by LORAREG_Init().

StackRetStatus_t InValidGetAttr ( LorawanRegionalAttributes_t  attr,
void *  attrInput,
void *  attrOutput 
)

References LORAWAN_INVALID_REQUEST.

Referenced by LORAREG_Init().

void JoinBackoffCallback ( uint8_t  param)

References BACKOFF_BASE_TIME_IN_MS, JoinBackoffCallback(), _RegParams::joinbccount, MS_TO_US, NULL, _RegParams::pJoinBackoffTimer, SW_TIMEOUT_RELATIVE, SwTimerStart(), and _JoinBackoffTimer::timerId.

Referenced by JoinBackoffCallback(), and setJoinBackOffTimer().

StackRetStatus_t LORAReg_InitAS ( IsmBand_t  ismBand)

References aRegAsPdsOps, _RegParams::band, _RegPdsItems::band_item_id, _RegPdsItems::ch_param_1_item_id, _RegPdsItems::ch_param_2_item_id, _RegParamsType2::chParams, _RegParams::cmnParams, DEFAULT_EIRP_AS, _RegParams::DefRx1DataRate, _RegParams::DefRx2DataRate, _RegParams::DefRx2Freq, _RegParams::defTxPwrIndx, _TxParams::downlinkDwellTime, _RegParamsType2::DRParams, _RegParamsType2::DutyCycleTimer, _RegParams::FeaturesSupport, _PdsFileMarks::fIDcb, _RegPdsItems::fileid, _PdsFileMarks::fileMarkListAddr, InitDefault923Channels(), ISM_BRN923, ISM_VTM923, _PdsFileMarks::itemListAddr, _RegParams::joinBackoffTimer, _RegParams::joinbccount, _RegParams::joinDutyCycleTimeout, _RegParams::joinDutyCycleTimer, _RegPdsItems::lastUsedSB, LORAREG_InitGetAttrFnPtrsAS(), LORAREG_InitSetAttrFnPtrsAS(), LORAREG_InitValidateAttrFnPtrsAS(), LORAWAN_INVALID_PARAMETER, LORAWAN_SUCCESS, LorawanReg_AS_Pds_Cb(), MAC_RX1_WINDOW_DATARATE_AS, MAC_RX2_WINDOW_DATARATE_AS, MAC_RX2_WINDOW_FREQ_AS, _RegParams::MacTxPower, MAX_CHANNELS_AS, MAX_NUM_SUBBANDS_AS, MAX_TX_PWR_INDEX_AS, _RegParams::maxChannels, _RegParams::maxDataRate, _TxParams::maxEIRP, _RegParams::maxSubBands, _RegParams::maxTxPwr, _RegParams::maxTxPwrIndx, _RegParams::minDataRate, _RegParams::MinNewChIndex, _RegParamsType2::minNonDefChId, NEW_CHANNEL_INDEX_AS, _PdsFileMarks::numItems, _RegParamsType2::othChParams, _CmnParams::paramsType2, _RegParams::pChParams, _RegParams::pDrParams, PDS_FILE_REG_AS_05_IDX, PDS_REG_AS_BAND, PDS_REG_AS_CH_PARAM_1, PDS_REG_AS_CH_PARAM_2, PDS_REG_AS_MAX_VALUE, PDS_RegFile(), PDS_STORE, _RegParams::pDutyCycleTimer, _RegParams::pJoinBackoffTimer, _RegParams::pJoinDutyCycleTimer, _RegParams::pOtherChParams, _RegParams::pSubBandParams, _RegParams::regParamItems, RegParams, regTimerId, _JoinDutyCycleTimer::remainingtime, result, _RegParams::Rx1DrOffset, _RegParamsType2::SubBands, _DutyCycleTimer::timerId, _JoinDutyCycleTimer::timerId, _JoinBackoffTimer::timerId, _RegParams::TxCurDataRate, _RegParamsType2::txParams, UNSUPPORTED_BAND, and _TxParams::uplinkDwellTime.

Referenced by LORAREG_Init().

StackRetStatus_t LORAReg_InitAU ( IsmBand_t  ismBand)

References _RegParamsType1::alternativeChannel, aRegAuPdsOps, _RegParams::band, _RegPdsItems::band_item_id, _RegPdsItems::ch_param_1_item_id, _RegPdsItems::ch_param_2_item_id, _RegParamsType1::chParams, _RegParams::cmnParams, DEFAULT_EIRP_AU, _RegParams::DefRx1DataRate, _RegParams::DefRx2DataRate, _RegParams::DefRx2Freq, _RegParams::defTxPwrIndx, DOWNSTREAM_CH0_AU, _RegParamsType1::DownStreamCh0Freq, DR0, DR13, DR6, DR8, _RegParamsType1::DRParams, _RegParams::FeaturesSupport, _PdsFileMarks::fIDcb, _RegPdsItems::fileid, _PdsFileMarks::fileMarkListAddr, InitDefault915ChannelsAU(), _PdsFileMarks::itemListAddr, _RegParams::joinBackoffTimer, _RegParams::joinbccount, _RegParams::joinDutyCycleTimeout, _RegParams::joinDutyCycleTimer, _RegPdsItems::lastUsedSB, _RegParamsType1::lastUsedSB, LORAREG_InitGetAttrFnPtrsAU(), LORAREG_InitSetAttrFnPtrsAU(), LORAREG_InitValidateAttrFnPtrsAU(), LORAWAN_SUCCESS, LorawanReg_AU_Pds_Cb(), MAC_RX1_WINDOW_DATARATE_AU, MAC_RX2_WINDOW_DATARATE_AU, MAC_RX2_WINDOW_FREQ_AU, _RegParams::MacTxPower, _RegParamsType1::Max_125khzChan, _RegParamsType1::Max_500khzChan, MAX_CHANNELS_AU_NA, MAX_CHANNELS_BANDWIDTH_125_AU_NA, MAX_CHANNELS_BANDWIDTH_500_AU_NA, _RegParams::maxChannels, _RegParams::maxDataRate, _RegParamsType1::maxRxDR, _RegParamsType1::maxTxDR, _RegParams::maxTxPwr, _RegParams::maxTxPwrIndx, _RegParams::minDataRate, _RegParams::MinNewChIndex, _RegParamsType1::minRxDR, _RegParamsType1::minTxDR, _PdsFileMarks::numItems, _CmnParams::paramsType1, _RegParams::pChParams, _RegParams::pDrParams, PDS_FILE_REG_AU_09_IDX, PDS_REG_AU_CH_PARAM, PDS_REG_AU_LAST_USED_SB, PDS_REG_AU_MAX_VALUE, PDS_RegFile(), _RegParams::pJoinBackoffTimer, _RegParams::pJoinDutyCycleTimer, _RegParams::regParamItems, RegParams, regTimerId, _JoinDutyCycleTimer::remainingtime, result, _RegParams::Rx1DrOffset, _RegParamsType1::RxParamWindowOffset1, _JoinDutyCycleTimer::timerId, _JoinBackoffTimer::timerId, _RegParams::TxCurDataRate, UNSUPPORTED_BAND, UPSTREAM_CH0_AU, UPSTREAM_CH64_AU, _RegParamsType1::UpStreamCh0Freq, and _RegParamsType1::UpStreamCh64Freq.

Referenced by LORAREG_Init().

StackRetStatus_t LORAReg_InitEU ( IsmBand_t  ismBand)

References aRegEu868Fid1PdsOps, aRegEu868Fid2PdsOps, _RegParams::band, _RegPdsItems::band_item_id, _RegPdsItems::ch_param_1_item_id, _RegPdsItems::ch_param_2_item_id, _RegParamsType2::chParams, _RegParams::cmnParams, DEFAULT_EIRP_EU, _RegParams::DefRx1DataRate, _RegParams::DefRx2DataRate, _RegParams::DefRx2Freq, _RegParams::defTxPwrIndx, _RegParamsType2::DRParams, _RegParamsType2::DutyCycleTimer, _RegParams::FeaturesSupport, _PdsFileMarks::fIDcb, _RegPdsItems::fileid, _PdsFileMarks::fileMarkListAddr, InitDefault433Channels(), InitDefault868Channels(), ISM_EU433, ISM_EU868, _PdsFileMarks::itemListAddr, _RegParams::joinBackoffTimer, _RegParams::joinbccount, _RegParams::joinDutyCycleTimeout, _RegParams::joinDutyCycleTimer, _RegPdsItems::lastUsedSB, LORAREG_InitGetAttrFnPtrsEU(), LORAREG_InitSetAttrFnPtrsEU(), LORAREG_InitValidateAttrFnPtrsEU(), LORAWAN_SUCCESS, LorawanReg_EU868_Pds_Cb(), MAC_433_RX1_WINDOW_DATARATE, MAC_433_RX2_WINDOW_DATARATE, MAC_433_RX2_WINDOW_FREQ, MAC_868_RX1_WINDOW_DATARATE, MAC_868_RX2_WINDOW_DATARATE, MAC_868_RX2_WINDOW_FREQ, _RegParams::MacTxPower, MAX_CHANNELS_T2, MAX_NUM_SUBBANDS_EU, _RegParams::maxChannels, _RegParams::maxDataRate, _RegParams::maxSubBands, _RegParams::maxTxPwr, _RegParams::maxTxPwrIndx, _RegParams::minDataRate, _RegParams::MinNewChIndex, _RegParamsType2::minNonDefChId, _PdsFileMarks::numItems, _RegParamsType2::othChParams, _CmnParams::paramsType2, _RegParams::pChParams, _RegParams::pDrParams, PDS_FILE_REG_EU868_04_IDX, PDS_FILE_REG_EU868_12_IDX, PDS_REG_EU868_CH_PARAM_1, PDS_REG_EU868_CH_PARAM_2, PDS_REG_EU868_FID1_MAX_VALUE, PDS_REG_EU868_FID2_MAX_VALUE, PDS_RegFile(), _RegParams::pDutyCycleTimer, _RegParams::pJoinBackoffTimer, _RegParams::pJoinDutyCycleTimer, _RegParams::pOtherChParams, _RegParams::pSubBandParams, _RegParams::regParamItems, RegParams, regTimerId, _JoinDutyCycleTimer::remainingtime, _RegParams::Rx1DrOffset, _RegParamsType2::SubBands, _DutyCycleTimer::timerId, _JoinDutyCycleTimer::timerId, _JoinBackoffTimer::timerId, _RegParams::TxCurDataRate, and UNSUPPORTED_BAND.

Referenced by LORAREG_Init().

void LORAREG_InitGetAttrFnPtrsAS ( void  )

References BANDWIDTH_ATTR, CHANNEL_ID_STATUS, CURRENT_CHANNEL_INDEX, DATA_RANGE, DATA_RANGE_CH_BAND, DEF_TX_PWR, DEFAULT_RX1_DATA_RATE, DEFAULT_RX2_DATA_RATE, DEFAULT_RX2_FREQUENCY, DL_FREQUENCY, DUTY_CYCLE, FREE_CHANNEL, FREQUENCY, JOIN_DUTY_CYCLE_TIMER, LORAREG_GetAttr_BandwidthAttrT2(), LORAREG_GetAttr_ChIdStatus(), LORAREG_GetAttr_CurChIndx(), LORAREG_GetAttr_DataRange(), LORAREG_GetAttr_DefRx1DataRate(), LORAREG_GetAttr_DefRx2DataRate(), LORAREG_GetAttr_DefRx2Freq(), LORAREG_GetAttr_DefTxPwr(), LORAREG_GetAttr_DlFrequency(), LORAREG_GetAttr_DRangeChBandT2(), LORAREG_GetAttr_DutyCycleT2(), LORAREG_GetAttr_DutyCycleTimer(), LORAREG_GetAttr_FreeChannel2(), LORAREG_GetAttr_FreqT3(), LORAREG_GetAttr_JoinDutyCycleRemainingTime(), LORAREG_GetAttr_MacAdrAckDelay(), LORAREG_GetAttr_MacAdrAckLimit(), LORAREG_GetAttr_MacJoinAcptDelay1(), LORAREG_GetAttr_MacJoinAcptDelay2(), LORAREG_GetAttr_MacRecvDelay1(), LORAREG_GetAttr_MacRecvDelay2(), LORAREG_GetAttr_MacRetransmitTimeout(), LORAREG_GetAttr_MaxChannel(), LORAREG_GetAttr_MaxPayloadT3(), LORAREG_GetAttr_MinMaxDr(), LORAREG_GetAttr_MinNewChIndex(), LORAREG_GetAttr_ModulationAttrT2(), LORAREG_GetAttr_NewTxChConfigT2(), LORAREG_GetAttr_RegDefTxDR(), LORAREG_GetAttr_RegDefTxPwr(), LORAREG_GetAttr_RegFeatures(), LORAREG_GetAttr_Rx1WindowparamsType4(), LORAREG_GetAttr_RxWindowOffsetT2(), LORAREG_GetAttr_RxWindowSizeT2(), LORAREG_GetAttr_SpreadFactorT2(), MAC_ADR_ACK_DELAY, MAC_ADR_ACK_LIMIT, MAC_JOIN_ACCEPT_DELAY1, MAC_JOIN_ACCEPT_DELAY2, MAC_RECEIVE_DELAY1, MAC_RECEIVE_DELAY2, MAC_RETRANSMIT_TIMEOUT, MAX_CHANNELS, MAX_PAYLOAD_SIZE, MIN_DUTY_CYCLE_TIMER, MIN_MAX_DR, MIN_NEW_CH_INDEX, MODULATION_ATTR, NEW_TX_CHANNEL_CONFIG, pGetAttr, REG_DEF_TX_DATARATE, REG_DEF_TX_POWER, RX1_WINDOW_PARAMS, RX_WINDOW_OFFSET, RX_WINDOW_SIZE, SPREADING_FACTOR_ATTR, and SUPPORTED_REGIONAL_FEATURES.

Referenced by LORAReg_InitAS().

void LORAREG_InitGetAttrFnPtrsAU ( void  )

References BANDWIDTH_ATTR, CHANNEL_ID_STATUS, CURRENT_CHANNEL_INDEX, DATA_RANGE, DATA_RANGE_CH_BAND, DEF_TX_PWR, DEFAULT_RX1_DATA_RATE, DEFAULT_RX2_DATA_RATE, DEFAULT_RX2_FREQUENCY, DUTY_CYCLE, DUTY_CYCLE_TIMER, FREE_CHANNEL, FREQUENCY, JOIN_DUTY_CYCLE_TIMER, LORAREG_GetAttr_BandwidthAttrT1(), LORAREG_GetAttr_ChIdStatus(), LORAREG_GetAttr_CurChIndx(), LORAREG_GetAttr_DataRange(), LORAREG_GetAttr_DefRx1DataRate(), LORAREG_GetAttr_DefRx2DataRate(), LORAREG_GetAttr_DefRx2Freq(), LORAREG_GetAttr_DefTxPwr(), LORAREG_GetAttr_DRangeChBandT1(), LORAREG_GetAttr_DutyCycleT1(), LORAREG_GetAttr_FreeChannel1(), LORAREG_GetAttr_FreqT1(), LORAREG_GetAttr_JoinDutyCycleRemainingTime(), LORAREG_GetAttr_MacAdrAckDelay(), LORAREG_GetAttr_MacAdrAckLimit(), LORAREG_GetAttr_MacJoinAcptDelay1(), LORAREG_GetAttr_MacJoinAcptDelay2(), LORAREG_GetAttr_MacRecvDelay1(), LORAREG_GetAttr_MacRecvDelay2(), LORAREG_GetAttr_MacRetransmitTimeout(), LORAREG_GetAttr_MaxChannel(), LORAREG_GetAttr_MaxPayloadT1(), LORAREG_GetAttr_MinDutyCycleTimer(), LORAREG_GetAttr_MinMaxDr(), LORAREG_GetAttr_MinNewChIndex(), LORAREG_GetAttr_ModulationAttrT1(), LORAREG_GetAttr_NewTxChConfigT1(), LORAREG_GetAttr_RegDefTxDR(), LORAREG_GetAttr_RegDefTxPwr(), LORAREG_GetAttr_RegFeatures(), LORAREG_GetAttr_Rx1WindowparamsType1(), LORAREG_GetAttr_RxWindowOffsetT1(), LORAREG_GetAttr_RxWindowSizeT1(), LORAREG_GetAttr_SpreadFactorT1(), MAC_ADR_ACK_DELAY, MAC_ADR_ACK_LIMIT, MAC_JOIN_ACCEPT_DELAY1, MAC_JOIN_ACCEPT_DELAY2, MAC_RECEIVE_DELAY1, MAC_RECEIVE_DELAY2, MAC_RETRANSMIT_TIMEOUT, MAX_CHANNELS, MAX_PAYLOAD_SIZE, MIN_MAX_DR, MIN_NEW_CH_INDEX, MODULATION_ATTR, NEW_TX_CHANNEL_CONFIG, pGetAttr, REG_DEF_TX_DATARATE, REG_DEF_TX_POWER, RX1_WINDOW_PARAMS, RX_WINDOW_OFFSET, RX_WINDOW_SIZE, SPREADING_FACTOR_ATTR, and SUPPORTED_REGIONAL_FEATURES.

Referenced by LORAReg_InitAU().

void LORAREG_InitGetAttrFnPtrsEU ( void  )

References BANDWIDTH_ATTR, CHANNEL_ID_STATUS, CURRENT_CHANNEL_INDEX, DATA_RANGE, DATA_RANGE_CH_BAND, DEF_TX_PWR, DEFAULT_RX1_DATA_RATE, DEFAULT_RX2_DATA_RATE, DEFAULT_RX2_FREQUENCY, DL_FREQUENCY, DUTY_CYCLE, FREE_CHANNEL, FREQUENCY, JOIN_DUTY_CYCLE_TIMER, LORAREG_GetAttr_BandwidthAttrT2(), LORAREG_GetAttr_ChIdStatus(), LORAREG_GetAttr_CurChIndx(), LORAREG_GetAttr_DataRange(), LORAREG_GetAttr_DefRx1DataRate(), LORAREG_GetAttr_DefRx2DataRate(), LORAREG_GetAttr_DefRx2Freq(), LORAREG_GetAttr_DefTxPwr(), LORAREG_GetAttr_DlFrequency(), LORAREG_GetAttr_DRangeChBandT2(), LORAREG_GetAttr_DutyCycleT2(), LORAREG_GetAttr_DutyCycleTimer(), LORAREG_GetAttr_FreeChannel2(), LORAREG_GetAttr_FreqT2(), LORAREG_GetAttr_JoinDutyCycleRemainingTime(), LORAREG_GetAttr_MacAdrAckDelay(), LORAREG_GetAttr_MacAdrAckLimit(), LORAREG_GetAttr_MacJoinAcptDelay1(), LORAREG_GetAttr_MacJoinAcptDelay2(), LORAREG_GetAttr_MacRecvDelay1(), LORAREG_GetAttr_MacRecvDelay2(), LORAREG_GetAttr_MacRetransmitTimeout(), LORAREG_GetAttr_MaxChannel(), LORAREG_GetAttr_MaxPayloadT2(), LORAREG_GetAttr_MinMaxDr(), LORAREG_GetAttr_MinNewChIndex(), LORAREG_GetAttr_ModulationAttrT2(), LORAREG_GetAttr_NewTxChConfigT2(), LORAREG_GetAttr_RegDefTxDR(), LORAREG_GetAttr_RegDefTxPwr(), LORAREG_GetAttr_RegFeatures(), LORAREG_GetAttr_Rx1WindowparamsType2(), LORAREG_GetAttr_RxWindowOffsetT2(), LORAREG_GetAttr_RxWindowSizeT2(), LORAREG_GetAttr_SpreadFactorT2(), MAC_ADR_ACK_DELAY, MAC_ADR_ACK_LIMIT, MAC_JOIN_ACCEPT_DELAY1, MAC_JOIN_ACCEPT_DELAY2, MAC_RECEIVE_DELAY1, MAC_RECEIVE_DELAY2, MAC_RETRANSMIT_TIMEOUT, MAX_CHANNELS, MAX_PAYLOAD_SIZE, MIN_DUTY_CYCLE_TIMER, MIN_MAX_DR, MIN_NEW_CH_INDEX, MODULATION_ATTR, NEW_TX_CHANNEL_CONFIG, pGetAttr, REG_DEF_TX_DATARATE, REG_DEF_TX_POWER, RX1_WINDOW_PARAMS, RX_WINDOW_OFFSET, RX_WINDOW_SIZE, SPREADING_FACTOR_ATTR, and SUPPORTED_REGIONAL_FEATURES.

Referenced by LORAReg_InitEU().

void LORAREG_InitGetAttrFnPtrsIN ( void  )

References BANDWIDTH_ATTR, CHANNEL_ID_STATUS, CURRENT_CHANNEL_INDEX, DATA_RANGE, DATA_RANGE_CH_BAND, DEF_TX_PWR, DEFAULT_RX1_DATA_RATE, DEFAULT_RX2_DATA_RATE, DEFAULT_RX2_FREQUENCY, DL_FREQUENCY, FREE_CHANNEL, FREQUENCY, JOIN_DUTY_CYCLE_TIMER, LORAREG_GetAttr_BandwidthAttrT2(), LORAREG_GetAttr_ChIdStatus(), LORAREG_GetAttr_CurChIndx(), LORAREG_GetAttr_DataRange(), LORAREG_GetAttr_DefRx1DataRate(), LORAREG_GetAttr_DefRx2DataRate(), LORAREG_GetAttr_DefRx2Freq(), LORAREG_GetAttr_DefTxPwr(), LORAREG_GetAttr_DlFrequency(), LORAREG_GetAttr_DRangeChBandT2(), LORAREG_GetAttr_FreeChannel2(), LORAREG_GetAttr_FreqT2(), LORAREG_GetAttr_JoinDutyCycleRemainingTime(), LORAREG_GetAttr_MacAdrAckDelay(), LORAREG_GetAttr_MacAdrAckLimit(), LORAREG_GetAttr_MacJoinAcptDelay1(), LORAREG_GetAttr_MacJoinAcptDelay2(), LORAREG_GetAttr_MacRecvDelay1(), LORAREG_GetAttr_MacRecvDelay2(), LORAREG_GetAttr_MacRetransmitTimeout(), LORAREG_GetAttr_MaxChannel(), LORAREG_GetAttr_MaxPayloadT2(), LORAREG_GetAttr_MinMaxDr(), LORAREG_GetAttr_MinNewChIndex(), LORAREG_GetAttr_ModulationAttrT2(), LORAREG_GetAttr_NewTxChConfigT2(), LORAREG_GetAttr_RegDefTxDR(), LORAREG_GetAttr_RegDefTxPwr(), LORAREG_GetAttr_RegFeatures(), LORAREG_GetAttr_Rx1WindowparamsType3(), LORAREG_GetAttr_RxWindowOffsetT2(), LORAREG_GetAttr_RxWindowSizeT2(), LORAREG_GetAttr_SpreadFactorT2(), MAC_ADR_ACK_DELAY, MAC_ADR_ACK_LIMIT, MAC_JOIN_ACCEPT_DELAY1, MAC_JOIN_ACCEPT_DELAY2, MAC_RECEIVE_DELAY1, MAC_RECEIVE_DELAY2, MAC_RETRANSMIT_TIMEOUT, MAX_CHANNELS, MAX_PAYLOAD_SIZE, MIN_MAX_DR, MIN_NEW_CH_INDEX, MODULATION_ATTR, NEW_TX_CHANNEL_CONFIG, pGetAttr, REG_DEF_TX_DATARATE, REG_DEF_TX_POWER, RX1_WINDOW_PARAMS, RX_WINDOW_OFFSET, RX_WINDOW_SIZE, SPREADING_FACTOR_ATTR, and SUPPORTED_REGIONAL_FEATURES.

Referenced by LORAReg_InitIN().

void LORAREG_InitGetAttrFnPtrsJP ( void  )

References BANDWIDTH_ATTR, CHANNEL_ID_STATUS, CURRENT_CHANNEL_INDEX, DATA_RANGE, DATA_RANGE_CH_BAND, DEF_TX_PWR, DEFAULT_LBT_PARAMS, DEFAULT_RX1_DATA_RATE, DEFAULT_RX2_DATA_RATE, DEFAULT_RX2_FREQUENCY, DL_FREQUENCY, DUTY_CYCLE, FREE_CHANNEL, FREQUENCY, JOIN_DUTY_CYCLE_TIMER, LORAREG_GetAttr_BandwidthAttrT2(), LORAREG_GetAttr_ChIdStatus(), LORAREG_GetAttr_CurChIndx(), LORAREG_GetAttr_DataRange(), LORAREG_GetAttr_DefLBTParams(), LORAREG_GetAttr_DefRx1DataRate(), LORAREG_GetAttr_DefRx2DataRate(), LORAREG_GetAttr_DefRx2Freq(), LORAREG_GetAttr_DefTxPwr(), LORAREG_GetAttr_DlFrequency(), LORAREG_GetAttr_DRangeChBandT2(), LORAREG_GetAttr_DutyCycleT2(), LORAREG_GetAttr_DutyCycleTimer(), LORAREG_GetAttr_FreeChannel2(), LORAREG_GetAttr_FreqT3(), LORAREG_GetAttr_JoinDutyCycleRemainingTime(), LORAREG_GetAttr_MacAdrAckDelay(), LORAREG_GetAttr_MacAdrAckLimit(), LORAREG_GetAttr_MacJoinAcptDelay1(), LORAREG_GetAttr_MacJoinAcptDelay2(), LORAREG_GetAttr_MacRecvDelay1(), LORAREG_GetAttr_MacRecvDelay2(), LORAREG_GetAttr_MacRetransmitTimeout(), LORAREG_GetAttr_MaxChannel(), LORAREG_GetAttr_MaxPayloadT3(), LORAREG_GetAttr_minLBTChPauseTimer(), LORAREG_GetAttr_MinMaxDr(), LORAREG_GetAttr_MinNewChIndex(), LORAREG_GetAttr_ModulationAttrT2(), LORAREG_GetAttr_NewTxChConfigT2(), LORAREG_GetAttr_RegDefTxDR(), LORAREG_GetAttr_RegDefTxPwr(), LORAREG_GetAttr_RegFeatures(), LORAREG_GetAttr_Rx1WindowparamsType4(), LORAREG_GetAttr_RxWindowOffsetT2(), LORAREG_GetAttr_RxWindowSizeT2(), LORAREG_GetAttr_SpreadFactorT2(), MAC_ADR_ACK_DELAY, MAC_ADR_ACK_LIMIT, MAC_JOIN_ACCEPT_DELAY1, MAC_JOIN_ACCEPT_DELAY2, MAC_RECEIVE_DELAY1, MAC_RECEIVE_DELAY2, MAC_RETRANSMIT_TIMEOUT, MAX_CHANNELS, MAX_PAYLOAD_SIZE, MIN_DUTY_CYCLE_TIMER, MIN_LBT_CHANNEL_PAUSE_TIMER, MIN_MAX_DR, MIN_NEW_CH_INDEX, MODULATION_ATTR, NEW_TX_CHANNEL_CONFIG, pGetAttr, REG_DEF_TX_DATARATE, REG_DEF_TX_POWER, RX1_WINDOW_PARAMS, RX_WINDOW_OFFSET, RX_WINDOW_SIZE, SPREADING_FACTOR_ATTR, and SUPPORTED_REGIONAL_FEATURES.

Referenced by LORAReg_InitJP().

void LORAREG_InitGetAttrFnPtrsKR ( void  )

References BANDWIDTH_ATTR, CHANNEL_ID_STATUS, CURRENT_CHANNEL_INDEX, DATA_RANGE, DATA_RANGE_CH_BAND, DEF_TX_PWR, DEFAULT_LBT_PARAMS, DEFAULT_RX1_DATA_RATE, DEFAULT_RX2_DATA_RATE, DEFAULT_RX2_FREQUENCY, DL_FREQUENCY, FREE_CHANNEL, FREQUENCY, JOIN_DUTY_CYCLE_TIMER, LORAREG_GetAttr_BandwidthAttrT2(), LORAREG_GetAttr_ChIdStatus(), LORAREG_GetAttr_CurChIndx(), LORAREG_GetAttr_DataRange(), LORAREG_GetAttr_DefLBTParams(), LORAREG_GetAttr_DefRx1DataRate(), LORAREG_GetAttr_DefRx2DataRate(), LORAREG_GetAttr_DefRx2Freq(), LORAREG_GetAttr_DefTxPwr(), LORAREG_GetAttr_DlFrequency(), LORAREG_GetAttr_DRangeChBandT2(), LORAREG_GetAttr_FreeChannel2(), LORAREG_GetAttr_FreqT2(), LORAREG_GetAttr_JoinDutyCycleRemainingTime(), LORAREG_GetAttr_MacAdrAckDelay(), LORAREG_GetAttr_MacAdrAckLimit(), LORAREG_GetAttr_MacJoinAcptDelay1(), LORAREG_GetAttr_MacJoinAcptDelay2(), LORAREG_GetAttr_MacRecvDelay1(), LORAREG_GetAttr_MacRecvDelay2(), LORAREG_GetAttr_MacRetransmitTimeout(), LORAREG_GetAttr_MaxChannel(), LORAREG_GetAttr_MaxPayloadT2(), LORAREG_GetAttr_minLBTChPauseTimer(), LORAREG_GetAttr_MinMaxDr(), LORAREG_GetAttr_MinNewChIndex(), LORAREG_GetAttr_ModulationAttrT2(), LORAREG_GetAttr_NewTxChConfigT2(), LORAREG_GetAttr_RegDefTxDR(), LORAREG_GetAttr_RegDefTxPwr(), LORAREG_GetAttr_RegFeatures(), LORAREG_GetAttr_Rx1WindowparamsType2(), LORAREG_GetAttr_RxWindowOffsetT2(), LORAREG_GetAttr_RxWindowSizeT2(), LORAREG_GetAttr_SpreadFactorT2(), MAC_ADR_ACK_DELAY, MAC_ADR_ACK_LIMIT, MAC_JOIN_ACCEPT_DELAY1, MAC_JOIN_ACCEPT_DELAY2, MAC_RECEIVE_DELAY1, MAC_RECEIVE_DELAY2, MAC_RETRANSMIT_TIMEOUT, MAX_CHANNELS, MAX_PAYLOAD_SIZE, MIN_LBT_CHANNEL_PAUSE_TIMER, MIN_MAX_DR, MIN_NEW_CH_INDEX, MODULATION_ATTR, NEW_TX_CHANNEL_CONFIG, pGetAttr, REG_DEF_TX_DATARATE, REG_DEF_TX_POWER, RX1_WINDOW_PARAMS, RX_WINDOW_OFFSET, RX_WINDOW_SIZE, SPREADING_FACTOR_ATTR, and SUPPORTED_REGIONAL_FEATURES.

Referenced by LORAReg_InitKR().

void LORAREG_InitGetAttrFnPtrsNA ( void  )

References BANDWIDTH_ATTR, CHANNEL_ID_STATUS, CURRENT_CHANNEL_INDEX, DATA_RANGE, DATA_RANGE_CH_BAND, DEF_TX_PWR, DEFAULT_RX1_DATA_RATE, DEFAULT_RX2_DATA_RATE, DEFAULT_RX2_FREQUENCY, DUTY_CYCLE, FREE_CHANNEL, FREQUENCY, JOIN_DUTY_CYCLE_TIMER, LORAREG_GetAttr_BandwidthAttrT1(), LORAREG_GetAttr_ChIdStatus(), LORAREG_GetAttr_CurChIndx(), LORAREG_GetAttr_DataRange(), LORAREG_GetAttr_DefRx1DataRate(), LORAREG_GetAttr_DefRx2DataRate(), LORAREG_GetAttr_DefRx2Freq(), LORAREG_GetAttr_DefTxPwr(), LORAREG_GetAttr_DRangeChBandT1(), LORAREG_GetAttr_DutyCycleT1(), LORAREG_GetAttr_FreeChannel1(), LORAREG_GetAttr_FreqT1(), LORAREG_GetAttr_JoinDutyCycleRemainingTime(), LORAREG_GetAttr_MacAdrAckDelay(), LORAREG_GetAttr_MacAdrAckLimit(), LORAREG_GetAttr_MacJoinAcptDelay1(), LORAREG_GetAttr_MacJoinAcptDelay2(), LORAREG_GetAttr_MacRecvDelay1(), LORAREG_GetAttr_MacRecvDelay2(), LORAREG_GetAttr_MacRetransmitTimeout(), LORAREG_GetAttr_MaxChannel(), LORAREG_GetAttr_MaxPayloadT1(), LORAREG_GetAttr_MinDutyCycleTimer(), LORAREG_GetAttr_MinMaxDr(), LORAREG_GetAttr_MinNewChIndex(), LORAREG_GetAttr_ModulationAttrT1(), LORAREG_GetAttr_NewTxChConfigT1(), LORAREG_GetAttr_RegDefTxDR(), LORAREG_GetAttr_RegDefTxPwr(), LORAREG_GetAttr_RegFeatures(), LORAREG_GetAttr_Rx1WindowparamsType1(), LORAREG_GetAttr_RxWindowOffsetT1(), LORAREG_GetAttr_RxWindowSizeT1(), LORAREG_GetAttr_SpreadFactorT1(), MAC_ADR_ACK_DELAY, MAC_ADR_ACK_LIMIT, MAC_JOIN_ACCEPT_DELAY1, MAC_JOIN_ACCEPT_DELAY2, MAC_RECEIVE_DELAY1, MAC_RECEIVE_DELAY2, MAC_RETRANSMIT_TIMEOUT, MAX_CHANNELS, MAX_PAYLOAD_SIZE, MIN_DUTY_CYCLE_TIMER, MIN_MAX_DR, MIN_NEW_CH_INDEX, MODULATION_ATTR, NEW_TX_CHANNEL_CONFIG, pGetAttr, REG_DEF_TX_DATARATE, REG_DEF_TX_POWER, RX1_WINDOW_PARAMS, RX_WINDOW_OFFSET, RX_WINDOW_SIZE, SPREADING_FACTOR_ATTR, and SUPPORTED_REGIONAL_FEATURES.

Referenced by LORAReg_InitNA().

StackRetStatus_t LORAReg_InitIN ( IsmBand_t  ismBand)

References aRegIndPdsOps, _RegParams::band, _RegPdsItems::band_item_id, _RegPdsItems::ch_param_1_item_id, _RegPdsItems::ch_param_2_item_id, _RegParamsType2::chParams, _RegParams::cmnParams, DEFAULT_EIRP_IN, _RegParams::DefRx1DataRate, _RegParams::DefRx2DataRate, _RegParams::DefRx2Freq, _RegParams::defTxPwrIndx, _RegParamsType2::DRParams, _RegParamsType2::DutyCycleTimer, _RegParams::FeaturesSupport, _PdsFileMarks::fIDcb, _RegPdsItems::fileid, _PdsFileMarks::fileMarkListAddr, InitDefault865Channels(), ISM_IND865, _PdsFileMarks::itemListAddr, _RegParams::joinBackoffTimer, _RegParams::joinbccount, _RegParams::joinDutyCycleTimeout, _RegParams::joinDutyCycleTimer, _RegPdsItems::lastUsedSB, LORAREG_InitGetAttrFnPtrsIN(), LORAREG_InitSetAttrFnPtrsIN(), LORAREG_InitValidateAttrFnPtrsIN(), LORAWAN_INVALID_PARAMETER, LORAWAN_SUCCESS, LorawanReg_IND_Pds_Cb(), MAC_RX1_WINDOW_DATARATE_IN, MAC_RX2_WINDOW_DATARATE_IN, MAC_RX2_WINDOW_FREQ_IN, _RegParams::MacTxPower, MAX_CHANNELS_IN, MAX_NUM_SUBBANDS_IN, _RegParams::maxChannels, _RegParams::maxDataRate, _TxParams::maxEIRP, _RegParams::maxSubBands, _RegParams::maxTxPwr, _RegParams::maxTxPwrIndx, MIN_CHANNEL_INDEX_IN, _RegParams::minDataRate, _RegParams::MinNewChIndex, _RegParamsType2::minNonDefChId, _PdsFileMarks::numItems, _RegParamsType2::othChParams, _CmnParams::paramsType2, _RegParams::pChParams, _RegParams::pDrParams, PDS_FILE_REG_IND_07_IDX, PDS_REG_IND_CH_PARAM_1, PDS_REG_IND_CH_PARAM_2, PDS_REG_IND_MAX_VALUE, PDS_RegFile(), _RegParams::pDutyCycleTimer, _RegParams::pJoinBackoffTimer, _RegParams::pJoinDutyCycleTimer, _RegParams::pOtherChParams, _RegParams::regParamItems, RegParams, regTimerId, _JoinDutyCycleTimer::remainingtime, result, _RegParams::Rx1DrOffset, _JoinDutyCycleTimer::timerId, _JoinBackoffTimer::timerId, _RegParams::TxCurDataRate, _RegParamsType2::txParams, and UNSUPPORTED_BAND.

Referenced by LORAREG_Init().

StackRetStatus_t LORAReg_InitJP ( IsmBand_t  ismBand)

References aRegJpnFid1PdsOps, _RegParams::band, _RegPdsItems::band_item_id, _RegPdsItems::ch_param_1_item_id, _RegPdsItems::ch_param_2_item_id, _RegParamsType2::chParams, _RegParams::cmnParams, DEFAULT_EIRP_JP, _RegParams::DefRx1DataRate, _RegParams::DefRx2DataRate, _RegParams::DefRx2Freq, _RegParams::defTxPwrIndx, _TxParams::downlinkDwellTime, _RegParamsType2::DRParams, _RegParamsType2::DutyCycleTimer, _RegParams::FeaturesSupport, _PdsFileMarks::fIDcb, _RegPdsItems::fileid, _PdsFileMarks::fileMarkListAddr, InitDefault920Channels(), ISM_JPN923, _PdsFileMarks::itemListAddr, _RegParams::joinBackoffTimer, _RegParams::joinbccount, _RegParams::joinDutyCycleTimeout, _RegParams::joinDutyCycleTimer, _RegPdsItems::lastUsedSB, _RegParamsType2::LBT_RSSISamplesCount, LBT_SCAN_PERIOD_JP, LBT_SIGNAL_THRESHOLD_JP, _RegParamsType2::LBTScanPeriod, _RegParamsType2::LBTSignalThreshold, _RegParamsType2::LBTTimer, LORAREG_InitGetAttrFnPtrsJP(), LORAREG_InitSetAttrFnPtrsJP(), LORAREG_InitValidateAttrFnPtrsJP(), LORAWAN_INVALID_PARAMETER, LORAWAN_SUCCESS, LorawanReg_JPN_Pds_Cb(), MAC_RX1_WINDOW_DATARATE_JP, MAC_RX2_WINDOW_DATARATE_JP, MAC_RX2_WINDOW_FREQ_JP, _RegParams::MacTxPower, MAX_CHANNELS_JP, MAX_NUM_SUBBANDS_JP, _RegParams::maxChannels, _RegParams::maxDataRate, _TxParams::maxEIRP, _RegParams::maxSubBands, _RegParams::maxTxPwr, _RegParams::maxTxPwrIndx, MIN_CHANNEL_INDEX_JP, _RegParams::minDataRate, _RegParams::MinNewChIndex, _RegParamsType2::minNonDefChId, _PdsFileMarks::numItems, _RegParamsType2::othChParams, _CmnParams::paramsType2, _RegParams::pChParams, _RegParams::pDrParams, PDS_FILE_REG_JPN_08_IDX, PDS_REG_JPN_CH_PARAM_1, PDS_REG_JPN_CH_PARAM_2, PDS_REG_JPN_FID1_MAX_VALUE, PDS_RegFile(), _RegParams::pDutyCycleTimer, _RegParams::pJoinBackoffTimer, _RegParams::pJoinDutyCycleTimer, _RegParams::pOtherChParams, _RegParams::pSubBandParams, _RegParams::regParamItems, RegParams, regTimerId, _JoinDutyCycleTimer::remainingtime, result, _RegParams::Rx1DrOffset, _RegParamsType2::SubBands, _DutyCycleTimer::timerId, _JoinDutyCycleTimer::timerId, _JoinBackoffTimer::timerId, _LBTTimer::timerId, _RegParams::TxCurDataRate, _RegParamsType2::txParams, UNSUPPORTED_BAND, and _TxParams::uplinkDwellTime.

Referenced by LORAREG_Init().

StackRetStatus_t LORAReg_InitKR ( IsmBand_t  ismBand)

References aRegKrFid1PdsOps, _RegParams::band, _RegPdsItems::band_item_id, _DRParams::bandwidth, BW_125KHZ, _RegPdsItems::ch_param_1_item_id, _RegPdsItems::ch_param_2_item_id, _RegParamsType2::chParams, _RegParams::cmnParams, DEFAULT_EIRP_KR_HF, _RegParams::DefRx1DataRate, _RegParams::DefRx2DataRate, _RegParams::DefRx2Freq, _RegParams::defTxPwrIndx, _RegParamsType2::DRParams, _RegParamsType2::DutyCycleTimer, _RegParams::FeaturesSupport, _PdsFileMarks::fIDcb, _RegPdsItems::fileid, _PdsFileMarks::fileMarkListAddr, InitDefault920ChannelsKR(), ISM_KR920, _PdsFileMarks::itemListAddr, _RegParams::joinBackoffTimer, _RegParams::joinbccount, _RegParams::joinDutyCycleTimeout, _RegParams::joinDutyCycleTimer, _RegPdsItems::lastUsedSB, _RegParamsType2::LBT_RSSISamplesCount, LBT_SCAN_PERIOD_KR, LBT_SIGNAL_THRESHOLD_KR, _RegParamsType2::LBTScanPeriod, _RegParamsType2::LBTSignalThreshold, _RegParamsType2::LBTTimer, LORAREG_InitGetAttrFnPtrsKR(), LORAREG_InitSetAttrFnPtrsKR(), LORAREG_InitValidateAttrFnPtrsKR(), LORAWAN_SUCCESS, LorawanReg_KR_Pds_Cb(), MAC_RX1_WINDOW_DATARATE_KR, MAC_RX2_WINDOW_DATARATE_KR, MAC_RX2_WINDOW_FREQ_KR, _RegParams::MacTxPower, MAX_CHANNELS_KR, MAX_NUM_SUBBANDS_KR, _RegParams::maxChannels, _RegParams::maxDataRate, _RegParams::maxSubBands, _RegParams::maxTxPwr, _RegParams::maxTxPwrIndx, MIN_CHANNEL_INDEX_KR, _RegParams::minDataRate, _RegParams::MinNewChIndex, _RegParamsType2::minNonDefChId, _DRParams::modulation, MODULATION_LORA, _PdsFileMarks::numItems, _RegParamsType2::othChParams, _CmnParams::paramsType2, _RegParams::pChParams, _RegParams::pDrParams, PDS_FILE_REG_KR_06_IDX, PDS_REG_KR_CH_PARAM_1, PDS_REG_KR_CH_PARAM_2, PDS_REG_KR_FID1_MAX_VALUE, PDS_RegFile(), _RegParams::pDutyCycleTimer, _RegParams::pJoinBackoffTimer, _RegParams::pJoinDutyCycleTimer, _RegParams::pOtherChParams, _RegParams::regParamItems, RegParams, regTimerId, _JoinDutyCycleTimer::remainingtime, result, _RegParams::Rx1DrOffset, _JoinDutyCycleTimer::timerId, _JoinBackoffTimer::timerId, _LBTTimer::timerId, _RegParams::TxCurDataRate, and UNSUPPORTED_BAND.

Referenced by LORAREG_Init().

StackRetStatus_t LORAReg_InitNA ( IsmBand_t  ismBand)

References _RegParamsType1::alternativeChannel, aRegNaPdsOps, _RegParams::band, _RegPdsItems::band_item_id, _RegPdsItems::ch_param_1_item_id, _RegPdsItems::ch_param_2_item_id, _RegParamsType1::chParams, _RegParams::cmnParams, DEFAULT_EIRP_NA, _RegParams::DefRx1DataRate, _RegParams::DefRx2DataRate, _RegParams::DefRx2Freq, _RegParams::defTxPwrIndx, DOWNSTREAM_CH0_NA, _RegParamsType1::DownStreamCh0Freq, DR0, DR13, DR4, DR8, _RegParamsType1::DRParams, _RegParams::FeaturesSupport, _PdsFileMarks::fIDcb, _RegPdsItems::fileid, _PdsFileMarks::fileMarkListAddr, InitDefault915Channels(), _PdsFileMarks::itemListAddr, _RegParams::joinBackoffTimer, _RegParams::joinbccount, _RegParams::joinDutyCycleTimeout, _RegParams::joinDutyCycleTimer, _RegPdsItems::lastUsedSB, _RegParamsType1::lastUsedSB, LORAREG_InitGetAttrFnPtrsNA(), LORAREG_InitSetAttrFnPtrsNA(), LORAREG_InitValidateAttrFnPtrsNA(), LORAWAN_SUCCESS, LorawanReg_NA_Pds_Cb(), MAC_RX1_WINDOW_DATARATE_NA, MAC_RX2_WINDOW_DATARATE_NA, MAC_RX2_WINDOW_FREQ_NA, _RegParams::MacTxPower, _RegParamsType1::Max_125khzChan, _RegParamsType1::Max_500khzChan, MAX_CHANNELS_BANDWIDTH_125_AU_NA, MAX_CHANNELS_BANDWIDTH_500_AU_NA, MAX_CHANNELS_T1, _RegParams::maxChannels, _RegParams::maxDataRate, _RegParamsType1::maxRxDR, _RegParamsType1::maxTxDR, _RegParams::maxTxPwr, _RegParams::maxTxPwrIndx, _RegParams::minDataRate, _RegParams::MinNewChIndex, _RegParamsType1::minRxDR, _RegParamsType1::minTxDR, _PdsFileMarks::numItems, _CmnParams::paramsType1, _RegParams::pChParams, _RegParams::pDrParams, PDS_FILE_REG_NA_03_IDX, PDS_REG_NA_CH_PARAM, PDS_REG_NA_LAST_USED_SB, PDS_REG_NA_MAX_VALUE, PDS_RegFile(), _RegParams::pJoinBackoffTimer, _RegParams::pJoinDutyCycleTimer, _RegParams::regParamItems, RegParams, regTimerId, _JoinDutyCycleTimer::remainingtime, result, _RegParams::Rx1DrOffset, _RegParamsType1::RxParamWindowOffset1, _JoinDutyCycleTimer::timerId, _JoinBackoffTimer::timerId, _RegParams::TxCurDataRate, UNSUPPORTED_BAND, UPSTREAM_CH0_NA, UPSTREAM_CH64_NA, _RegParamsType1::UpStreamCh0Freq, and _RegParamsType1::UpStreamCh64Freq.

Referenced by LORAREG_Init().

void LORAREG_InitSetAttrFnPtrsAS ( void  )

References CHANNEL_ID_STATUS, CHLIST_DEFAULTS, DATA_RANGE, DL_FREQUENCY, DUTY_CYCLE, DUTY_CYCLE_TIMER, FREQUENCY, JOIN_BACK_OFF_TIMER, JOIN_DUTY_CYCLE_TIMER, JOINBACKOFF_CNTL, NEW_CHANNELS, pSetAttr, setChannelIdStatusT3(), setChlistDefaultState(), setDataRangeT2(), setDlFrequency(), setDutyCycle(), setDutyCycleTimer(), setFrequency(), setJoinBackoffCntl(), setJoinBackOffTimer(), setJoinDutyCycleTimer(), setNewChannel(), setTxParams(), and TX_PARAMS.

Referenced by LORAReg_InitAS().

void LORAREG_InitSetAttrFnPtrsAU ( void  )

References CHANNEL_ID_STATUS, DATA_RANGE, JOIN_BACK_OFF_TIMER, JOIN_DUTY_CYCLE_TIMER, JOINBACKOFF_CNTL, NEW_CHANNELS, pSetAttr, REG_JOIN_ENABLE_ALL, REG_JOIN_SUCCESS, setChannelIdStatus(), setDataRange(), setEnableAllChs(), setJoinBackoffCntl(), setJoinBackOffTimer(), setJoinDutyCycleTimer(), setJoinSuccess(), and setNewChannelsT1().

Referenced by LORAReg_InitAU().

void LORAREG_InitSetAttrFnPtrsEU ( void  )

References CHANNEL_ID_STATUS, CHLIST_DEFAULTS, DATA_RANGE, DL_FREQUENCY, DUTY_CYCLE, DUTY_CYCLE_TIMER, FREQUENCY, JOIN_BACK_OFF_TIMER, JOIN_DUTY_CYCLE_TIMER, JOINBACKOFF_CNTL, NEW_CHANNELS, pSetAttr, setChannelIdStatusT2(), setChlistDefaultState(), setDataRangeT2(), setDlFrequency(), setDutyCycle(), setDutyCycleTimer(), setFrequency(), setJoinBackoffCntl(), setJoinBackOffTimer(), setJoinDutyCycleTimer(), and setNewChannel().

Referenced by LORAReg_InitEU().

void LORAREG_InitSetAttrFnPtrsIN ( void  )

References CHANNEL_ID_STATUS, CHLIST_DEFAULTS, DATA_RANGE, DL_FREQUENCY, FREQUENCY, JOIN_BACK_OFF_TIMER, JOIN_DUTY_CYCLE_TIMER, JOINBACKOFF_CNTL, NEW_CHANNELS, pSetAttr, setChannelIdStatusT2(), setChlistDefaultState(), setDataRangeT2(), setDlFrequency(), setFrequency(), setJoinBackoffCntl(), setJoinBackOffTimer(), setJoinDutyCycleTimer(), setNewChannel(), setTxParams(), and TX_PARAMS.

Referenced by LORAReg_InitIN().

void LORAREG_InitSetAttrFnPtrsJP ( void  )

References CHANNEL_ID_STATUS, CHLIST_DEFAULTS, DATA_RANGE, DL_FREQUENCY, DUTY_CYCLE, DUTY_CYCLE_TIMER, FREQUENCY, JOIN_BACK_OFF_TIMER, JOIN_DUTY_CYCLE_TIMER, JOINBACKOFF_CNTL, LBT_TIMER, NEW_CHANNELS, pSetAttr, setChannelIdStatusT3(), setChlistDefaultState(), setDataRangeT2(), setDlFrequency(), setDutyCycle(), setDutyCycleTimer(), setFrequency(), setJoinBackoffCntl(), setJoinBackOffTimer(), setJoinDutyCycleTimer(), setLBTTimer(), setNewChannel(), setTxParams(), and TX_PARAMS.

Referenced by LORAReg_InitJP().

void LORAREG_InitSetAttrFnPtrsKR ( void  )

References CHANNEL_ID_STATUS, CHLIST_DEFAULTS, DATA_RANGE, DL_FREQUENCY, FREQUENCY, JOIN_BACK_OFF_TIMER, JOIN_DUTY_CYCLE_TIMER, JOINBACKOFF_CNTL, LBT_TIMER, NEW_CHANNELS, pSetAttr, setChannelIdStatusT3(), setChlistDefaultState(), setDataRangeT2(), setDlFrequency(), setFrequency(), setJoinBackoffCntl(), setJoinBackOffTimer(), setJoinDutyCycleTimer(), setLBTTimer(), setNewChannel(), setTxParams(), and TX_PARAMS.

Referenced by LORAReg_InitKR().

void LORAREG_InitSetAttrFnPtrsNA ( void  )

References CHANNEL_ID_STATUS, DATA_RANGE, JOIN_BACK_OFF_TIMER, JOIN_DUTY_CYCLE_TIMER, JOINBACKOFF_CNTL, NEW_CHANNELS, pSetAttr, REG_JOIN_ENABLE_ALL, REG_JOIN_SUCCESS, setChannelIdStatus(), setDataRange(), setEnableAllChs(), setJoinBackoffCntl(), setJoinBackOffTimer(), setJoinDutyCycleTimer(), setJoinSuccess(), and setNewChannelsT1().

Referenced by LORAReg_InitNA().

void LORAREG_InitValidateAttrFnPtrsAS ( void  )

References CHANNEL_ID, CHANNEL_MASK, CHANNEL_MASK_CNTL, CHMASK_CHCNTL, DATA_RANGE, pValidateAttr, RX1_DATARATE_OFFSET, RX2_DATARATE, RX_DATARATE, RX_FREQUENCY, SUPPORTED_DR, TX_DATARATE, TX_FREQUENCY, TX_PWR, ValidateChannelIdT2(), ValidateChannelMaskCntlT2(), ValidateChannelMaskT2(), ValidateChMaskChCntlT2(), ValidateDataRangeT2(), ValidateDataRateRxT2(), ValidateDataRateTxT2(), ValidateFrequencyAS(), ValidateRx1DataRateOffset(), ValidateSupportedDr(), ValidateTxFreqT2(), and ValidateTxPower().

Referenced by LORAReg_InitAS().

void LORAREG_InitValidateAttrFnPtrsAU ( void  )

References CHANNEL_ID, CHANNEL_MASK, CHANNEL_MASK_CNTL, CHMASK_CHCNTL, DATA_RANGE, pValidateAttr, RX1_DATARATE_OFFSET, RX2_DATARATE, RX_DATARATE, RX_FREQUENCY, SUPPORTED_DR, TX_DATARATE, TX_FREQUENCY, TX_PWR, ValidateChannelId(), ValidateChannelMask(), ValidateChannelMaskCntl(), ValidateChMaskChCntl(), ValidateDataRange(), ValidateDataRateRxT1(), ValidateDataRateTxT1(), ValidateRx1DataRateOffset(), ValidateRxFreqT1(), ValidateSupportedDr(), ValidateTxFreqT1(), and ValidateTxPower().

Referenced by LORAReg_InitAU().

void LORAREG_InitValidateAttrFnPtrsEU ( void  )

References CHANNEL_ID, CHANNEL_MASK, CHANNEL_MASK_CNTL, CHMASK_CHCNTL, DATA_RANGE, pValidateAttr, RX1_DATARATE_OFFSET, RX2_DATARATE, RX_DATARATE, RX_FREQUENCY, SUPPORTED_DR, TX_DATARATE, TX_FREQUENCY, TX_PWR, ValidateChannelIdT2(), ValidateChannelMaskCntlT2(), ValidateChannelMaskT2(), ValidateChMaskChCntlT2(), ValidateDataRangeT2(), ValidateDataRate(), ValidateFreq(), ValidateRx1DataRateOffset(), ValidateSupportedDr(), ValidateTxFreqT2(), and ValidateTxPower().

Referenced by LORAReg_InitEU().

void LORAREG_InitValidateAttrFnPtrsIN ( void  )

References CHANNEL_ID, CHANNEL_MASK, CHANNEL_MASK_CNTL, CHMASK_CHCNTL, DATA_RANGE, pValidateAttr, RX1_DATARATE_OFFSET, RX2_DATARATE, RX_DATARATE, RX_FREQUENCY, SUPPORTED_DR, TX_DATARATE, TX_FREQUENCY, TX_PWR, ValidateChannelIdT2(), ValidateChannelMaskCntlT2(), ValidateChannelMaskT2(), ValidateChMaskChCntlT2(), ValidateDataRangeT2(), ValidateDataRate(), ValidateFreqIN(), ValidateRx1DataRateOffset(), ValidateSupportedDr(), ValidateTxFreqT2(), and ValidateTxPower().

Referenced by LORAReg_InitIN().

void LORAREG_InitValidateAttrFnPtrsJP ( void  )

References CHANNEL_ID, CHANNEL_MASK, CHANNEL_MASK_CNTL, CHMASK_CHCNTL, DATA_RANGE, pValidateAttr, RX1_DATARATE_OFFSET, RX2_DATARATE, RX_DATARATE, RX_FREQUENCY, SUPPORTED_DR, TX_DATARATE, TX_FREQUENCY, TX_PWR, ValidateChannelIdT2(), ValidateChannelMaskCntlT2(), ValidateChannelMaskT2(), ValidateChMaskChCntlT2(), ValidateDataRangeT2(), ValidateDataRateRxT2(), ValidateDataRateTxT2(), ValidateFreqJP(), ValidateRx1DataRateOffset(), ValidateSupportedDr(), ValidateTxFreqT2(), and ValidateTxPower().

Referenced by LORAReg_InitJP().

void LORAREG_InitValidateAttrFnPtrsKR ( void  )

References CHANNEL_ID, CHANNEL_MASK, CHANNEL_MASK_CNTL, CHMASK_CHCNTL, DATA_RANGE, pValidateAttr, RX1_DATARATE_OFFSET, RX2_DATARATE, RX_DATARATE, RX_FREQUENCY, SUPPORTED_DR, TX_DATARATE, TX_FREQUENCY, TX_PWR, ValidateChannelIdT2(), ValidateChannelMaskCntlT2(), ValidateChannelMaskT2(), ValidateChMaskChCntlT2(), ValidateDataRangeT2(), ValidateDataRate(), ValidateFreqKR(), ValidateRx1DataRateOffset(), ValidateSupportedDr(), ValidateTxFreqT2(), and ValidateTxPower().

Referenced by LORAReg_InitKR().

void LORAREG_InitValidateAttrFnPtrsNA ( void  )

References CHANNEL_ID, CHANNEL_MASK, CHANNEL_MASK_CNTL, CHMASK_CHCNTL, DATA_RANGE, pValidateAttr, RX1_DATARATE_OFFSET, RX2_DATARATE, RX_DATARATE, RX_FREQUENCY, SUPPORTED_DR, TX_DATARATE, TX_FREQUENCY, TX_PWR, ValidateChannelId(), ValidateChannelMask(), ValidateChannelMaskCntl(), ValidateChMaskChCntl(), ValidateDataRange(), ValidateDataRateRxT1(), ValidateDataRateTxT1(), ValidateRx1DataRateOffset(), ValidateRxFreqT1(), ValidateSupportedDr(), ValidateTxFreqT1(), and ValidateTxPower().

Referenced by LORAReg_InitNA().

void StopAllRegSoftwareTimers ( void  )

References i, REG_PARAMS_TIMERS_COUNT, regTimerId, and SwTimerStop().

Referenced by LORAREG_Init(), and LORAREG_UnInit().

RegParams_t RegParams

Referenced by InitDefault433Channels(), InitDefault865Channels(), InitDefault868Channels(), InitDefault915Channels(), InitDefault915ChannelsAU(), InitDefault920Channels(), InitDefault920ChannelsKR(), InitDefault923Channels(), LORAReg_InitAS(), LORAReg_InitAU(), LORAReg_InitEU(), LORAReg_InitIN(), LORAReg_InitJP(), LORAReg_InitKR(), and LORAReg_InitNA().

uint8_t regTimerId[REG_PARAMS_TIMERS_COUNT]

Referenced by CreateAllRegSoftwareTimers(), LORAReg_InitAS(), LORAReg_InitAU(), LORAReg_InitEU(), LORAReg_InitIN(), LORAReg_InitJP(), LORAReg_InitKR(), LORAReg_InitNA(), and StopAllRegSoftwareTimers().

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